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reformat converted VHDL

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This commit is contained in:
Markus Fröschle
2016-01-12 07:14:33 +00:00
parent 3ec978dff5
commit 7d2430a62c
5 changed files with 1998 additions and 1800 deletions
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84
FPGA_Quartus_13.1/Video/DDR_CTR.tdf
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@@ -15,45 +15,47 @@ CONSTANT FIFO_HWM = 500;
SUBDESIGN ddr_ctr SUBDESIGN ddr_ctr
( (
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT; FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT; nFB_CS1 : INPUT;
nFB_CS2 : INPUT; nFB_CS2 : INPUT;
nFB_CS3 : INPUT; nFB_CS3 : INPUT;
nFB_OE : INPUT; nFB_OE : INPUT;
FB_SIZE0 : INPUT; FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT; FB_SIZE1 : INPUT;
nRSTO : INPUT; nRSTO : INPUT;
MAIN_CLK : INPUT; MAIN_CLK : INPUT;
FB_ALE : INPUT; FB_ALE : INPUT;
nFB_WR : INPUT; nFB_WR : INPUT;
DDR_SYNC_66M : INPUT; DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT; CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT; VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT; BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT; BLITTER_SIG : INPUT;
BLITTER_WR : INPUT; BLITTER_WR : INPUT;
DDRCLK0 : INPUT; CLK33M : INPUT;
CLK33M : INPUT; FIFO_MW[8..0] : INPUT;
FIFO_MW[8..0] : INPUT;
VA[12..0] : OUTPUT; DDRCLK0 : INPUT;
nVWE : OUTPUT; VA[12..0] : OUTPUT;
nVRAS : OUTPUT; nVWE : OUTPUT;
nVCS : OUTPUT; nVRAS : OUTPUT;
VCKE : OUTPUT; nVCS : OUTPUT;
nVCAS : OUTPUT; VCKE : OUTPUT;
FB_LE[3..0] : OUTPUT; nVCAS : OUTPUT;
FB_VDOE[3..0] : OUTPUT; BA[1..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT; VDM_SEL[3..0] : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT; FB_LE[3..0] : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT; FB_VDOE[3..0] : OUTPUT;
SR_VDMP[7..0] : OUTPUT; SR_FIFO_WRE : OUTPUT;
VIDEO_DDR_TA : OUTPUT; SR_DDR_FB : OUTPUT;
SR_BLITTER_DACK : OUTPUT; SR_DDR_WR : OUTPUT;
BA[1..0] : OUTPUT; SR_DDRWR_D_SEL : OUTPUT;
DDRWR_D_SEL1 : OUTPUT; SR_VDMP[7..0] : OUTPUT;
VDM_SEL[3..0] : OUTPUT; VIDEO_DDR_TA : OUTPUT;
FB_AD[31..0] : BIDIR; SR_BLITTER_DACK : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
) )
@@ -657,10 +659,10 @@ BEGIN
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
% FB_AD[31..24] = lpm_bustri_BYT( FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) VIDEO_BASE_H & (0, VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]),
(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); % (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT( FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[] VIDEO_BASE_L & VIDEO_BASE_L_D[]

2063
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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File diff suppressed because it is too large Load Diff

1261
FPGA_Quartus_13.1/Video/video.vhd
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File diff suppressed because it is too large Load Diff

2
FPGA_Quartus_13.1/firebee1.qsf
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@@ -670,6 +670,7 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
set_global_assignment -name SOURCE_FILE altpll4.cmp set_global_assignment -name SOURCE_FILE altpll4.cmp
@@ -684,7 +685,6 @@ set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
set_global_assignment -name VHDL_FILE Video/mux41_1.vhd set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
set_global_assignment -name VHDL_FILE Video/mux41_0.vhd set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp

24
FPGA_Quartus_13.1/firebee1.sdc
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@@ -133,16 +133,20 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_port
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
# video RAM access # video RAM access
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
#************************************************************** #**************************************************************