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reformat converted VHDL

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This commit is contained in:
Markus Fröschle
2016-01-12 07:14:33 +00:00
parent 3ec978dff5
commit 7d2430a62c
5 changed files with 1998 additions and 1800 deletions
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12
FPGA_Quartus_13.1/Video/DDR_CTR.tdf
View File

@@ -32,15 +32,19 @@ SUBDESIGN ddr_ctr
BLITTER_ADR[31..0] : INPUT; BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT; BLITTER_SIG : INPUT;
BLITTER_WR : INPUT; BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT; CLK33M : INPUT;
FIFO_MW[8..0] : INPUT; FIFO_MW[8..0] : INPUT;
DDRCLK0 : INPUT;
VA[12..0] : OUTPUT; VA[12..0] : OUTPUT;
nVWE : OUTPUT; nVWE : OUTPUT;
nVRAS : OUTPUT; nVRAS : OUTPUT;
nVCS : OUTPUT; nVCS : OUTPUT;
VCKE : OUTPUT; VCKE : OUTPUT;
nVCAS : OUTPUT; nVCAS : OUTPUT;
BA[1..0] : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_LE[3..0] : OUTPUT; FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT; FB_VDOE[3..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT; SR_FIFO_WRE : OUTPUT;
@@ -50,9 +54,7 @@ SUBDESIGN ddr_ctr
SR_VDMP[7..0] : OUTPUT; SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT; VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT; SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT; DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR; FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
) )
@@ -657,10 +659,10 @@ BEGIN
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
% FB_AD[31..24] = lpm_bustri_BYT( FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) VIDEO_BASE_H & (0, VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]),
(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); % (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT( FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[] VIDEO_BASE_L & VIDEO_BASE_L_D[]

1377
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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File diff suppressed because it is too large Load Diff

349
FPGA_Quartus_13.1/Video/video.vhd
View File

@@ -183,36 +183,6 @@ ARCHITECTURE rtl OF video IS
); );
END COMPONENT; END COMPONENT;
COMPONENT blitter
PORT
(
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic;
FB_ALE : IN std_logic;
nFB_WR : IN std_logic;
nFB_OE : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
BLITTER_ON : IN std_logic;
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
DDRCLK0 : IN std_logic;
SR_BLITTER_DACK : IN std_logic;
BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0);
BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0);
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0);
BLITTER_RUN : OUT std_logic;
BLITTER_SIG : OUT std_logic;
BLITTER_WR : OUT std_logic;
BLITTER_TA : OUT std_logic;
BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0);
BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0)
);
END COMPONENT;
COMPONENT ddr_ctr COMPONENT ddr_ctr
PORT PORT
( (
@@ -259,7 +229,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT ddr_ctr; END COMPONENT ddr_ctr;
COMPONENT altdpram1 COMPONENT altdpram1
PORT(wren_a : IN std_logic; PORT
(
wren_a : IN std_logic;
wren_b : IN std_logic; wren_b : IN std_logic;
clock_a : IN std_logic; clock_a : IN std_logic;
clock_b : IN std_logic; clock_b : IN std_logic;
@@ -273,7 +245,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_fifo_dc0 COMPONENT lpm_fifo_dc0
PORT(wrreq : IN std_logic; PORT
(
wrreq : IN std_logic;
wrclk : IN std_logic; wrclk : IN std_logic;
rdreq : IN std_logic; rdreq : IN std_logic;
rdclk : IN std_logic; rdclk : IN std_logic;
@@ -286,7 +260,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT altddio_bidir0 COMPONENT altddio_bidir0
PORT(oe : IN std_logic; PORT
(
oe : IN std_logic;
inclock : IN std_logic; inclock : IN std_logic;
outclock : IN std_logic; outclock : IN std_logic;
datain_h : IN std_logic_vector(31 DOWNTO 0); datain_h : IN std_logic_vector(31 DOWNTO 0);
@@ -299,14 +275,18 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff4 COMPONENT lpm_ff4
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data : IN std_logic_vector(15 DOWNTO 0); data : IN std_logic_vector(15 DOWNTO 0);
q : OUT std_logic_vector(15 DOWNTO 0) q : OUT std_logic_vector(15 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_muxvdm COMPONENT lpm_muxvdm
PORT(data0x : IN std_logic_vector(127 DOWNTO 0); PORT
(
data0x : IN std_logic_vector(127 DOWNTO 0);
data10x : IN std_logic_vector(127 DOWNTO 0); data10x : IN std_logic_vector(127 DOWNTO 0);
data11x : IN std_logic_vector(127 DOWNTO 0); data11x : IN std_logic_vector(127 DOWNTO 0);
data12x : IN std_logic_vector(127 DOWNTO 0); data12x : IN std_logic_vector(127 DOWNTO 0);
@@ -328,7 +308,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux3 COMPONENT lpm_mux3
PORT(data1 : IN std_logic; PORT
(
data1 : IN std_logic;
data0 : IN std_logic; data0 : IN std_logic;
sel : IN std_logic; sel : IN std_logic;
result : OUT std_logic result : OUT std_logic
@@ -336,28 +318,36 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_bustri_long COMPONENT lpm_bustri_long
PORT(enabledt : IN std_logic; PORT
(
enabledt : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0); data : IN std_logic_vector(31 DOWNTO 0);
tridata : INOUT std_logic_vector(31 DOWNTO 0) tridata : INOUT std_logic_vector(31 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff5 COMPONENT lpm_ff5
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data : IN std_logic_vector(7 DOWNTO 0); data : IN std_logic_vector(7 DOWNTO 0);
q : OUT std_logic_vector(7 DOWNTO 0) q : OUT std_logic_vector(7 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff1 COMPONENT lpm_ff1
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0); data : IN std_logic_vector(31 DOWNTO 0);
q : OUT std_logic_vector(31 DOWNTO 0) q : OUT std_logic_vector(31 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff0 COMPONENT lpm_ff0
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
enable : IN std_logic; enable : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0); data : IN std_logic_vector(31 DOWNTO 0);
q : OUT std_logic_vector(31 DOWNTO 0) q : OUT std_logic_vector(31 DOWNTO 0)
@@ -365,7 +355,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT altddio_out0 COMPONENT altddio_out0
PORT(outclock : IN std_logic; PORT
(
outclock : IN std_logic;
datain_h : IN std_logic_vector(3 DOWNTO 0); datain_h : IN std_logic_vector(3 DOWNTO 0);
datain_l : IN std_logic_vector(3 DOWNTO 0); datain_l : IN std_logic_vector(3 DOWNTO 0);
dataout : OUT std_logic_vector(3 DOWNTO 0) dataout : OUT std_logic_vector(3 DOWNTO 0)
@@ -373,7 +365,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux0 COMPONENT lpm_mux0
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data0x : IN std_logic_vector(31 DOWNTO 0); data0x : IN std_logic_vector(31 DOWNTO 0);
data1x : IN std_logic_vector(31 DOWNTO 0); data1x : IN std_logic_vector(31 DOWNTO 0);
data2x : IN std_logic_vector(31 DOWNTO 0); data2x : IN std_logic_vector(31 DOWNTO 0);
@@ -384,7 +378,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux5 COMPONENT lpm_mux5
PORT(data0x : IN std_logic_vector(63 DOWNTO 0); PORT
(
data0x : IN std_logic_vector(63 DOWNTO 0);
data1x : IN std_logic_vector(63 DOWNTO 0); data1x : IN std_logic_vector(63 DOWNTO 0);
data2x : IN std_logic_vector(63 DOWNTO 0); data2x : IN std_logic_vector(63 DOWNTO 0);
data3x : IN std_logic_vector(63 DOWNTO 0); data3x : IN std_logic_vector(63 DOWNTO 0);
@@ -394,12 +390,16 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_constant2 COMPONENT lpm_constant2
PORT( result : OUT std_logic_vector(7 DOWNTO 0) PORT
(
result : OUT std_logic_vector(7 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux1 COMPONENT lpm_mux1
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data0x : IN std_logic_vector(15 DOWNTO 0); data0x : IN std_logic_vector(15 DOWNTO 0);
data1x : IN std_logic_vector(15 DOWNTO 0); data1x : IN std_logic_vector(15 DOWNTO 0);
data2x : IN std_logic_vector(15 DOWNTO 0); data2x : IN std_logic_vector(15 DOWNTO 0);
@@ -414,7 +414,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux2 COMPONENT lpm_mux2
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data0x : IN std_logic_vector(7 DOWNTO 0); data0x : IN std_logic_vector(7 DOWNTO 0);
data10x : IN std_logic_vector(7 DOWNTO 0); data10x : IN std_logic_vector(7 DOWNTO 0);
data11x : IN std_logic_vector(7 DOWNTO 0); data11x : IN std_logic_vector(7 DOWNTO 0);
@@ -437,21 +439,27 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_shiftreg4 COMPONENT lpm_shiftreg4
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
shiftin : IN std_logic; shiftin : IN std_logic;
shiftout : OUT std_logic shiftout : OUT std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_latch0 COMPONENT lpm_latch0
PORT(gate : IN std_logic; PORT
(
gate : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0); data : IN std_logic_vector(31 DOWNTO 0);
q : OUT std_logic_vector(31 DOWNTO 0) q : OUT std_logic_vector(31 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff6 COMPONENT lpm_ff6
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
enable : IN std_logic; enable : IN std_logic;
data : IN std_logic_vector(127 DOWNTO 0); data : IN std_logic_vector(127 DOWNTO 0);
q : OUT std_logic_vector(127 DOWNTO 0) q : OUT std_logic_vector(127 DOWNTO 0)
@@ -459,14 +467,18 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_ff3 COMPONENT lpm_ff3
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data : IN std_logic_vector(23 DOWNTO 0); data : IN std_logic_vector(23 DOWNTO 0);
q : OUT std_logic_vector(23 DOWNTO 0) q : OUT std_logic_vector(23 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT altddio_out2 COMPONENT altddio_out2
PORT(outclock : IN std_logic; PORT
(
outclock : IN std_logic;
datain_h : IN std_logic_vector(23 DOWNTO 0); datain_h : IN std_logic_vector(23 DOWNTO 0);
datain_l : IN std_logic_vector(23 DOWNTO 0); datain_l : IN std_logic_vector(23 DOWNTO 0);
dataout : OUT std_logic_vector(23 DOWNTO 0) dataout : OUT std_logic_vector(23 DOWNTO 0)
@@ -474,26 +486,34 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_bustri1 COMPONENT lpm_bustri1
PORT(enabledt : IN std_logic; PORT
(
enabledt : IN std_logic;
data : IN std_logic_vector(2 DOWNTO 0); data : IN std_logic_vector(2 DOWNTO 0);
tridata : INOUT std_logic_vector(2 DOWNTO 0) tridata : INOUT std_logic_vector(2 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_bustri_byt COMPONENT lpm_bustri_byt
PORT(enabledt : IN std_logic; PORT
(
enabledt : IN std_logic;
data : IN std_logic_vector(7 DOWNTO 0); data : IN std_logic_vector(7 DOWNTO 0);
tridata : INOUT std_logic_vector(7 DOWNTO 0) tridata : INOUT std_logic_vector(7 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_constant0 COMPONENT lpm_constant0
PORT( result : OUT std_logic_vector(4 DOWNTO 0) PORT
(
result : OUT std_logic_vector(4 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_muxdz COMPONENT lpm_muxdz
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
clken : IN std_logic; clken : IN std_logic;
sel : IN std_logic; sel : IN std_logic;
data0x : IN std_logic_vector(127 DOWNTO 0); data0x : IN std_logic_vector(127 DOWNTO 0);
@@ -503,7 +523,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_fifodz COMPONENT lpm_fifodz
PORT(wrreq : IN std_logic; PORT
(
wrreq : IN std_logic;
rdreq : IN std_logic; rdreq : IN std_logic;
clock : IN std_logic; clock : IN std_logic;
aclr : IN std_logic; aclr : IN std_logic;
@@ -513,14 +535,18 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_bustri3 COMPONENT lpm_bustri3
PORT(enabledt : IN std_logic; PORT
(
enabledt : IN std_logic;
data : IN std_logic_vector(5 DOWNTO 0); data : IN std_logic_vector(5 DOWNTO 0);
tridata : INOUT std_logic_vector(5 DOWNTO 0) tridata : INOUT std_logic_vector(5 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux6 COMPONENT lpm_mux6
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
data0x : IN std_logic_vector(23 DOWNTO 0); data0x : IN std_logic_vector(23 DOWNTO 0);
data1x : IN std_logic_vector(23 DOWNTO 0); data1x : IN std_logic_vector(23 DOWNTO 0);
data2x : IN std_logic_vector(23 DOWNTO 0); data2x : IN std_logic_vector(23 DOWNTO 0);
@@ -535,12 +561,16 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_constant1 COMPONENT lpm_constant1
PORT( result : OUT std_logic_vector(1 DOWNTO 0) PORT
(
result : OUT std_logic_vector(1 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_mux4 COMPONENT lpm_mux4
PORT(sel : IN std_logic; PORT
(
sel : IN std_logic;
data0x : IN std_logic_vector(6 DOWNTO 0); data0x : IN std_logic_vector(6 DOWNTO 0);
data1x : IN std_logic_vector(6 DOWNTO 0); data1x : IN std_logic_vector(6 DOWNTO 0);
result : OUT std_logic_vector(6 DOWNTO 0) result : OUT std_logic_vector(6 DOWNTO 0)
@@ -548,19 +578,25 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT lpm_constant3 COMPONENT lpm_constant3
PORT( result : OUT std_logic_vector(6 DOWNTO 0) PORT
(
result : OUT std_logic_vector(6 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_shiftreg6 COMPONENT lpm_shiftreg6
PORT(clock : IN std_logic; PORT
(
clock : IN std_logic;
shiftin : IN std_logic; shiftin : IN std_logic;
q : OUT std_logic_vector(4 DOWNTO 0) q : OUT std_logic_vector(4 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lpm_shiftreg0 COMPONENT lpm_shiftreg0
PORT(load : IN std_logic; PORT
(
load : IN std_logic;
clock : IN std_logic; clock : IN std_logic;
shiftin : IN std_logic; shiftin : IN std_logic;
data : IN std_logic_vector(15 DOWNTO 0); data : IN std_logic_vector(15 DOWNTO 0);
@@ -569,7 +605,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT altdpram0 COMPONENT altdpram0
PORT(wren_a : IN std_logic; PORT
(
wren_a : IN std_logic;
wren_b : IN std_logic; wren_b : IN std_logic;
clock_a : IN std_logic; clock_a : IN std_logic;
clock_b : IN std_logic; clock_b : IN std_logic;
@@ -583,7 +621,9 @@ ARCHITECTURE rtl OF video IS
END COMPONENT; END COMPONENT;
COMPONENT video_mod_mux_clutctr COMPONENT video_mod_mux_clutctr
PORT(nRSTO : IN std_logic; PORT
(
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic; MAIN_CLK : IN std_logic;
nFB_CS1 : IN std_logic; nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic; nFB_CS2 : IN std_logic;
@@ -806,38 +846,32 @@ BEGIN
SYNTHESIZED_WIRE_56 <= '0'; SYNTHESIZED_WIRE_56 <= '0';
SYNTHESIZED_WIRE_57 <= '0'; SYNTHESIZED_WIRE_57 <= '0';
CC16(18) <= GDFX_TEMP_SIGNAL_16(7);
CC16(17) <= GDFX_TEMP_SIGNAL_16(6);
CC16(16) <= GDFX_TEMP_SIGNAL_16(5);
CC16(9) <= GDFX_TEMP_SIGNAL_16(4);
CC16(8) <= GDFX_TEMP_SIGNAL_16(3);
CC16(2) <= GDFX_TEMP_SIGNAL_16(2);
CC16(1) <= GDFX_TEMP_SIGNAL_16(1);
CC16(0) <= GDFX_TEMP_SIGNAL_16(0);
CC16(23) <= GDFX_TEMP_SIGNAL_0(15); CC16(23) <= GDFX_TEMP_SIGNAL_0(15);
CC16(22) <= GDFX_TEMP_SIGNAL_0(14); CC16(22) <= GDFX_TEMP_SIGNAL_0(14);
CC16(21) <= GDFX_TEMP_SIGNAL_0(13); CC16(21) <= GDFX_TEMP_SIGNAL_0(13);
CC16(20) <= GDFX_TEMP_SIGNAL_0(12); CC16(20) <= GDFX_TEMP_SIGNAL_0(12);
CC16(19) <= GDFX_TEMP_SIGNAL_0(11); CC16(19) <= GDFX_TEMP_SIGNAL_0(11);
CC16(18) <= GDFX_TEMP_SIGNAL_16(7);
CC16(17) <= GDFX_TEMP_SIGNAL_16(6);
CC16(16) <= GDFX_TEMP_SIGNAL_16(5);
CC16(15) <= GDFX_TEMP_SIGNAL_0(10); CC16(15) <= GDFX_TEMP_SIGNAL_0(10);
CC16(14) <= GDFX_TEMP_SIGNAL_0(9); CC16(14) <= GDFX_TEMP_SIGNAL_0(9);
CC16(13) <= GDFX_TEMP_SIGNAL_0(8); CC16(13) <= GDFX_TEMP_SIGNAL_0(8);
CC16(12) <= GDFX_TEMP_SIGNAL_0(7); CC16(12) <= GDFX_TEMP_SIGNAL_0(7);
CC16(11) <= GDFX_TEMP_SIGNAL_0(6); CC16(11) <= GDFX_TEMP_SIGNAL_0(6);
CC16(10) <= GDFX_TEMP_SIGNAL_0(5); CC16(10) <= GDFX_TEMP_SIGNAL_0(5);
CC16(9) <= GDFX_TEMP_SIGNAL_16(4);
CC16(8) <= GDFX_TEMP_SIGNAL_16(3);
CC16(7) <= GDFX_TEMP_SIGNAL_0(4); CC16(7) <= GDFX_TEMP_SIGNAL_0(4);
CC16(6) <= GDFX_TEMP_SIGNAL_0(3); CC16(6) <= GDFX_TEMP_SIGNAL_0(3);
CC16(5) <= GDFX_TEMP_SIGNAL_0(2); CC16(5) <= GDFX_TEMP_SIGNAL_0(2);
CC16(4) <= GDFX_TEMP_SIGNAL_0(1); CC16(4) <= GDFX_TEMP_SIGNAL_0(1);
CC16(3) <= GDFX_TEMP_SIGNAL_0(0); CC16(3) <= GDFX_TEMP_SIGNAL_0(0);
CC16(2) <= GDFX_TEMP_SIGNAL_16(2);
CC16(1) <= GDFX_TEMP_SIGNAL_16(1);
CC16(0) <= GDFX_TEMP_SIGNAL_16(0);
GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8));
GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16));
GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24));
GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32));
GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40));
GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48));
GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56));
GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64));
GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72));
@@ -847,10 +881,18 @@ BEGIN
GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104));
GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112));
GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120));
GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8));
GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16));
GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24));
GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32));
GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40));
GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48));
ACP_CLUT_RAM : altdpram2 ACP_CLUT_RAM : altdpram2
PORT MAP(wren_a => ACP_CLUT_WR(3), PORT MAP
(
wren_a => ACP_CLUT_WR(3),
wren_b => SYNTHESIZED_WIRE_0, wren_b => SYNTHESIZED_WIRE_0,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -859,11 +901,14 @@ BEGIN
data_a => FB_AD(7 DOWNTO 0), data_a => FB_AD(7 DOWNTO 0),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_30, q_a => SYNTHESIZED_WIRE_30,
q_b => CCA(7 DOWNTO 0)); q_b => CCA(7 DOWNTO 0)
);
ACP_CLUT_RAM54 : altdpram2 ACP_CLUT_RAM54 : altdpram2
PORT MAP(wren_a => ACP_CLUT_WR(2), PORT MAP
(
wren_a => ACP_CLUT_WR(2),
wren_b => SYNTHESIZED_WIRE_1, wren_b => SYNTHESIZED_WIRE_1,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -872,11 +917,14 @@ BEGIN
data_a => FB_AD(15 DOWNTO 8), data_a => FB_AD(15 DOWNTO 8),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_32, q_a => SYNTHESIZED_WIRE_32,
q_b => CCA(15 DOWNTO 8)); q_b => CCA(15 DOWNTO 8)
);
ACP_CLUT_RAM55 : altdpram2 ACP_CLUT_RAM55 : altdpram2
PORT MAP(wren_a => ACP_CLUT_WR(1), PORT MAP
(
wren_a => ACP_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_2, wren_b => SYNTHESIZED_WIRE_2,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -885,11 +933,14 @@ BEGIN
data_a => FB_AD(23 DOWNTO 16), data_a => FB_AD(23 DOWNTO 16),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_33, q_a => SYNTHESIZED_WIRE_33,
q_b => CCA(23 DOWNTO 16)); q_b => CCA(23 DOWNTO 16)
);
i_blitter : blitter i_blitter : work.blitter
PORT MAP(nRSTO => nRSTO, PORT MAP
(
nRSTO => nRSTO,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
FB_ALE => FB_ALE, FB_ALE => FB_ALE,
nFB_WR => nFB_WR, nFB_WR => nFB_WR,
@@ -912,11 +963,14 @@ BEGIN
BLITTER_WR => BLITTER_WR, BLITTER_WR => BLITTER_WR,
BLITTER_TA => BLITTER_TA, BLITTER_TA => BLITTER_TA,
BLITTER_ADR => BLITTER_ADR, BLITTER_ADR => BLITTER_ADR,
BLITTER_DOUT => BLITTER_DOUT); BLITTER_DOUT => BLITTER_DOUT
);
i_ddr_ctr : ddr_ctr i_ddr_ctr : ddr_ctr
PORT MAP(nFB_CS1 => nFB_CS1, PORT MAP
(
nFB_CS1 => nFB_CS1,
nFB_CS2 => nFB_CS2, nFB_CS2 => nFB_CS2,
nFB_CS3 => nFB_CS3, nFB_CS3 => nFB_CS3,
nFB_OE => nFB_OE, nFB_OE => nFB_OE,
@@ -954,11 +1008,14 @@ BEGIN
FB_VDOE => FB_VDOE, FB_VDOE => FB_VDOE,
SR_VDMP => SR_VDMP, SR_VDMP => SR_VDMP,
VA => VA, VA => VA,
VDM_SEL => VDM_SEL); VDM_SEL => VDM_SEL
);
FALCON_CLUT_BLUE : altdpram1 FALCON_CLUT_BLUE : altdpram1
PORT MAP(wren_a => FALCON_CLUT_WR(3), PORT MAP
(
wren_a => FALCON_CLUT_WR(3),
wren_b => SYNTHESIZED_WIRE_3, wren_b => SYNTHESIZED_WIRE_3,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -967,11 +1024,14 @@ BEGIN
data_a => FB_AD(23 DOWNTO 18), data_a => FB_AD(23 DOWNTO 18),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_45, q_a => SYNTHESIZED_WIRE_45,
q_b => CCF(7 DOWNTO 2)); q_b => CCF(7 DOWNTO 2)
);
FALCON_CLUT_GREEN : altdpram1 FALCON_CLUT_GREEN : altdpram1
PORT MAP(wren_a => FALCON_CLUT_WR(1), PORT MAP
(
wren_a => FALCON_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_4, wren_b => SYNTHESIZED_WIRE_4,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -980,11 +1040,14 @@ BEGIN
data_a => FB_AD(23 DOWNTO 18), data_a => FB_AD(23 DOWNTO 18),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_44, q_a => SYNTHESIZED_WIRE_44,
q_b => CCF(15 DOWNTO 10)); q_b => CCF(15 DOWNTO 10)
);
FALCON_CLUT_RED : altdpram1 FALCON_CLUT_RED : altdpram1
PORT MAP(wren_a => FALCON_CLUT_WR(0), PORT MAP
(
wren_a => FALCON_CLUT_WR(0),
wren_b => SYNTHESIZED_WIRE_5, wren_b => SYNTHESIZED_WIRE_5,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -993,22 +1056,28 @@ BEGIN
data_a => FB_AD(31 DOWNTO 26), data_a => FB_AD(31 DOWNTO 26),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_41, q_a => SYNTHESIZED_WIRE_41,
q_b => CCF(23 DOWNTO 18)); q_b => CCF(23 DOWNTO 18)
);
inst : lpm_fifo_dc0 inst : lpm_fifo_dc0
PORT MAP(wrreq => FIFO_WRE, PORT MAP
(
wrreq => FIFO_WRE,
wrclk => DDRCLK(0), wrclk => DDRCLK(0),
rdreq => SYNTHESIZED_WIRE_60, rdreq => SYNTHESIZED_WIRE_60,
rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED,
aclr => CLR_FIFO, aclr => CLR_FIFO,
data => VDMC, data => VDMC,
q => SYNTHESIZED_WIRE_63, q => SYNTHESIZED_WIRE_63,
wrusedw => FIFO_MW); wrusedw => FIFO_MW
);
inst1 : altddio_bidir0 inst1 : altddio_bidir0
PORT MAP(oe => VDOUT_OE, PORT MAP
(
oe => VDOUT_OE,
inclock => DDRCLK(1), inclock => DDRCLK(1),
outclock => DDRCLK(3), outclock => DDRCLK(3),
datain_h => VDP_OUT(63 DOWNTO 32), datain_h => VDP_OUT(63 DOWNTO 32),
@@ -1016,17 +1085,23 @@ BEGIN
padio => VD, padio => VD,
combout => SYNTHESIZED_WIRE_15, combout => SYNTHESIZED_WIRE_15,
dataout_h => VDP_IN(31 DOWNTO 0), dataout_h => VDP_IN(31 DOWNTO 0),
dataout_l => VDP_IN(63 DOWNTO 32)); dataout_l => VDP_IN(63 DOWNTO 32)
);
inst10 : lpm_ff4 inst10 : lpm_ff4
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => SYNTHESIZED_WIRE_7, data => SYNTHESIZED_WIRE_7,
q => GDFX_TEMP_SIGNAL_0); q => GDFX_TEMP_SIGNAL_0
);
inst100 : lpm_muxvdm inst100 : lpm_muxvdm
PORT MAP(data0x => VDMB, PORT MAP
(
data0x => VDMB,
data10x => GDFX_TEMP_SIGNAL_1, data10x => GDFX_TEMP_SIGNAL_1,
data11x => GDFX_TEMP_SIGNAL_2, data11x => GDFX_TEMP_SIGNAL_2,
data12x => GDFX_TEMP_SIGNAL_3, data12x => GDFX_TEMP_SIGNAL_3,
@@ -1043,14 +1118,18 @@ BEGIN
data8x => GDFX_TEMP_SIGNAL_14, data8x => GDFX_TEMP_SIGNAL_14,
data9x => GDFX_TEMP_SIGNAL_15, data9x => GDFX_TEMP_SIGNAL_15,
sel => VDM_SEL, sel => VDM_SEL,
result => VDMC); result => VDMC
);
inst102 : lpm_mux3 inst102 : lpm_mux3
PORT MAP(data1 => DFF_inst93, PORT MAP
(
data1 => DFF_inst93,
data0 => ZR_C8(0), data0 => ZR_C8(0),
sel => COLOR1, sel => COLOR1,
result => ZR_C8B(0)); result => ZR_C8B(0)
);
@@ -1063,53 +1142,77 @@ BEGIN
inst108 : lpm_bustri_long inst108 : lpm_bustri_long
PORT MAP(enabledt => FB_VDOE(0), PORT MAP
(
enabledt => FB_VDOE(0),
data => VDR, data => VDR,
tridata => FB_AD); tridata => FB_AD
);
inst109 : lpm_bustri_long inst109 : lpm_bustri_long
PORT MAP(enabledt => FB_VDOE(1), PORT MAP
(
enabledt => FB_VDOE(1),
data => SYNTHESIZED_WIRE_11, data => SYNTHESIZED_WIRE_11,
tridata => FB_AD); tridata => FB_AD
);
inst11 : lpm_ff5 inst11 : lpm_ff5
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => SYNTHESIZED_WIRE_12, data => SYNTHESIZED_WIRE_12,
q => ZR_C8); q => ZR_C8
);
inst110 : lpm_bustri_long inst110 : lpm_bustri_long
PORT MAP(enabledt => FB_VDOE(2), PORT MAP
(
enabledt => FB_VDOE(2),
data => SYNTHESIZED_WIRE_13, data => SYNTHESIZED_WIRE_13,
tridata => FB_AD); tridata => FB_AD
);
inst119 : lpm_bustri_long inst119 : lpm_bustri_long
PORT MAP(enabledt => FB_VDOE(3), PORT MAP
(
enabledt => FB_VDOE(3),
data => SYNTHESIZED_WIRE_14, data => SYNTHESIZED_WIRE_14,
tridata => FB_AD); tridata => FB_AD
);
inst12 : lpm_ff1 inst12 : lpm_ff1
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
data => VDP_IN(31 DOWNTO 0), data => VDP_IN(31 DOWNTO 0),
q => VDVZ(31 DOWNTO 0)); q => VDVZ(31 DOWNTO 0)
);
inst13 : lpm_ff0 inst13 : lpm_ff0
PORT MAP(clock => DDR_SYNC_66M, PORT MAP
(
clock => DDR_SYNC_66M,
enable => FB_LE(0), enable => FB_LE(0),
data => FB_AD, data => FB_AD,
q => FB_DDR(127 DOWNTO 96)); q => FB_DDR(127 DOWNTO 96)
);
inst14 : lpm_ff0 inst14 : lpm_ff0
PORT MAP(clock => DDR_SYNC_66M, PORT MAP
(
clock => DDR_SYNC_66M,
enable => FB_LE(1), enable => FB_LE(1),
data => FB_AD, data => FB_AD,
q => FB_DDR(95 DOWNTO 64)); q => FB_DDR(95 DOWNTO 64)
);
inst15 : lpm_ff0 inst15 : lpm_ff0

2
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -670,6 +670,7 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
set_global_assignment -name SOURCE_FILE altpll4.cmp set_global_assignment -name SOURCE_FILE altpll4.cmp
@@ -684,7 +685,6 @@ set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
set_global_assignment -name VHDL_FILE Video/mux41_1.vhd set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
set_global_assignment -name VHDL_FILE Video/mux41_0.vhd set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp

24
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -133,16 +133,20 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_port
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
# video RAM access # video RAM access
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
#************************************************************** #**************************************************************