ragnar/FPGA_Config
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rename video registers to their Falcon names

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This commit is contained in:
Markus Fröschle
2016-01-09 18:49:18 +00:00
parent 5c933580a2
commit 7bdeac0860
5 changed files with 819 additions and 529 deletions
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26
FPGA_Quartus_13.1/Video/DDR_CTR.tdf
View File

@@ -202,7 +202,7 @@ BEGIN
END CASE; END CASE;
-- DDR STEUERUNG ----------------------------------------------------- -- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0; VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1; nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2; DDR_REFRESH_ON = VIDEO_RAM_CTR2;
@@ -230,10 +230,10 @@ BEGIN
DDR_CS.ENA = FB_ALE; DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL; DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<EFBFBD>TER -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<EFBFBD>TER # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER
CPU_REQ.CLK = DDR_SYNC_66M; CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
@@ -350,7 +350,7 @@ BEGIN
CPU_AC = CPU_AC; CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC; BLITTER_AC = BLITTER_AC;
VCAS = VCC; VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<EFBFBD>R CPU SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R; DDR_SM = DS_T5R;
@@ -359,7 +359,7 @@ BEGIN
BLITTER_AC = BLITTER_AC; BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[]; VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE VA_S[10] = GND; -- MANUELL PRECHARGE
BA_S[] = FIFO_BA[]; BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F; DDR_SM = DS_T6F;
ELSE ELSE
@@ -393,7 +393,7 @@ BEGIN
VCAS = VCC; VCAS = VCC;
VWE = VCC; VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<EFBFBD>LFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W; DDR_SM = DS_T7W;
@@ -401,7 +401,7 @@ BEGIN
CPU_AC = CPU_AC; CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC; BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<EFBFBD>LFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W; DDR_SM = DS_T8W;
WHEN DS_T8W => WHEN DS_T8W =>
@@ -536,12 +536,12 @@ BEGIN
-- CLOSE FIFO BANK -- CLOSE FIFO BANK
WHEN DS_CB6 => WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<EFBFBD>NKE SCHLIESSEN VRAS = VCC; -- BÄNKE SCHLIESSEN
VWE = VCC; VWE = VCC;
DDR_SM = DS_N7; DDR_SM = DS_N7;
WHEN DS_CB8 => WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<EFBFBD>NKE SCHLIESSEN VRAS = VCC; -- BÄNKE SCHLIESSEN
VWE = VCC; VWE = VCC;
DDR_SM = DS_T1; DDR_SM = DS_T1;
@@ -599,14 +599,14 @@ BEGIN
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00"); FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0; FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK; FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<EFBFBD>HLER R<EFBFBD>CKSETZEN WENN CLR FIFO ---------------- -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0; CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0; CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE; CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0; STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT; STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<EFBFBD>HLEN ----------------------------------------------- -- ZÄHLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0; VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT; VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
@@ -623,12 +623,12 @@ BEGIN
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
----------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M; DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<EFBFBD>HLEN 0-2047 DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0; REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0; DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<EFBFBD>CK (8 REFRESH UND 1 ALS VORLAUF) DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0; DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;

638
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -93,15 +93,15 @@ VARIABLE
ACP_VIDEO_ON :NODE; ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE; SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE; SYS_CTR_CS :NODE;
VDL_LOF[15..0] :DFFE; LOF[15..0] :DFFE;
VDL_LOF_CS :NODE; LOF_CS :NODE;
VDL_LWD[15..0] :DFFE; LWD[15..0] :DFFE;
VDL_LWD_CS :NODE; LWD_CS :NODE;
-- DIV. CONTROL REGISTER -- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF; HSYNC :DFF;
HSYNC_I[7..0] :DFF; HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<EFBFBD>NGE HSYNC PULS IN PIXEL_CLK HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF; HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF; VSYNC :DFF;
@@ -113,9 +113,9 @@ VARIABLE
DPO_ON :DFF; DPO_ON :DFF;
DPO_OFF :DFF; DPO_OFF :DFF;
VDTRON :DFF; VDTRON :DFF;
VDO_ZL :DFFE; VCO_ZL :DFFE;
VDO_ON :DFF; VCO_ON :DFF;
VDO_OFF :DFF; VCO_OFF :DFF;
VHCNT[11..0] :DFF; VHCNT[11..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE; SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE; VVCNT[10..0] :DFFE;
@@ -150,18 +150,18 @@ VARIABLE
H_TOTAL[11..0] :NODE; H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE; HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE; MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE; HHT[11..0] :DFFE;
VDL_HHT_CS :NODE; HHT_CS :NODE;
VDL_HBE[11..0] :DFFE; HBE[11..0] :DFFE;
VDL_HBE_CS :NODE; HBE_CS :NODE;
VDL_HDB[11..0] :DFFE; HDB[11..0] :DFFE;
VDL_HDB_CS :NODE; HDB_CS :NODE;
VDL_HDE[11..0] :DFFE; HDE[11..0] :DFFE;
VDL_HDE_CS :NODE; HDE_CS :NODE;
VDL_HBB[11..0] :DFFE; HBB[11..0] :DFFE;
VDL_HBB_CS :NODE; HBB_CS :NODE;
VDL_HSS[11..0] :DFFE; HSS[11..0] :DFFE;
VDL_HSS_CS :NODE; HSS_CS :NODE;
-- VERTIKAL -- VERTIKAL
RAND_OBEN[10..0] :NODE; RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE; VDIS_START[10..0] :NODE;
@@ -175,22 +175,22 @@ VARIABLE
DOP_ZEI :DFF; DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF; DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE; VBE[10..0] :DFFE;
VDL_VBE_CS :NODE; VBE_CS :NODE;
VDL_VDB[10..0] :DFFE; VDB[10..0] :DFFE;
VDL_VDB_CS :NODE; VDB_CS :NODE;
VDL_VDE[10..0] :DFFE; VDE[10..0] :DFFE;
VDL_VDE_CS :NODE; VDE_CS :NODE;
VDL_VBB[10..0] :DFFE; VBB[10..0] :DFFE;
VDL_VBB_CS :NODE; VBB_CS :NODE;
VDL_VSS[10..0] :DFFE; VSS[10..0] :DFFE;
VDL_VSS_CS :NODE; VSS_CS :NODE;
VDL_VFT[10..0] :DFFE; VFT[10..0] :DFFE;
VDL_VFT_CS :NODE; VFT_CS :NODE;
VDL_VCT[8..0] :DFFE; VCO[8..0] :DFFE;
VDL_VCT_CS :NODE; VCO_CS :NODE;
VDL_VMD[3..0] :DFFE; VCNTRL[3..0] :DFFE;
VDL_VMD_CS :NODE; VCNTRL_CS :NODE;
BEGIN BEGIN
-- BYT SELECT 32 BIT -- BYT SELECT 32 BIT
@@ -242,7 +242,21 @@ BEGIN
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
-- ACP VIDEO CONTROL
-- BIT 0 = ACP VIDEO ON
-- BIT 1 = POWER ON VIDEO DAC
-- BIT 2 = ACP 24BIT
-- BIT 3 = ACP 16BIT
-- BIT 4 = ACP 8BIT
-- BIT 5 = ACP 1BIT
-- BIT 6 = FALCON SHIFT MODE
-- BIT 7 = ST SHIFT MODE
-- BIT 9..8 = VCLK FREQUENZ
-- BIT 15 =-SYNC ALLOWED
-- BIT 31..16 = VIDEO_RAM_CTR
-- BIT 25 = RANDFARBE EINSCHALTEN
-- BIT 26 = STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8]; ACP_VCTR[31..8] = FB_AD[31..8];
@@ -254,41 +268,46 @@ BEGIN
ACP_VIDEO_ON = ACP_VCTR0; ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1; nPD_VGA = ACP_VCTR1;
-- ATARI MODUS -- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<EFBFBD>SUNG ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG
-- HORIZONTAL TIMING 640x480 -- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK; ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2] == H"104"; -- $410/4
ATARI_HH[] = FB_AD[]; ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480 -- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK; ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2] == H"105"; -- $414/4
ATARI_VH[] = FB_AD[]; ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240 -- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK; ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2] == H"106"; -- $418/4
ATARI_HL[] = FB_AD[]; ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240 -- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK; ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2] == H"107"; -- $41C/4
ATARI_VL[] = FB_AD[]; ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG -- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9] == H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK; VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
@@ -296,10 +315,11 @@ BEGIN
VR_DOUT[].ENA = !VR_BUSY; VR_DOUT[].ENA = !VR_BUSY;
VR_DOUT[] = VR_D[]; VR_DOUT[] = VR_D[];
VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0] == H"04";
VR_FRQ[] = FB_AD[23..16]; VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG -- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0] == H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------
@@ -310,6 +330,7 @@ BEGIN
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
@@ -325,6 +346,7 @@ BEGIN
# B"101" & COLOR16 # B"101" & COLOR16
# B"110" & COLOR24 # B"110" & COLOR24
# B"111" & RAND_ON; # B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ---------------------------- -- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE -- RANDFARBE
CCR[].CLK = MAIN_CLK; CCR[].CLK = MAIN_CLK;
@@ -333,282 +355,351 @@ BEGIN
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 -- System Config Register
-- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi
-- ||||||||
-- |||||||+- RAM Wait Status
-- ||||||| 0 = 1 Wait (default)
-- ||||||| 1 = 0 Wait
-- ||||||+-- Video Bus Width
-- |||||| 0 = 16 Bit
-- |||||| 1 = 32 Bit (default)
-- ||||++--- ROM Wait Status
-- |||| 00 = reserved
-- |||| 01 = 2 Wait (default)
-- |||| 10 = 1 Wait
-- |||| 11 = 0 Wait
-- ||++----- Main Memory Size
-- || 01 = 4 MB
-- || 10 = 16 MB
-- ++------- Monitor Type
-- 00 Monochrome
-- 01 RGB
-- 10 VGA
-- 11 TV
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3; BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 -- LOF
VDL_LOF[].CLK = MAIN_CLK; LOF_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C107"; -- $820E/2
VDL_LOF[] = FB_AD[31..16]; LOF[].CLK = MAIN_CLK;
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; LOF[] = FB_AD[31..16];
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; LOF[15..8].ENA = LOF_CS & !nFB_WR & FB_B2;
--VDL_LWD LOF[7..0].ENA = LOF_CS & !nFB_WR & FB_B3;
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK; -- LWD
VDL_LWD[] = FB_AD[31..16]; LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; LWD[].CLK = MAIN_CLK;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; LWD[] = FB_AD[31..16];
LWD[15..8].ENA = LWD_CS & !nFB_WR & FB_B0;
LWD[7..0].ENA = LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL -- HORIZONTAL
-- VDL_HHT -- HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK; HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16]; HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; HHT[11..8].ENA = HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; HHT[7..0].ENA = HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 -- HBE
VDL_HBE[].CLK = MAIN_CLK; HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[] = FB_AD[27..16]; HBE[].CLK = MAIN_CLK;
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; HBE[] = FB_AD[27..16];
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; HBE[11..8].ENA = HBE_CS & !nFB_WR & FB_B2;
-- VDL_HDB HBE[7..0].ENA = HBE_CS & !nFB_WR & FB_B3;
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK; -- HDB
VDL_HDB[] = FB_AD[27..16]; HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; HDB[].CLK = MAIN_CLK;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; HDB[] = FB_AD[27..16];
-- VDL_HDE HDB[11..8].ENA = HDB_CS & !nFB_WR & FB_B0;
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 HDB[7..0].ENA = HDB_CS & !nFB_WR & FB_B1;
VDL_HDE[].CLK = MAIN_CLK; -- HDE
VDL_HDE[] = FB_AD[27..16]; HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; HDE[].CLK = MAIN_CLK;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; HDE[] = FB_AD[27..16];
-- VDL_HBB HDE[11..8].ENA = HDE_CS & !nFB_WR & FB_B2;
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 HDE[7..0].ENA = HDE_CS & !nFB_WR & FB_B3;
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16]; -- HBB
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; HBB[].CLK = MAIN_CLK;
-- VDL_HSS HBB[] = FB_AD[27..16];
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 HBB[11..8].ENA = HBB_CS & !nFB_WR & FB_B0;
VDL_HSS[].CLK = MAIN_CLK; HBB[7..0].ENA = HBB_CS & !nFB_WR & FB_B1;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; -- HSS
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; HSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C146"; -- Videl HSYNC start register $828C / 2
HSS[].CLK = MAIN_CLK;
HSS[] = FB_AD[27..16];
HSS[11..8].ENA = HSS_CS & !nFB_WR & FB_B0;
HSS[7..0].ENA = HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL -- VERTIKAL
-- VDL_VBE -- VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VBE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK; VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16]; VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VBE[10..8].ENA = VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; VBE[7..0].ENA = VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 -- VDB
VDL_VDB[].CLK = MAIN_CLK; VDB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C154"; -- $82A8/2
VDL_VDB[] = FB_AD[26..16]; VDB[].CLK = MAIN_CLK;
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDB[] = FB_AD[26..16];
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; VDB[10..8].ENA = VDB_CS & !nFB_WR & FB_B0;
-- VDL_VDE VDB[7..0].ENA = VDB_CS & !nFB_WR & FB_B1;
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK; -- VDE
VDL_VDE[] = FB_AD[26..16]; VDE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C155"; -- $82AA/2
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDE[].CLK = MAIN_CLK;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; VDE[] = FB_AD[26..16];
-- VDL_VBB VDE[10..8].ENA = VDE_CS & !nFB_WR & FB_B2;
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDE[7..0].ENA = VDE_CS & !nFB_WR & FB_B3;
VDL_VBB[].CLK = MAIN_CLK; -- VBB
VDL_VBB[] = FB_AD[26..16]; VBB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C152"; -- $82A4/2
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VBB[].CLK = MAIN_CLK;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; VBB[] = FB_AD[26..16];
-- VDL_VSS VBB[10..8].ENA = VBB_CS & !nFB_WR & FB_B0;
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VBB[7..0].ENA = VBB_CS & !nFB_WR & FB_B1;
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16]; -- VSS
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C156"; -- $82AC/2
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; VSS[].CLK = MAIN_CLK;
-- VDL_VFT VSS[] = FB_AD[26..16];
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VSS[10..8].ENA = VSS_CS & !nFB_WR & FB_B0;
VDL_VFT[].CLK = MAIN_CLK; VSS[7..0].ENA = VSS_CS & !nFB_WR & FB_B1;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; -- VFT
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; VFT_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C151"; -- $82A2/2
-- VDL_VCT VFT[].CLK = MAIN_CLK;
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VFT[] = FB_AD[26..16];
VDL_VCT[].CLK = MAIN_CLK; VFT[10..8].ENA = VFT_CS & !nFB_WR & FB_B2;
VDL_VCT[] = FB_AD[24..16]; VFT[7..0].ENA = VFT_CS & !nFB_WR & FB_B3;
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; -- VCO
-- VDL_VMD VCO_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C160"; -- $82C0 / 2 Falcon clock control register VCO
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VCO[].CLK = MAIN_CLK;
VDL_VMD[].CLK = MAIN_CLK; VCO[] = FB_AD[24..16];
VDL_VMD[] = FB_AD[19..16]; VCO[8].ENA = VCO_CS & !nFB_WR & FB_B0;
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; VCO[7..0].ENA = VCO_CS & !nFB_WR & FB_B1;
-- VCNTRL
VCNTRL_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C161"; -- $82C2 / 2 Falcon resolution control register VCNTRL
VCNTRL[].CLK = MAIN_CLK;
VCNTRL[] = FB_AD[19..16];
VCNTRL[3..0].ENA = VCNTRL_CS & !nFB_WR & FB_B3;
--- REGISTER OUT --- REGISTER OUT
-- low word register access
FB_AD[31..16] = lpm_bustri_WORD( FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") ST_SHIFT_MODE_CS & (0, ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) # FALCON_SHIFT_MODE_CS & (0, FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) # SYS_CTR_CS & (B"100000000", SYS_CTR[6..4], !BLITTER_RUN, SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[] # LOF_CS & LOF[]
# VDL_LWD_CS & VDL_LWD[] # LWD_CS & LWD[]
# VDL_HBE_CS & (0,VDL_HBE[]) # HBE_CS & (0, HBE[])
# VDL_HDB_CS & (0,VDL_HDB[]) # HDB_CS & (0, HDB[])
# VDL_HDE_CS & (0,VDL_HDE[]) # HDE_CS & (0, HDE[])
# VDL_HBB_CS & (0,VDL_HBB[]) # HBB_CS & (0, HBB[])
# VDL_HSS_CS & (0,VDL_HSS[]) # HSS_CS & (0, HSS[])
# VDL_HHT_CS & (0,VDL_HHT[]) # HHT_CS & (0, HHT[])
# VDL_VBE_CS & (0,VDL_VBE[]) # VBE_CS & (0, VBE[])
# VDL_VDB_CS & (0,VDL_VDB[]) # VDB_CS & (0, VDB[])
# VDL_VDE_CS & (0,VDL_VDE[]) # VDE_CS & (0, VDE[])
# VDL_VBB_CS & (0,VDL_VBB[]) # VBB_CS & (0, VBB[])
# VDL_VSS_CS & (0,VDL_VSS[]) # VSS_CS & (0, VSS[])
# VDL_VFT_CS & (0,VDL_VFT[]) # VFT_CS & (0, VFT[])
# VDL_VCT_CS & (0,VDL_VCT[]) # VCO_CS & (0, VCO[])
# VDL_VMD_CS & (0,VDL_VMD[]) # VCNTRL_CS & (0, VCNTRL[])
# ACP_VCTR_CS & ACP_VCTR[31..16] # ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16] # ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16] # ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16] # ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16] # ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16]) # CCR_CS & (0, CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") # VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE);
-- high word register access
FB_AD[15..0] = lpm_bustri_WORD( FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0] ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0] # ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0] # ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0] # ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0] # ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0] # CCR_CS & CCR[15..0],
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); (ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS;
-- VIDEO AUSGABE SETZEN -- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M; CLK17M.CLK = CLK33M;
CLK17M = !CLK17M; CLK17M = !CLK17M;
CLK13M.CLK = CLK25M; CLK13M.CLK = CLK25M;
CLK13M = !CLK13M; CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz,
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz,
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, VGA monitor
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA monitor
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
-------------------------------------------------------------- --------------------------------------------------------------
-- HORIZONTALE SYNC L<EFBFBD>NGE in PIXEL_CLK -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
---------------------------------------------------------------- ----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK; -- HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 640 pixels
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 320 pixels
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
# 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR MULF[] = 2 & !ST_VIDEO & VCNTRL2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2 # 4 & !ST_VIDEO & !VCNTRL2
# 16 & ST_VIDEO & VDL_VMD2 # 16 & ST_VIDEO & VCNTRL2
# 32 & ST_VIDEO & !VDL_VMD2; # 32 & ST_VIDEO & !VCNTRL2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2; # 640 & !VCNTRL2;
-- DOPPELZEILENMODUS -- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS
INTER_ZEI.CLK = PIXEL_CLK; INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0 == VDIS_START0 & VVCNT[] != 0 & VHCNT[] > (HDIS_END[] - 2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK; DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<EFBFBD>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON HDIS_START[] = HDB[] & ACP_VIDEO_ON
# RAND_LINKS[] + 1 & !ACP_VIDEO_ON; --
HDIS_END[] = HDE[] & ACP_VIDEO_ON
# RAND_LINKS[] + HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON
# HDIS_END[] + 1 & !ACP_VIDEO_ON; --
HS_START[] = HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC # 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; # (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
VDIS_START[] = VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC # 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; # (0, VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
VDIS_END[] = VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; # (0, VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC RAND_UNTEN[] = VBB[] & ACP_VIDEO_ON
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; # VDIS_END[] + 1 & !ACP_VIDEO_ON & ATARI_SYNC
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON # (0, VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 VS_START[] = VSS[] & ACP_VIDEO_ON
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # (0, VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; V_TOTAL[] = VFT[] & ACP_VIDEO_ON
-- Z<>HLER # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# (0, VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- ZÄHLER
LAST.CLK = PIXEL_CLK; LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2); LAST = VHCNT[] == (H_TOTAL[] - 2);
VHCNT[].CLK = PIXEL_CLK; VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST; VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK; VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST; VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1);
-- DISPLAY ON OFF -- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK; DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <EFBFBD>BERNEHMEN DPO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
DPO_ON.CLK = PIXEL_CLK; DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING DPO_ON = VHCNT[] == RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK; DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1); DPO_OFF = VHCNT[] == (RAND_RECHTS[] - 1);
DISP_ON.CLK = PIXEL_CLK; DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL; # DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF -- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK; VCO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING VCO_ON = VHCNT[] == (HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[]; VCO_OFF.CLK = PIXEL_CLK;
VDO_ZL.CLK = PIXEL_CLK; VCO_OFF = VHCNT[] == HDIS_END[];
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF VCO_ZL.CLK = PIXEL_CLK;
VCO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
VCO_ZL = (VVCNT[] >= (VDIS_START[] - 1)) & (VVCNT[] < VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK; VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF VDTRON = VDTRON & !VCO_OFF
# VDO_ON & VDO_ZL; # VCO_ON & VCO_ZL;
-- VERZ<52>GERUNG UND SYNC
-- VERZÖGERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK; HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3; HSYNC_START = VHCNT[] == HS_START[] - 3;
HSYNC_I[].CLK = PIXEL_CLK; HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0; # (HSYNC_I[] - 1) & !HSYNC_START & HSYNC_I[] != 0;
VSYNC_START.CLK = PIXEL_CLK; VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST; VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync VSYNC_START = VVCNT[] == (VS_START[] - 3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK; VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<EFBFBD>hlen bis 0 # (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[] != 0; -- runterzählen bis 0
VERZ[][].CLK = PIXEL_CLK; VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0]; VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1]; VERZ[][2] = VERZ[][1];
@@ -620,18 +711,23 @@ BEGIN
VERZ[][8] = VERZ[][7]; VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8]; VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON; VERZ[0][0] = DISP_ON;
-- VERZ[1][0] = HSYNC_I[]!=0; -- VERZ[1][0] = HSYNC_I[] != 0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0 VERZ[1][0] = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<EFBFBD>GLICH WENN BEIDE # ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0 VERZ[2][0] = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<EFBFBD>GLICH WENN BEIDE # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK; nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8]; nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK; HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9]; HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK; VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9]; VSYNC = VERZ[2][9];
nSYNC = GND; nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------ -- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK; RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25; RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
@@ -643,31 +739,37 @@ BEGIN
RAND[6] = RAND[5]; RAND[6] = RAND[5];
RAND_ON = RAND[6]; RAND_ON = RAND[6];
---------------------------------------------------------- ----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK; CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST; CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<EFBFBD>SCHEN CLR_FIFO = VVCNT[] == V_TOTAL[] - 2; -- IN LETZTER ZEILE LÖSCHEN
START_ZEILE.CLK = PIXEL_CLK; START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST; START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1 START_ZEILE = VVCNT[] == 0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK; SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN SYNC_PIX = VHCNT[] == 3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK; SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN SYNC_PIX1 = VHCNT[] == 5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK; SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<EFBFBD>HLER SYNCHRONISIEREN SYNC_PIX2 = VHCNT[] == 7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK; SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX; SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
FIFO_RDE.CLK = PIXEL_CLK; FIFO_RDE.CLK = PIXEL_CLK;
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1 FIFO_RDE = (SUB_PIXEL_CNT[6..0] == 1 & COLOR1
# SUB_PIXEL_CNT[5..0]==1 & COLOR2 # SUB_PIXEL_CNT[5..0] == 1 & COLOR2
# SUB_PIXEL_CNT[4..0]==1 & COLOR4 # SUB_PIXEL_CNT[4..0] == 1 & COLOR4
# SUB_PIXEL_CNT[3..0]==1 & COLOR8 # SUB_PIXEL_CNT[3..0] == 1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16 # SUB_PIXEL_CNT[2..0] == 1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON # SUB_PIXEL_CNT[1..0] == 1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<EFBFBD>TZLICH F<EFBFBD>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK; CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK; CLUT_MUX_AV[][].CLK = PIXEL_CLK;
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0]; CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][]; CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];

490
FPGA_Quartus_13.1/Video/Video.bdf
View File

@@ -6701,7 +6701,7 @@ applicable agreement for further details.
) )
) )
(symbol (symbol
(rect 2072 1176 2232 1320) (rect 2080 1176 2240 1320)
(text "lpm_fifoDZ" (rect 41 2 118 18)(font "Arial" (font_size 10))) (text "lpm_fifoDZ" (rect 41 2 118 18)(font "Arial" (font_size 10)))
(text "inst63" (rect 8 125 38 136)(font "Arial" )) (text "inst63" (rect 8 125 38 136)(font "Arial" ))
(port (port
@@ -9886,36 +9886,6 @@ applicable agreement for further details.
(pt 2248 1344) (pt 2248 1344)
(bus) (bus)
) )
(connector
(pt 1968 1424)
(pt 1968 1208)
(bus)
)
(connector
(pt 2248 1208)
(pt 2232 1208)
(bus)
)
(connector
(pt 2248 1344)
(pt 2248 1208)
(bus)
)
(connector
(pt 1872 1424)
(pt 1968 1424)
(bus)
)
(connector
(pt 1968 1424)
(pt 2000 1424)
(bus)
)
(connector
(pt 1968 1208)
(pt 2072 1208)
(bus)
)
(connector (connector
(pt 2512 1248) (pt 2512 1248)
(pt 2512 1408) (pt 2512 1408)
@@ -9944,16 +9914,6 @@ applicable agreement for further details.
(pt 1160 1136) (pt 1160 1136)
(bus) (bus)
) )
(connector
(text "DOP_FIFO_CLR" (rect 1978 1280 2062 1291)(font "Arial" ))
(pt 2072 1296)
(pt 1992 1296)
)
(connector
(text "PIXEL_CLK" (rect 2002 1256 2063 1267)(font "Arial" ))
(pt 2072 1272)
(pt 1992 1272)
)
(connector (connector
(text "VDVZ[127..96]" (rect 1450 936 1523 947)(font "Arial" )) (text "VDVZ[127..96]" (rect 1450 936 1523 947)(font "Arial" ))
(pt 1440 952) (pt 1440 952)
@@ -10161,6 +10121,205 @@ applicable agreement for further details.
(pt 1640 1384) (pt 1640 1384)
(pt 1712 1384) (pt 1712 1384)
) )
(connector
(pt 1888 1120)
(pt 1888 1160)
(bus)
)
(connector
(text "VDM_SEL[3..0]" (rect 1810 1144 1886 1155)(font "Arial" ))
(pt 1888 1160)
(pt 1800 1160)
(bus)
)
(connector
(pt 1944 1296)
(pt 1920 1296)
)
(connector
(text "FIFO_RDE" (rect 1770 1272 1826 1283)(font "Arial" ))
(pt 1760 1288)
(pt 1856 1288)
)
(connector
(text "INTER_ZEI" (rect 1762 1288 1818 1299)(font "Arial" ))
(pt 1752 1304)
(pt 1856 1304)
)
(connector
(text "VIDEO_MOD_TA" (rect 258 1816 347 1827)(font "Arial" ))
(pt 264 1832)
(pt 360 1832)
)
(connector
(text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" ))
(pt 296 2232)
(pt 192 2232)
)
(connector
(text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" ))
(pt 1712 1472)
(pt 1632 1472)
)
(connector
(text "SR_BLITTER_DACK" (rect 778 2560 884 2571)(font "Arial" ))
(pt 904 2576)
(pt 768 2576)
)
(connector
(text "DDRCLK0" (rect 794 2544 847 2555)(font "Arial" ))
(pt 904 2560)
(pt 784 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1165 2571)(font "Arial" ))
(pt 1176 2576)
(pt 1048 2576)
(bus)
)
(connector
(text "BLITTER_DACK[0]" (rect 778 2952 872 2963)(font "Arial" ))
(pt 776 2968)
(pt 888 2968)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 1042 2944 1149 2955)(font "Arial" ))
(pt 1160 2960)
(pt 1032 2960)
(bus)
)
(connector
(text "BLITTER_SIG" (rect 578 2808 649 2819)(font "Arial" ))
(pt 568 2824)
(pt 680 2824)
)
(connector
(text "BLITTER_WR" (rect 578 2832 649 2843)(font "Arial" ))
(pt 568 2848)
(pt 680 2848)
)
(connector
(text "nFB_CS1" (rect 202 2696 250 2707)(font "Arial" ))
(pt 192 2712)
(pt 296 2712)
)
(connector
(text "nFB_CS2" (rect 202 2720 251 2731)(font "Arial" ))
(pt 192 2736)
(pt 296 2736)
)
(connector
(text "nFB_CS3" (rect 202 2744 251 2755)(font "Arial" ))
(pt 192 2760)
(pt 296 2760)
)
(connector
(text "nFB_WR" (rect 202 2768 248 2779)(font "Arial" ))
(pt 192 2784)
(pt 296 2784)
)
(connector
(text "FB_SIZE0" (rect 202 2792 253 2803)(font "Arial" ))
(pt 192 2808)
(pt 296 2808)
)
(connector
(text "FB_SIZE1" (rect 202 2816 252 2827)(font "Arial" ))
(pt 192 2832)
(pt 296 2832)
)
(connector
(text "nFB_OE" (rect 202 2840 245 2851)(font "Arial" ))
(pt 192 2856)
(pt 296 2856)
)
(connector
(text "MAIN_CLK" (rect 202 2624 259 2635)(font "Arial" ))
(pt 296 2640)
(pt 192 2640)
)
(connector
(text "FB_ALE" (rect 202 2672 244 2683)(font "Arial" ))
(pt 296 2688)
(pt 192 2688)
)
(connector
(text "FB_ADR[31..0]" (rect 202 2648 276 2659)(font "Arial" ))
(pt 192 2664)
(pt 296 2664)
(bus)
)
(connector
(text "nRSTO" (rect 202 2576 240 2587)(font "Arial" ))
(pt 192 2592)
(pt 296 2592)
)
(connector
(text "FB_AD[31..0]" (rect 578 2616 644 2627)(font "Arial" ))
(pt 688 2632)
(pt 568 2632)
(bus)
)
(connector
(text "DDRCLK0" (rect 194 2600 247 2611)(font "Arial" ))
(pt 296 2616)
(pt 184 2616)
)
(connector
(text "BLITTER_TA" (rect 578 2968 646 2979)(font "Arial" ))
(pt 568 2984)
(pt 672 2984)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 178 2872 285 2883)(font "Arial" ))
(pt 296 2888)
(pt 184 2888)
(bus)
)
(connector
(text "VIDEO_RAM_CTR[15..0]" (rect 154 2904 279 2915)(font "Arial" ))
(pt 296 2920)
(pt 144 2920)
(bus)
)
(connector
(text "BLITTER_ON" (rect 202 2928 270 2939)(font "Arial" ))
(pt 296 2944)
(pt 192 2944)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 162 2952 269 2963)(font "Arial" ))
(pt 296 2968)
(pt 152 2968)
(bus)
)
(connector
(text "BLITTER_DOUT[127..0]" (rect 578 2752 697 2763)(font "Arial" ))
(pt 712 2768)
(pt 568 2768)
(bus)
)
(connector
(text "BLITTER_ADR[31..0]" (rect 578 2784 684 2795)(font "Arial" ))
(pt 704 2800)
(pt 568 2800)
(bus)
)
(connector
(text "BLITTER_RUN" (rect 578 2720 653 2731)(font "Arial" ))
(pt 672 2736)
(pt 568 2736)
)
(connector
(text "SR_BLITTER_DACK" (rect 170 2984 276 2995)(font "Arial" ))
(pt 296 3000)
(pt 160 3000)
)
(connector
(text "DOP_FIFO_CLR" (rect 1978 1296 2062 1307)(font "Arial" ))
(pt 2064 1312)
(pt 1992 1312)
)
(connector (connector
(text "nFB_BURST" (rect 1570 1896 1634 1907)(font "Arial" )) (text "nFB_BURST" (rect 1570 1896 1634 1907)(font "Arial" ))
(pt 1560 1912) (pt 1560 1912)
@@ -10347,53 +10506,9 @@ applicable agreement for further details.
(pt 1536 2544) (pt 1536 2544)
) )
(connector (connector
(pt 1888 1120) (text "CLK_VIDEO" (rect 1570 2144 1633 2155)(font "Arial" ))
(pt 1888 1160) (pt 1512 2160)
(bus) (pt 1664 2160)
)
(connector
(text "VDM_SEL[3..0]" (rect 1810 1144 1886 1155)(font "Arial" ))
(pt 1888 1160)
(pt 1800 1160)
(bus)
)
(connector
(pt 1608 1432)
(pt 1608 1232)
)
(connector
(pt 1600 1432)
(pt 1608 1432)
)
(connector
(pt 1608 1432)
(pt 1712 1432)
)
(connector
(pt 1608 1232)
(pt 2072 1232)
)
(connector
(pt 2072 1248)
(pt 1944 1248)
)
(connector
(pt 1944 1248)
(pt 1944 1296)
)
(connector
(pt 1944 1296)
(pt 1920 1296)
)
(connector
(text "FIFO_RDE" (rect 1770 1272 1826 1283)(font "Arial" ))
(pt 1760 1288)
(pt 1856 1288)
)
(connector
(text "INTER_ZEI" (rect 1762 1288 1818 1299)(font "Arial" ))
(pt 1752 1304)
(pt 1856 1304)
) )
(connector (connector
(text "CLK33M" (rect 1586 2168 1630 2179)(font "Arial" )) (text "CLK33M" (rect 1586 2168 1630 2179)(font "Arial" ))
@@ -10405,16 +10520,6 @@ applicable agreement for further details.
(pt 1512 2208) (pt 1512 2208)
(pt 1664 2208) (pt 1664 2208)
) )
(connector
(text "CLK_VIDEO" (rect 1570 2144 1633 2155)(font "Arial" ))
(pt 1512 2160)
(pt 1664 2160)
)
(connector
(text "VIDEO_MOD_TA" (rect 258 1816 347 1827)(font "Arial" ))
(pt 264 1832)
(pt 360 1832)
)
(connector (connector
(text "COLOR8" (rect 2026 1912 2073 1923)(font "Arial" )) (text "COLOR8" (rect 2026 1912 2073 1923)(font "Arial" ))
(pt 2016 1928) (pt 2016 1928)
@@ -10447,13 +10552,18 @@ applicable agreement for further details.
) )
(connector (connector
(text "VR_WR" (rect 2026 1784 2067 1795)(font "Arial" )) (text "VR_WR" (rect 2026 1784 2067 1795)(font "Arial" ))
(pt 2016 1800)
(pt 2112 1800) (pt 2112 1800)
(pt 2016 1800)
) )
(connector (connector
(text "VR_RD" (rect 2026 1800 2064 1811)(font "Arial" )) (text "VR_RD" (rect 2026 1800 2064 1811)(font "Arial" ))
(pt 2016 1816)
(pt 2112 1816) (pt 2112 1816)
(pt 2016 1816)
)
(connector
(text "VR_BUSY" (rect 1578 2104 1632 2115)(font "Arial" ))
(pt 1512 2120)
(pt 1664 2120)
) )
(connector (connector
(text "VR_D[8..0]" (rect 1570 2120 1624 2131)(font "Arial" )) (text "VR_D[8..0]" (rect 1570 2120 1624 2131)(font "Arial" ))
@@ -10461,179 +10571,77 @@ applicable agreement for further details.
(pt 1664 2136) (pt 1664 2136)
(bus) (bus)
) )
(connector
(text "VR_BUSY" (rect 1578 2104 1632 2115)(font "Arial" ))
(pt 1512 2120)
(pt 1664 2120)
)
(connector
(text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" ))
(pt 296 2232)
(pt 192 2232)
)
(connector (connector
(text "CLR_FIFO" (rect 2026 1752 2081 1763)(font "Arial" )) (text "CLR_FIFO" (rect 2026 1752 2081 1763)(font "Arial" ))
(pt 2016 1768) (pt 2016 1768)
(pt 2112 1768) (pt 2112 1768)
) )
(connector (connector
(text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" )) (pt 1968 1424)
(pt 1712 1472) (pt 1968 1208)
(pt 1632 1472)
)
(connector
(text "SR_BLITTER_DACK" (rect 778 2560 884 2571)(font "Arial" ))
(pt 904 2576)
(pt 768 2576)
)
(connector
(text "DDRCLK0" (rect 794 2544 847 2555)(font "Arial" ))
(pt 904 2560)
(pt 784 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1165 2571)(font "Arial" ))
(pt 1176 2576)
(pt 1048 2576)
(bus) (bus)
) )
(connector (connector
(text "BLITTER_DACK[0]" (rect 778 2952 872 2963)(font "Arial" )) (pt 2248 1208)
(pt 776 2968) (pt 2240 1208)
(pt 888 2968)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 1042 2944 1149 2955)(font "Arial" ))
(pt 1160 2960)
(pt 1032 2960)
(bus) (bus)
) )
(connector (connector
(text "BLITTER_SIG" (rect 578 2808 649 2819)(font "Arial" )) (pt 2248 1344)
(pt 568 2824) (pt 2248 1208)
(pt 680 2824)
)
(connector
(text "BLITTER_WR" (rect 578 2832 649 2843)(font "Arial" ))
(pt 568 2848)
(pt 680 2848)
)
(connector
(text "nFB_CS1" (rect 202 2696 250 2707)(font "Arial" ))
(pt 192 2712)
(pt 296 2712)
)
(connector
(text "nFB_CS2" (rect 202 2720 251 2731)(font "Arial" ))
(pt 192 2736)
(pt 296 2736)
)
(connector
(text "nFB_CS3" (rect 202 2744 251 2755)(font "Arial" ))
(pt 192 2760)
(pt 296 2760)
)
(connector
(text "nFB_WR" (rect 202 2768 248 2779)(font "Arial" ))
(pt 192 2784)
(pt 296 2784)
)
(connector
(text "FB_SIZE0" (rect 202 2792 253 2803)(font "Arial" ))
(pt 192 2808)
(pt 296 2808)
)
(connector
(text "FB_SIZE1" (rect 202 2816 252 2827)(font "Arial" ))
(pt 192 2832)
(pt 296 2832)
)
(connector
(text "nFB_OE" (rect 202 2840 245 2851)(font "Arial" ))
(pt 192 2856)
(pt 296 2856)
)
(connector
(text "MAIN_CLK" (rect 202 2624 259 2635)(font "Arial" ))
(pt 296 2640)
(pt 192 2640)
)
(connector
(text "FB_ALE" (rect 202 2672 244 2683)(font "Arial" ))
(pt 296 2688)
(pt 192 2688)
)
(connector
(text "FB_ADR[31..0]" (rect 202 2648 276 2659)(font "Arial" ))
(pt 192 2664)
(pt 296 2664)
(bus) (bus)
) )
(connector (connector
(text "nRSTO" (rect 202 2576 240 2587)(font "Arial" )) (pt 1608 1432)
(pt 192 2592) (pt 1608 1232)
(pt 296 2592)
) )
(connector (connector
(text "FB_AD[31..0]" (rect 578 2616 644 2627)(font "Arial" )) (pt 1944 1296)
(pt 688 2632) (pt 1944 1248)
(pt 568 2632) )
(connector
(pt 2064 1312)
(pt 2064 1296)
)
(connector
(pt 1872 1424)
(pt 1968 1424)
(bus) (bus)
) )
(connector (connector
(text "DDRCLK0" (rect 194 2600 247 2611)(font "Arial" )) (pt 1968 1424)
(pt 296 2616) (pt 2000 1424)
(pt 184 2616)
)
(connector
(text "BLITTER_TA" (rect 578 2968 646 2979)(font "Arial" ))
(pt 568 2984)
(pt 672 2984)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 178 2872 285 2883)(font "Arial" ))
(pt 296 2888)
(pt 184 2888)
(bus) (bus)
) )
(connector (connector
(text "VIDEO_RAM_CTR[15..0]" (rect 154 2904 279 2915)(font "Arial" )) (pt 1600 1432)
(pt 296 2920) (pt 1608 1432)
(pt 144 2920) )
(connector
(pt 1608 1432)
(pt 1712 1432)
)
(connector
(pt 1968 1208)
(pt 2080 1208)
(bus) (bus)
) )
(connector (connector
(text "BLITTER_ON" (rect 202 2928 270 2939)(font "Arial" )) (pt 1608 1232)
(pt 296 2944) (pt 2080 1232)
(pt 192 2944)
) )
(connector (connector
(text "BLITTER_DIN[127..0]" (rect 162 2952 269 2963)(font "Arial" )) (pt 1944 1248)
(pt 296 2968) (pt 2080 1248)
(pt 152 2968)
(bus)
) )
(connector (connector
(text "BLITTER_DOUT[127..0]" (rect 578 2752 697 2763)(font "Arial" )) (text "PIXEL_CLK" (rect 2010 1256 2071 1267)(font "Arial" ))
(pt 712 2768) (pt 2000 1272)
(pt 568 2768) (pt 2080 1272)
(bus)
) )
(connector (connector
(text "BLITTER_ADR[31..0]" (rect 578 2784 684 2795)(font "Arial" )) (pt 2064 1296)
(pt 704 2800) (pt 2080 1296)
(pt 568 2800)
(bus)
)
(connector
(text "BLITTER_RUN" (rect 578 2720 653 2731)(font "Arial" ))
(pt 672 2736)
(pt 568 2736)
)
(connector
(text "SR_BLITTER_DACK" (rect 170 2984 276 2995)(font "Arial" ))
(pt 296 3000)
(pt 160 3000)
) )
(junction (pt 2984 1688)) (junction (pt 2984 1688))
(junction (pt 792 1192)) (junction (pt 792 1192))

1
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -827,4 +827,5 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

179
FPGA_Quartus_13.1/firebee1.sdc.groups Normal file
View File

@@ -0,0 +1,179 @@
#--------------------------------------------------------------#
# #
# Synopsis design constraints for the Firebee project #
# #
# This file is part of the Firebee ACP project. #
# http://www.experiment-s.de #
# #
# Description: #
# timing constraints for the Firebee VHDL config #
# #
# #
# #
# To Do: #
# - #
# #
# Author(s): #
# Markus Fröschle, mfro@mubf.de #
# #
#--------------------------------------------------------------#
# #
# Copyright (C) 2015 Markus Fröschle & the ACP project #
# #
# This source file may be used and distributed without #
# restriction provided that this copyright statement is not #
# removed from the file and that any derivative work contains #
# the original copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it #
# and/or modify it under the terms of the GNU Lesser General #
# Public License as published by the Free Software Foundation; #
# either version 2.1 of the License, or (at your option) any #
# later version. #
# #
# This source is distributed in the hope that it will be #
# useful, but WITHOUT ANY WARRANTY; without even the implied #
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
# PURPOSE. See the GNU Lesser General Public License for more #
# details. #
# #
# You should have received a copy of the GNU Lesser General #
# Public License along with this source; if not, download it #
# from http://www.gnu.org/licenses/lgpl.html #
# #
################################################################
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
# Clocks used:
# MAIN_CLK 33MHz
#
# PLL1: i_mfp_acia_clk_pll
# input: MAIN_CLK
# c0: 500 kHz
# c1: 2.4576 MHz
# c2: 24.576 MHz
#
# PLL2: i_ddr_clock_pll
# input: MAIN_CLK
# c0: 132 MHz 240°
# c1: 132 MHz 0°
# c2: 132 MHz 180°
# c3: 132 MHz 105°
# c4: 66 MHz 270°
#
# PLL3: i_atari_clk_pll
# input: MAIN_CLK
# c0: 2 MHz
# c1: 16 MHz
# c2: 25 MHz
# c3: 48 MHz
#
# PLL4_ i_video_clk_pll
# input: USB_CLK (48 MHz, PLL3 c3)
# c0: 96 MHz, programmable in 1MHz steps
#
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
# PIXEL_CLK is either
# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
# where CLK13M is half of CLK25M,
# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
# clock of i_video_clk_pll
#
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.0
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.0
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \
[get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] \
-group [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \
[get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \
[get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \
[get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \
-group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \
-group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \
-group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \
-group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \
-group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************