From 6a0eebf0684f2775fd7d380a22e896c6c4e5b853 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 25 Apr 2016 19:09:52 +0000 Subject: [PATCH] change formatting --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 1312 ++++++++--------- .../Video/video_mod_mux_clutctr.vhd | 940 ++++++------ 2 files changed, 1122 insertions(+), 1130 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index d5e2740..cb29254 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -16,56 +16,56 @@ -- FIFO WATER MARK -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -LIBRARY ieee; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_arith.all; -ENTITY ddr_ctr IS - PORT +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; +entity ddr_ctr is + port ( - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - CLR_FIFO : IN std_logic; - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VA : BUFFER std_logic_vector(12 DOWNTO 0); - nVWE : BUFFER std_logic; - nVRAS : BUFFER std_logic; - nVCS : BUFFER std_logic; - VCKE : BUFFER std_logic; - nVCAS : BUFFER std_logic; - FB_LE : BUFFER std_logic_vector(3 DOWNTO 0); - FB_VDOE : BUFFER std_logic_vector(3 DOWNTO 0); - SR_FIFO_WRE : BUFFER std_logic; - SR_DDR_FB : BUFFER std_logic; - SR_DDR_WR : BUFFER std_logic; - SR_DDRWR_D_SEL : BUFFER std_logic; - SR_VDMP : BUFFER std_logic_vector(7 DOWNTO 0); - VIDEO_DDR_TA : BUFFER std_logic; - SR_BLITTER_DACK : BUFFER std_logic; - BA : BUFFER std_logic_vector(1 DOWNTO 0); - DDRWR_D_SEL1 : BUFFER std_logic; - VDM_SEL : BUFFER std_logic_vector(3 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + FB_ADR : in std_logic_vector(31 downto 0); + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + FB_ALE : in std_logic; + nFB_WR : in std_logic; + DDR_SYNC_66M : in std_logic; + CLR_FIFO : in std_logic; + VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); + BLITTER_ADR : in std_logic_vector(31 downto 0); + BLITTER_SIG : in std_logic; + BLITTER_WR : in std_logic; + DDRCLK0 : in std_logic; + CLK33M : in std_logic; + FIFO_MW : in std_logic_vector(8 downto 0); + VA : buffer std_logic_vector(12 downto 0); + nVWE : buffer std_logic; + nVRAS : buffer std_logic; + nVCS : buffer std_logic; + VCKE : buffer std_logic; + nVCAS : buffer std_logic; + FB_LE : buffer std_logic_vector(3 downto 0); + FB_VDOE : buffer std_logic_vector(3 downto 0); + SR_FIFO_WRE : buffer std_logic; + SR_DDR_FB : buffer std_logic; + SR_DDR_WR : buffer std_logic; + SR_DDRWR_D_SEL : buffer std_logic; + SR_VDMP : buffer std_logic_vector(7 downto 0); + VIDEO_DDR_TA : buffer std_logic; + SR_BLITTER_DACK : buffer std_logic; + BA : buffer std_logic_vector(1 downto 0); + DDRWR_D_SEL1 : buffer std_logic; + VDM_SEL : buffer std_logic_vector(3 downto 0); + FB_AD : inout std_logic_vector(31 downto 0) ); -END ddr_ctr; +end ddr_ctr; -ARCHITECTURE rtl OF ddr_ctr IS +architecture rtl of ddr_ctr is -- START (NORMAL 8 CYCLES TOTAL = 60ns) -- CONFIG -- READ CPU UND BLITTER, @@ -73,522 +73,522 @@ ARCHITECTURE rtl OF ddr_ctr IS -- READ FIFO -- CLOSE FIFO BANK -- REFRESH 10X7.5NfS=75NS - SIGNAL FB_REGDDR_3 : std_logic_vector(2 DOWNTO 0); - SIGNAL FB_REGDDR_d : std_logic_vector(2 DOWNTO 0); - SIGNAL FB_REGDDR_q : std_logic_vector(2 DOWNTO 0); - SIGNAL DDR_SM_6 : std_logic_vector(5 DOWNTO 0); - SIGNAL DDR_SM_d : std_logic_vector(5 DOWNTO 0); - SIGNAL DDR_SM_q : std_logic_vector(5 DOWNTO 0); - SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); - SIGNAL VA_P : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_P_d : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_P_q : std_logic_vector(12 DOWNTO 0); - SIGNAL BA_P : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_P_d : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_P_q : std_logic_vector(1 DOWNTO 0); - SIGNAL VA_S : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_S_d : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_S_q : std_logic_vector(12 DOWNTO 0); - SIGNAL BA_S : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_S_d : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_S_q : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS_d : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS_q : std_logic_vector(1 DOWNTO 0); - SIGNAL SR_VDMP_d : std_logic_vector(7 DOWNTO 0); - SIGNAL SR_VDMP_q : std_logic_vector(7 DOWNTO 0); - SIGNAL CPU_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL CPU_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL CPU_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL BLITTER_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL BLITTER_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL BLITTER_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL FIFO_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL FIFO_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL FIFO_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT_d : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT_q : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG : std_logic_vector(3 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG_d : std_logic_vector(3 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG_q : std_logic_vector(3 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D_d : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D_q : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT_d : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT_q : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_BASE_ADR : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ACT_ADR : std_logic_vector(26 DOWNTO 0); - SIGNAL u0_data : std_logic_vector(7 DOWNTO 0); - SIGNAL u0_tridata : std_logic_vector(7 DOWNTO 0); - SIGNAL FB_REGDDR_0_clk_ctrl : std_logic; - SIGNAL SR_VDMP0_clk_ctrl : std_logic; - SIGNAL MCS0_clk_ctrl : std_logic; - SIGNAL VA_S0_clk_ctrl : std_logic; - SIGNAL BA_S0_clk_ctrl : std_logic; - SIGNAL VA_P0_clk_ctrl : std_logic; - SIGNAL BA_P0_clk_ctrl : std_logic; - SIGNAL DDR_SM_0_clk_ctrl : std_logic; - SIGNAL VIDEO_ADR_CNT0_clk_ctrl : std_logic; - SIGNAL VIDEO_ADR_CNT0_ena_ctrl : std_logic; - SIGNAL DDR_REFRESH_CNT0_clk_ctrl : std_logic; - SIGNAL DDR_REFRESH_SIG0_clk_ctrl : std_logic; - SIGNAL DDR_REFRESH_SIG0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_L_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_L_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_M_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_M_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_H_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_H_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_X_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_X_D0_ena_ctrl : std_logic; - SIGNAL VA12_2 : std_logic; - SIGNAL VA12_1 : std_logic; - SIGNAL VA11_2 : std_logic; - SIGNAL VA11_1 : std_logic; - SIGNAL VA10_2 : std_logic; - SIGNAL VA10_1 : std_logic; - SIGNAL VA9_2 : std_logic; - SIGNAL VA9_1 : std_logic; - SIGNAL VA8_2 : std_logic; - SIGNAL VA8_1 : std_logic; - SIGNAL VA7_2 : std_logic; - SIGNAL VA7_1 : std_logic; - SIGNAL VA6_2 : std_logic; - SIGNAL VA6_1 : std_logic; - SIGNAL VA5_2 : std_logic; - SIGNAL VA5_1 : std_logic; - SIGNAL VA4_2 : std_logic; - SIGNAL VA4_1 : std_logic; - SIGNAL VA3_2 : std_logic; - SIGNAL VA3_1 : std_logic; - SIGNAL VA2_2 : std_logic; - SIGNAL VA2_1 : std_logic; - SIGNAL VA1_2 : std_logic; - SIGNAL VA1_1 : std_logic; - SIGNAL VA0_2 : std_logic; - SIGNAL VA0_1 : std_logic; - SIGNAL BA1_2 : std_logic; - SIGNAL BA1_1 : std_logic; - SIGNAL BA0_2 : std_logic; - SIGNAL BA0_1 : std_logic; - SIGNAL BUS_CYC_d_2 : std_logic; - SIGNAL BUS_CYC_d_1 : std_logic; - SIGNAL FIFO_BANK_OK_d_2 : std_logic; - SIGNAL FIFO_BANK_OK_d_1 : std_logic; - SIGNAL u0_enabledt : std_logic; + signal FB_REGDDR_3 : std_logic_vector(2 downto 0); + signal FB_REGDDR_d : std_logic_vector(2 downto 0); + signal FB_REGDDR_q : std_logic_vector(2 downto 0); + signal DDR_SM_6 : std_logic_vector(5 downto 0); + signal DDR_SM_d : std_logic_vector(5 downto 0); + signal DDR_SM_q : std_logic_vector(5 downto 0); + signal FB_B : std_logic_vector(3 downto 0); + signal VA_P : std_logic_vector(12 downto 0); + signal VA_P_d : std_logic_vector(12 downto 0); + signal VA_P_q : std_logic_vector(12 downto 0); + signal BA_P : std_logic_vector(1 downto 0); + signal BA_P_d : std_logic_vector(1 downto 0); + signal BA_P_q : std_logic_vector(1 downto 0); + signal VA_S : std_logic_vector(12 downto 0); + signal VA_S_d : std_logic_vector(12 downto 0); + signal VA_S_q : std_logic_vector(12 downto 0); + signal BA_S : std_logic_vector(1 downto 0); + signal BA_S_d : std_logic_vector(1 downto 0); + signal BA_S_q : std_logic_vector(1 downto 0); + signal MCS : std_logic_vector(1 downto 0); + signal MCS_d : std_logic_vector(1 downto 0); + signal MCS_q : std_logic_vector(1 downto 0); + signal SR_VDMP_d : std_logic_vector(7 downto 0); + signal SR_VDMP_q : std_logic_vector(7 downto 0); + signal CPU_ROW_ADR : std_logic_vector(12 downto 0); + signal CPU_BA : std_logic_vector(1 downto 0); + signal CPU_COL_ADR : std_logic_vector(9 downto 0); + signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); + signal BLITTER_BA : std_logic_vector(1 downto 0); + signal BLITTER_COL_ADR : std_logic_vector(9 downto 0); + signal FIFO_ROW_ADR : std_logic_vector(12 downto 0); + signal FIFO_BA : std_logic_vector(1 downto 0); + signal FIFO_COL_ADR : std_logic_vector(9 downto 0); + signal DDR_REFRESH_CNT : std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_d : std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_q : std_logic_vector(10 downto 0); + signal DDR_REFRESH_SIG : std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_d : std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_q : std_logic_vector(3 downto 0); + signal VIDEO_BASE_L_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_X_D : std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_d : std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_q : std_logic_vector(2 downto 0); + signal VIDEO_ADR_CNT : std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_d : std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_q : std_logic_vector(22 downto 0); + signal VIDEO_BASE_ADR : std_logic_vector(22 downto 0); + signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); + signal u0_data : std_logic_vector(7 downto 0); + signal u0_tridata : std_logic_vector(7 downto 0); + signal FB_REGDDR_0_clk_ctrl : std_logic; + signal SR_VDMP0_clk_ctrl : std_logic; + signal MCS0_clk_ctrl : std_logic; + signal VA_S0_clk_ctrl : std_logic; + signal BA_S0_clk_ctrl : std_logic; + signal VA_P0_clk_ctrl : std_logic; + signal BA_P0_clk_ctrl : std_logic; + signal DDR_SM_0_clk_ctrl : std_logic; + signal VIDEO_ADR_CNT0_clk_ctrl : std_logic; + signal VIDEO_ADR_CNT0_ena_ctrl : std_logic; + signal DDR_REFRESH_CNT0_clk_ctrl : std_logic; + signal DDR_REFRESH_SIG0_clk_ctrl : std_logic; + signal DDR_REFRESH_SIG0_ena_ctrl : std_logic; + signal VIDEO_BASE_L_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_L_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_M_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_M_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_H_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_H_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_X_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_X_D0_ena_ctrl : std_logic; + signal VA12_2 : std_logic; + signal VA12_1 : std_logic; + signal VA11_2 : std_logic; + signal VA11_1 : std_logic; + signal VA10_2 : std_logic; + signal VA10_1 : std_logic; + signal VA9_2 : std_logic; + signal VA9_1 : std_logic; + signal VA8_2 : std_logic; + signal VA8_1 : std_logic; + signal VA7_2 : std_logic; + signal VA7_1 : std_logic; + signal VA6_2 : std_logic; + signal VA6_1 : std_logic; + signal VA5_2 : std_logic; + signal VA5_1 : std_logic; + signal VA4_2 : std_logic; + signal VA4_1 : std_logic; + signal VA3_2 : std_logic; + signal VA3_1 : std_logic; + signal VA2_2 : std_logic; + signal VA2_1 : std_logic; + signal VA1_2 : std_logic; + signal VA1_1 : std_logic; + signal VA0_2 : std_logic; + signal VA0_1 : std_logic; + signal BA1_2 : std_logic; + signal BA1_1 : std_logic; + signal BA0_2 : std_logic; + signal BA0_1 : std_logic; + signal BUS_CYC_d_2 : std_logic; + signal BUS_CYC_d_1 : std_logic; + signal FIFO_BANK_OK_d_2 : std_logic; + signal FIFO_BANK_OK_d_1 : std_logic; + signal u0_enabledt : std_logic; SiGNAL gnd : std_logic; - SIGNAL vcc : std_logic; - SIGNAL VIDEO_CNT_H : std_logic; - SIGNAL VIDEO_CNT_M : std_logic; - SIGNAL VIDEO_CNT_L : std_logic; - SIGNAL VIDEO_BASE_H : std_logic; - SIGNAL VIDEO_BASE_M : std_logic; - SIGNAL VIDEO_BASE_L : std_logic; - SIGNAL REFRESH_TIME_q : std_logic; - SIGNAL REFRESH_TIME_clk : std_logic; - SIGNAL REFRESH_TIME_d : std_logic; - SIGNAL REFRESH_TIME : std_logic; - SIGNAL DDR_REFRESH_REQ_q : std_logic; - SIGNAL DDR_REFRESH_REQ_clk : std_logic; - SIGNAL DDR_REFRESH_REQ_d : std_logic; - SIGNAL DDR_REFRESH_REQ : std_logic; - SIGNAL DDR_REFRESH_ON : std_logic; - SIGNAL FIFO_BANK_NOT_OK : std_logic; - SIGNAL FIFO_BANK_OK_q : std_logic; - SIGNAL FIFO_BANK_OK_clk : std_logic; - SIGNAL FIFO_BANK_OK_d : std_logic; - SIGNAL FIFO_BANK_OK : std_logic; + signal vcc : std_logic; + signal VIDEO_CNT_H : std_logic; + signal VIDEO_CNT_M : std_logic; + signal VIDEO_CNT_L : std_logic; + signal VIDEO_BASE_H : std_logic; + signal VIDEO_BASE_M : std_logic; + signal VIDEO_BASE_L : std_logic; + signal REFRESH_TIME_q : std_logic; + signal REFRESH_TIME_clk : std_logic; + signal REFRESH_TIME_d : std_logic; + signal REFRESH_TIME : std_logic; + signal DDR_REFRESH_REQ_q : std_logic; + signal DDR_REFRESH_REQ_clk : std_logic; + signal DDR_REFRESH_REQ_d : std_logic; + signal DDR_REFRESH_REQ : std_logic; + signal DDR_REFRESH_ON : std_logic; + signal FIFO_BANK_NOT_OK : std_logic; + signal FIFO_BANK_OK_q : std_logic; + signal FIFO_BANK_OK_clk : std_logic; + signal FIFO_BANK_OK_d : std_logic; + signal FIFO_BANK_OK : std_logic; SiGNAL SR_FIFO_WRE_q : std_logic; - SIGNAL SR_FIFO_WRE_clk : std_logic; - SIGNAL SR_FIFO_WRE_d : std_logic; - SIGNAL STOP_q : std_logic; - SIGNAL STOP_clk : std_logic; - SIGNAL STOP_d : std_logic; - SIGNAL STOP : std_logic; - SIGNAL CLEAR_FIFO_CNT_q : std_logic; - SIGNAL CLEAR_FIFO_CNT_clk : std_logic; - SIGNAL CLEAR_FIFO_CNT_d : std_logic; - SIGNAL CLEAR_FIFO_CNT : std_logic; - SIGNAL CLR_FIFO_SYNC_q : std_logic; - SIGNAL CLR_FIFO_SYNC_clk : std_logic; - SIGNAL CLR_FIFO_SYNC_d : std_logic; - SIGNAL CLR_FIFO_SYNC : std_logic; - SIGNAL FIFO_ACTIVE : std_logic; - SIGNAL FIFO_AC_q : std_logic; - SIGNAL FIFO_AC_clk : std_logic; - SIGNAL FIFO_AC_d : std_logic; - SIGNAL FIFO_AC : std_logic; - SIGNAL FIFO_REQ_q : std_logic; - SIGNAL FIFO_REQ_clk : std_logic; - SIGNAL FIFO_REQ_d : std_logic; - SIGNAL FIFO_REQ : std_logic; - SIGNAL BLITTER_AC_q : std_logic; - SIGNAL BLITTER_AC_clk : std_logic; - SIGNAL BLITTER_AC_d : std_logic; - SIGNAL BLITTER_AC : std_logic; - SIGNAL BLITTER_REQ_q : std_logic; - SIGNAL BLITTER_REQ_clk : std_logic; - SIGNAL BLITTER_REQ_d : std_logic; - SIGNAL BLITTER_REQ : std_logic; - SIGNAL BUS_CYC_END : std_logic; - SIGNAL BUS_CYC_q : std_logic; - SIGNAL BUS_CYC_clk : std_logic; - SIGNAL BUS_CYC_d : std_logic; - SIGNAL BUS_CYC : std_logic; - SIGNAL CPU_AC_q : std_logic; - SIGNAL CPU_AC_clk : std_logic; - SIGNAL CPU_AC_d : std_logic; - SIGNAL CPU_AC : std_logic; - SIGNAL CPU_REQ_q : std_logic; - SIGNAL CPU_REQ_clk : std_logic; - SIGNAL CPU_REQ_d : std_logic; - SIGNAL CPU_REQ : std_logic; - SIGNAL CPU_SIG : std_logic; - SIGNAL SR_DDRWR_D_SEL_q : std_logic; - SIGNAL SR_DDRWR_D_SEL_clk : std_logic; - SIGNAL SR_DDRWR_D_SEL_d : std_logic; - SIGNAL SR_DDR_WR_q : std_logic; - SIGNAL SR_DDR_WR_clk : std_logic; - SIGNAL SR_DDR_WR_d : std_logic; - SIGNAL DDR_CONFIG : std_logic; - SIGNAL DDR_CS_q : std_logic; - SIGNAL DDR_CS_ena : std_logic; - SIGNAL DDR_CS_clk : std_logic; - SIGNAL DDR_CS_d : std_logic; - SIGNAL DDR_CS : std_logic; - SIGNAL DDR_SEL : std_logic; - SIGNAL CPU_DDR_SYNC_q : std_logic; - SIGNAL CPU_DDR_SYNC_clk : std_logic; - SIGNAL CPU_DDR_SYNC_d : std_logic; - SIGNAL CPU_DDR_SYNC : std_logic; - SIGNAL VWE : std_logic; - SIGNAL VRAS : std_logic; - SIGNAL VCAS : std_logic; - SIGNAL LINE : std_logic; + signal SR_FIFO_WRE_clk : std_logic; + signal SR_FIFO_WRE_d : std_logic; + signal STOP_q : std_logic; + signal STOP_clk : std_logic; + signal STOP_d : std_logic; + signal STOP : std_logic; + signal CLEAR_FIFO_CNT_q : std_logic; + signal CLEAR_FIFO_CNT_clk : std_logic; + signal CLEAR_FIFO_CNT_d : std_logic; + signal CLEAR_FIFO_CNT : std_logic; + signal CLR_FIFO_SYNC_q : std_logic; + signal CLR_FIFO_SYNC_clk : std_logic; + signal CLR_FIFO_SYNC_d : std_logic; + signal CLR_FIFO_SYNC : std_logic; + signal FIFO_ACTIVE : std_logic; + signal FIFO_AC_q : std_logic; + signal FIFO_AC_clk : std_logic; + signal FIFO_AC_d : std_logic; + signal FIFO_AC : std_logic; + signal FIFO_REQ_q : std_logic; + signal FIFO_REQ_clk : std_logic; + signal FIFO_REQ_d : std_logic; + signal FIFO_REQ : std_logic; + signal BLITTER_AC_q : std_logic; + signal BLITTER_AC_clk : std_logic; + signal BLITTER_AC_d : std_logic; + signal BLITTER_AC : std_logic; + signal BLITTER_REQ_q : std_logic; + signal BLITTER_REQ_clk : std_logic; + signal BLITTER_REQ_d : std_logic; + signal BLITTER_REQ : std_logic; + signal BUS_CYC_END : std_logic; + signal BUS_CYC_q : std_logic; + signal BUS_CYC_clk : std_logic; + signal BUS_CYC_d : std_logic; + signal BUS_CYC : std_logic; + signal CPU_AC_q : std_logic; + signal CPU_AC_clk : std_logic; + signal CPU_AC_d : std_logic; + signal CPU_AC : std_logic; + signal CPU_REQ_q : std_logic; + signal CPU_REQ_clk : std_logic; + signal CPU_REQ_d : std_logic; + signal CPU_REQ : std_logic; + signal CPU_SIG : std_logic; + signal SR_DDRWR_D_SEL_q : std_logic; + signal SR_DDRWR_D_SEL_clk : std_logic; + signal SR_DDRWR_D_SEL_d : std_logic; + signal SR_DDR_WR_q : std_logic; + signal SR_DDR_WR_clk : std_logic; + signal SR_DDR_WR_d : std_logic; + signal DDR_CONFIG : std_logic; + signal DDR_CS_q : std_logic; + signal DDR_CS_ena : std_logic; + signal DDR_CS_clk : std_logic; + signal DDR_CS_d : std_logic; + signal DDR_CS : std_logic; + signal DDR_SEL : std_logic; + signal CPU_DDR_SYNC_q : std_logic; + signal CPU_DDR_SYNC_clk : std_logic; + signal CPU_DDR_SYNC_d : std_logic; + signal CPU_DDR_SYNC : std_logic; + signal VWE : std_logic; + signal VRAS : std_logic; + signal VCAS : std_logic; + signal LINE : std_logic; - SIGNAL v_basx : std_logic_vector(1 DOWNTO 0); - SIGNAL v_basx_cs : std_logic; + signal v_basx : std_logic_vector(1 downto 0); + signal v_basx_cs : std_logic; - SIGNAL v_bash : std_logic_vector(7 DOWNTO 0); - SIGNAL v_bash_cs : std_logic; + signal v_bash : std_logic_vector(7 downto 0); + signal v_bash_cs : std_logic; - SIGNAL reg_ta : std_logic; + signal reg_ta : std_logic; -- Sub Module Interface Section - COMPONENT lpm_bustri_BYT - PORT + component lpm_bustri_BYT + port ( - data : IN std_logic_vector(7 DOWNTO 0); - enabledt : IN std_logic; - tridata : BUFFER std_logic_vector(7 DOWNTO 0) + data : in std_logic_vector(7 downto 0); + enabledt : in std_logic; + tridata : buffer std_logic_vector(7 downto 0) ); - END COMPONENT lpm_bustri_BYT; + end component lpm_bustri_BYT; - FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS - VARIABLE ret : std_logic; - BEGIN - IF x THEN + function to_std_logic(X : in boolean) return std_logic is + variable ret : std_logic; + begin + if x then ret := '1'; - ELSE + else ret := '0'; - END IF; - RETURN ret; - END to_std_logic; + end if; + return ret; + end to_std_logic; -- sizeIt replicates a value to an array of specific length. - FUNCTION sizeit(a: std_logic; len: integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0); - BEGIN - FOR i IN rep'RANGE LOOP + function sizeit(a: std_logic; len: integer) return std_logic_vector is + variable rep: std_logic_vector(len - 1 downto 0); + begin + FOR i in rep'RANGE LOOP rep(i) := a; - END LOOP; - RETURN rep; - END sizeIt; + end LOOP; + return rep; + end sizeIt; -BEGIN +begin -- Sub Module Section - u0: lpm_bustri_BYT + u0 : lpm_bustri_BYT port map ( - data=>u0_data, - enabledt=>u0_enabledt, - tridata=>u0_tridata + data => u0_data, + enabledt => u0_enabledt, + tridata => u0_tridata ); -- Register Section SR_FIFO_WRE <= SR_FIFO_WRE_q; - PROCESS (SR_FIFO_WRE_clk) - BEGIN - IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN + process (SR_FIFO_WRE_clk) + begin + if rising_edge(sr_fifo_wre_clk) then SR_FIFO_WRE_q <= SR_FIFO_WRE_d; - END IF; - END PROCESS; + end if; + end process; SR_DDR_WR <= SR_DDR_WR_q; - PROCESS (SR_DDR_WR_clk) - BEGIN - IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN + process (SR_DDR_WR_clk) + begin + if rising_edge(sr_ddr_wr_clk) then SR_DDR_WR_q <= SR_DDR_WR_d; - END IF; - END PROCESS; + end if; + end process; SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; - PROCESS (SR_DDRWR_D_SEL_clk) - BEGIN - IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN + process (SR_DDRWR_D_SEL_clk) + begin + if rising_edge(sr_ddrwr_d_sel_clk) then SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; - END IF; - END PROCESS; + end if; + end process; SR_VDMP <= SR_VDMP_q; - PROCESS (SR_VDMP0_clk_ctrl) - BEGIN - IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN + process (SR_VDMP0_clk_ctrl) + begin + if rising_edge(sr_vdmp0_clk_ctrl) then SR_VDMP_q <= SR_VDMP_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FB_REGDDR_0_clk_ctrl) - BEGIN - IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN + process (FB_REGDDR_0_clk_ctrl) + begin + if rising_edge(fb_regddr_0_clk_ctrl) then FB_REGDDR_q <= FB_REGDDR_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_SM_0_clk_ctrl) - BEGIN - IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN + process (DDR_SM_0_clk_ctrl) + begin + if rising_edge(ddr_sm_0_clk_ctrl) then DDR_SM_q <= DDR_SM_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VA_P0_clk_ctrl) - BEGIN - IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN + process (VA_P0_clk_ctrl) + begin + if rising_edge(va_p0_clk_ctrl) then VA_P_q <= VA_P_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BA_P0_clk_ctrl) - BEGIN - IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN + process (BA_P0_clk_ctrl) + begin + if rising_edge(ba_p0_clk_ctrl) then BA_P_q <= BA_P_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VA_S0_clk_ctrl) - BEGIN - IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN + process (VA_S0_clk_ctrl) + begin + if rising_edge(va_s0_clk_ctrl) then VA_S_q <= VA_S_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BA_S0_clk_ctrl) - BEGIN - IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN + process (BA_S0_clk_ctrl) + begin + if BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' then BA_S_q <= BA_S_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (MCS0_clk_ctrl) - BEGIN - IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN + process (MCS0_clk_ctrl) + begin + if MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' then MCS_q <= MCS_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CPU_DDR_SYNC_clk) - BEGIN - IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN + process (CPU_DDR_SYNC_clk) + begin + if CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' then CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_CS_clk) - BEGIN - IF DDR_CS_clk'event and DDR_CS_clk='1' THEN - IF DDR_CS_ena='1' THEN + process (DDR_CS_clk) + begin + if DDR_CS_clk'event and DDR_CS_clk='1' then + if DDR_CS_ena='1' then DDR_CS_q <= DDR_CS_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (CPU_REQ_clk) - BEGIN - IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN + process (CPU_REQ_clk) + begin + if CPU_REQ_clk'event and CPU_REQ_clk='1' then CPU_REQ_q <= CPU_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CPU_AC_clk) - BEGIN - IF CPU_AC_clk'event and CPU_AC_clk='1' THEN + process (CPU_AC_clk) + begin + if CPU_AC_clk'event and CPU_AC_clk='1' then CPU_AC_q <= CPU_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BUS_CYC_clk) - BEGIN - IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN + process (BUS_CYC_clk) + begin + if BUS_CYC_clk'event and BUS_CYC_clk='1' then BUS_CYC_q <= BUS_CYC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BLITTER_REQ_clk) - BEGIN - IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN + process (BLITTER_REQ_clk) + begin + if BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' then BLITTER_REQ_q <= BLITTER_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BLITTER_AC_clk) - BEGIN - IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN + process (BLITTER_AC_clk) + begin + if BLITTER_AC_clk'event and BLITTER_AC_clk='1' then BLITTER_AC_q <= BLITTER_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_REQ_clk) - BEGIN - IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN + process (FIFO_REQ_clk) + begin + if FIFO_REQ_clk'event and FIFO_REQ_clk='1' then FIFO_REQ_q <= FIFO_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_AC_clk) - BEGIN - IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN + process (FIFO_AC_clk) + begin + if FIFO_AC_clk'event and FIFO_AC_clk='1' then FIFO_AC_q <= FIFO_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CLR_FIFO_SYNC_clk) - BEGIN - IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN + process (CLR_FIFO_SYNC_clk) + begin + if CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' then CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CLEAR_FIFO_CNT_clk) - BEGIN - IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN + process (CLEAR_FIFO_CNT_clk) + begin + if CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' then CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (STOP_clk) - BEGIN - IF STOP_clk'event and STOP_clk='1' THEN + process (STOP_clk) + begin + if STOP_clk'event and STOP_clk='1' then STOP_q <= STOP_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_BANK_OK_clk) - BEGIN - IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN + process (FIFO_BANK_OK_clk) + begin + if FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' then FIFO_BANK_OK_q <= FIFO_BANK_OK_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_CNT0_clk_ctrl) - BEGIN - IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN + process (DDR_REFRESH_CNT0_clk_ctrl) + begin + if DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' then DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_REQ_clk) - BEGIN - IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN + process (DDR_REFRESH_REQ_clk) + begin + if DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' then DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_SIG0_clk_ctrl) - BEGIN - IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN - IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN + process (DDR_REFRESH_SIG0_clk_ctrl) + begin + if DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' then + if DDR_REFRESH_SIG0_ena_ctrl='1' then DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (REFRESH_TIME_clk) - BEGIN - IF REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' THEN + process (REFRESH_TIME_clk) + begin + if REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' then REFRESH_TIME_q <= REFRESH_TIME_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VIDEO_BASE_L_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_L_D0_clk_ctrl) + begin + if VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' then + if VIDEO_BASE_L_D0_ena_ctrl='1' then VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_M_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_M_D0_clk_ctrl) + begin + if VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' then + if VIDEO_BASE_M_D0_ena_ctrl='1' then VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_H_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_H_D0_clk_ctrl) + begin + if VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' then + if VIDEO_BASE_H_D0_ena_ctrl='1' then VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_X_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_X_D0_clk_ctrl) + begin + if VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' then + if VIDEO_BASE_X_D0_ena_ctrl='1' then VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_ADR_CNT0_clk_ctrl) - BEGIN - IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN - IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN + process (VIDEO_ADR_CNT0_clk_ctrl) + begin + if VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' then + if VIDEO_ADR_CNT0_ena_ctrl='1' then VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; i_vbasx : work.flexbus_register - GENERIC MAP + generic map ( reg_width => 2, match_address => x"ffff8603", match_mask => x"0000ffff", -- byte register match_fbcs => 1 ) - PORT MAP + port map ( clk => clk33m, fb_addr => fb_adr, @@ -601,14 +601,14 @@ BEGIN ); i_vbash : work.flexbus_register - GENERIC MAP + generic map ( reg_width => 8, match_address => x"ffff8604", match_mask => x"0000fffe", -- byte register match_fbcs => 1 ) - PORT MAP + port map ( clk => clk33m, fb_addr => fb_adr, @@ -626,106 +626,106 @@ BEGIN -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- FB_REGDDR_0_clk_ctrl <= MAIN_CLK; - PROCESS (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) - VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); - BEGIN + process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) + variable stdVec3: std_logic_vector(2 downto 0); + begin FB_REGDDR_d <= FB_REGDDR_q; - fb_vdoe <= (OTHERS => '0'); - fb_le <= (OTHERS => '0'); + fb_vdoe <= (others => '0'); + fb_le <= (others => '0'); video_ddr_ta <= '0'; bus_cyc_end <= '0'; stdVec3 := FB_REGDDR_q; - CASE stdVec3 IS - WHEN "000" => + case stdVec3 is + when "000" => FB_LE(0) <= not nFB_WR; -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' THEN + if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' then FB_REGDDR_d <= "001"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "001" => - IF DDR_CS_q = '1' THEN + when "001" => + if DDR_CS_q = '1' then FB_LE(0) <= not nFB_WR; VIDEO_DDR_TA <= vcc; - IF LINE ='1' THEN + if LINE ='1' then FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); FB_REGDDR_d <= "010"; - ELSE + else BUS_CYC_END <= vcc; FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_REGDDR_d <= "000"; - END IF; - ELSE + end if; + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "010" => - IF DDR_CS_q = '1' THEN + when "010" => + if DDR_CS_q = '1' then FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(1) <= not nFB_WR; VIDEO_DDR_TA <= vcc; FB_REGDDR_d <= "011"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "011" => - IF DDR_CS_q ='1' THEN + when "011" => + if DDR_CS_q ='1' then FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(2) <= not nFB_WR; -- BEI LINE WRITE EVT. WARTEN - IF ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' THEN + if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then FB_REGDDR_d <= "011"; - ELSE + else VIDEO_DDR_TA <= vcc; FB_REGDDR_d <= "100"; - END IF; - ELSE + end if; + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "100" => - IF DDR_CS_q = '1' THEN + when "100" => + if DDR_CS_q = '1' then FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_LE(3) <= not nFB_WR; VIDEO_DDR_TA <= vcc; BUS_CYC_END <= vcc; FB_REGDDR_d <= "000"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN others => - END CASE; - stdVec3 := (OTHERS => '0'); -- no storage needed - END PROCESS; + when others => + end case; + stdVec3 := (others => '0'); -- no storage needed + end process; -- DDR STEUERUNG ----------------------------------------------------- - -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; VCKE <= VIDEO_RAM_CTR(0); nVCS <= not VIDEO_RAM_CTR(1); DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); @@ -733,9 +733,9 @@ BEGIN FIFO_ACTIVE <= VIDEO_RAM_CTR(8); -- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 DOWNTO 14); - CPU_BA <= FB_ADR(13 DOWNTO 12); - CPU_COL_ADR <= FB_ADR(11 DOWNTO 2); + CPU_ROW_ADR <= FB_ADR(26 downto 14); + CPU_BA <= FB_ADR(13 downto 12); + CPU_COL_ADR <= FB_ADR(11 downto 2); nVRAS <= not VRAS; nVCAS <= not VCAS; nVWE <= not VWE; @@ -751,7 +751,7 @@ BEGIN DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 DOWNTO 30) = "01"); + DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); DDR_CS_clk <= MAIN_CLK; DDR_CS_ena <= FB_ALE; DDR_CS_d <= DDR_SEL; @@ -792,15 +792,15 @@ BEGIN DDR_SM_0_clk_ctrl <= DDRCLK0; - PROCESS (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, + process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, DDR_REFRESH_SIG_q, vcc) - VARIABLE stdVec6: std_logic_vector(5 DOWNTO 0); - BEGIN + variable stdVec6: std_logic_vector(5 downto 0); + begin DDR_SM_d <= DDR_SM_q; BA_S_d <= "00"; VA_S_d <= "0000000000000"; @@ -809,7 +809,7 @@ BEGIN VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= std_logic_vector'("00000000000"); SR_VDMP_d <= "00000000"; - VA_P_d(12 DOWNTO 11) <= "00"; + VA_P_d(12 downto 11) <= "00"; (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, @@ -818,54 +818,54 @@ BEGIN std_logic_vector'("00000000000000000000000000000"); stdVec6 := DDR_SM_q; - CASE stdVec6 IS - WHEN "000000" => - IF (DDR_REFRESH_REQ_q)='1' THEN + case stdVec6 is + when "000000" => + if (DDR_REFRESH_REQ_q)='1' then DDR_SM_d <= "011111"; -- SYNCHRON UND EIN? - ELSIF (CPU_DDR_SYNC_q)='1' THEN + elsif (CPU_DDR_SYNC_q)='1' then -- JA - IF (DDR_CONFIG)='1' THEN + if (DDR_CONFIG)='1' then DDR_SM_d <= "001000"; -- BEI WAIT UND LINE WRITE - ELSIF (CPU_REQ_q)='1' THEN + elsif (CPU_REQ_q)='1' then VA_S_d <= CPU_ROW_ADR; BA_S_d <= CPU_BA; CPU_AC_d <= vcc; BUS_CYC_d_2 <= vcc; DDR_SM_d <= "000010"; - ELSE + else -- FIFO IST DEFAULT - IF (FIFO_REQ_q or (not BLITTER_REQ_q))='1' THEN + if (FIFO_REQ_q or (not BLITTER_REQ_q))='1' then VA_P_d <= FIFO_ROW_ADR; BA_P_d <= FIFO_BA; -- VORBESETZEN FIFO_AC_d <= vcc; - ELSE + else VA_P_d <= BLITTER_ROW_ADR; BA_P_d <= BLITTER_BA; -- VORBESETZEN BLITTER_AC_d <= vcc; - END IF; + end if; DDR_SM_d <= "000001"; - END IF; - ELSE + end if; + else -- NEIN ->SYNCHRONISIEREN DDR_SM_d <= "000000"; - END IF; + end if; - WHEN "000001" => + when "000001" => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - IF (DDR_SEL and (nFB_WR or (not LINE)))='1' THEN + if (DDR_SEL and (nFB_WR or (not LINE)))='1' then VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); - (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); -- AUTO PRECHARGE DA NICHT FIFO PAGE VA_S_d(10) <= vcc; CPU_AC_d <= vcc; -- BUS CYCLUS LOSTRETEN BUS_CYC_d_2 <= vcc; - ELSE + else VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (BA1_2, BA0_2) <= BA_P_q; @@ -873,10 +873,10 @@ BEGIN FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; - END IF; + end if; DDR_SM_d <= "000011"; - WHEN "000010" => + when "000010" => VRAS <= vcc; FIFO_BANK_NOT_OK <= vcc; CPU_AC_d <= vcc; @@ -885,36 +885,36 @@ BEGIN BUS_CYC_d_2 <= vcc; DDR_SM_d <= "000011"; - WHEN "000011" => + when "000011" => CPU_AC_d <= CPU_AC_q; FIFO_AC_d <= FIFO_AC_q; BLITTER_AC_d <= BLITTER_AC_q; -- AUTO PRECHARGE WENN NICHT FIFO PAGE VA_S_d(10) <= VA_S_q(10); - IF (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' THEN + if (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' then DDR_SM_d <= "010000"; -- CPU? - ELSIF (CPU_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= CPU_COL_ADR; + elsif (CPU_AC_q)='1' then + VA_S_d(9 downto 0) <= CPU_COL_ADR; BA_S_d <= CPU_BA; DDR_SM_d <= "001110"; -- FIFO? - ELSIF (FIFO_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + elsif (FIFO_AC_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; BA_S_d <= FIFO_BA; DDR_SM_d <= "010110"; - ELSIF (BLITTER_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= BLITTER_COL_ADR; + elsif (BLITTER_AC_q)='1' then + VA_S_d(9 downto 0) <= BLITTER_COL_ADR; BA_S_d <= BLITTER_BA; DDR_SM_d <= "001110"; - ELSE + else -- READ DDR_SM_d <= "000111"; - END IF; + end if; - WHEN "001110" => + when "001110" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; VCAS <= vcc; @@ -926,26 +926,26 @@ BEGIN SR_BLITTER_DACK <= BLITTER_AC_q; DDR_SM_d <= "001111"; - WHEN "001111" => + when "001111" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; -- FIFO READ EINSCHIEBEN WENN BANK OK - IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- MANUELL PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - ELSE + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- WRITE DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "010000" => + when "010000" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; @@ -956,29 +956,29 @@ BEGIN VA_S_d(10) <= VA_S_q(10); DDR_SM_d <= "010001"; - WHEN "010001" => + when "010001" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q, 10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q, 10) and BLITTER_COL_ADR); + VA_S_d(9 downto 0) <= (sizeIt(CPU_AC_q, 10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q, 10) and BLITTER_COL_ADR); -- AUTO PRECHARGE WENN NICHT FIFO PAGE VA_S_d(10) <= VA_S_q(10); BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); -- BYTE ENABLE WRITE - SR_VDMP_d(7 DOWNTO 4) <= FB_B; + SR_VDMP_d(7 downto 4) <= FB_B; -- LINE ENABLE WRITE - SR_VDMP_d(3 DOWNTO 0) <= sizeIt(LINE,4) and "1111"; + SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; DDR_SM_d <= "010010"; - WHEN "010010" => + when "010010" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; VCAS <= vcc; VWE <= vcc; - -- WRITE COMMAND CPU UND BLITTER IF WRITER + -- WRITE COMMAND CPU UND BLITTER if WRITER SR_DDR_WR_d <= vcc; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN @@ -988,160 +988,160 @@ BEGIN SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; DDR_SM_d <= "010011"; - WHEN "010011" => + when "010011" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - -- WRITE COMMAND CPU UND BLITTER IF WRITE + -- WRITE COMMAND CPU UND BLITTER if WRITE SR_DDR_WR_d <= vcc; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= vcc; DDR_SM_d <= "010100"; - WHEN "010100" => + when "010100" => DDR_SM_d <= "010101"; - WHEN "010101" => - IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + when "010101" => + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - ELSE + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- FIFO READ DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "010110" => + when "010110" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; DDR_SM_d <= "010111"; - WHEN "010111" => - IF (FIFO_REQ_q)='1' THEN + when "010111" => + if (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - ELSE - VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - END IF; - ELSE + end if; + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- NOCH OFFEN LASSEN DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "011000" => + when "011000" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; DDR_SM_d <= "011001"; - WHEN "011001" => - IF CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) THEN + when "011001" => + if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then -- ALLE PAGES SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - ELSIF (FIFO_REQ_q)='1' THEN + elsif (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - ELSE - VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011010"; - END IF; - ELSE + end if; + else -- ALLE PAGES SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - END IF; + end if; - WHEN "011010" => + when "011010" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; -- NOTFALL? - IF (unsigned(FIFO_MW) < unsigned'("000000000")) THEN + if (unsigned(FIFO_MW) < unsigned'("000000000")) then -- JA-> DDR_SM_d <= "010111"; - ELSE + else DDR_SM_d <= "011011"; - END IF; + end if; - WHEN "011011" => - IF (FIFO_REQ_q)='1' THEN + when "011011" => + if (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE BANKS SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - ELSE - VA_P_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_P_d(10) <= gnd; BA_P_d <= FIFO_BA; DDR_SM_d <= "011100"; - END IF; - ELSE + end if; + else -- ALLE BANKS SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "011100" => - IF (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 DOWNTO 12) /= FIFO_BA THEN + when "011100" => + if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); - (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); CPU_AC_d <= vcc; -- BUS CYCLUS LOSTRETEN @@ -1150,7 +1150,7 @@ BEGIN -- AUTO PRECHARGE DA NICHT FIFO BANK VA_S_d(10) <= vcc; DDR_SM_d <= "000011"; - ELSE + else VCAS <= vcc; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (BA1_2, BA0_2) <= BA_P_q; @@ -1160,31 +1160,31 @@ BEGIN -- CONFIG CYCLUS DDR_SM_d <= "011001"; - END IF; + end if; - WHEN "001000" => + when "001000" => DDR_SM_d <= "001001"; - WHEN "001001" => + when "001001" => BUS_CYC_d_2 <= CPU_REQ_q; DDR_SM_d <= "001010"; - WHEN "001010" => - IF (CPU_REQ_q)='1' THEN + when "001010" => + if (CPU_REQ_q)='1' then DDR_SM_d <= "001011"; - ELSE + else DDR_SM_d <= "000000"; - END IF; + end if; - WHEN "001011" => + when "001011" => DDR_SM_d <= "001100"; - WHEN "001100" => - VA_S_d <= FB_AD(12 DOWNTO 0); - BA_S_d <= FB_AD(14 DOWNTO 13); + when "001100" => + VA_S_d <= FB_AD(12 downto 0); + BA_S_d <= FB_AD(14 downto 13); DDR_SM_d <= "001101"; - WHEN "001101" => + when "001101" => -- NUR BEI LONG WRITE VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); @@ -1198,7 +1198,7 @@ BEGIN -- CLOSE FIFO BANK DDR_SM_d <= "000111"; - WHEN "011101" => + when "011101" => -- AUF NOT OK FIFO_BANK_NOT_OK <= vcc; @@ -1208,7 +1208,7 @@ BEGIN VWE <= vcc; DDR_SM_d <= "000110"; - WHEN "011110" => + when "011110" => -- AUF NOT OK FIFO_BANK_NOT_OK <= vcc; @@ -1219,10 +1219,10 @@ BEGIN -- REFRESH 70NS = 10 ZYCLEN DDR_SM_d <= "000000"; - WHEN "011111" => + when "011111" => -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - IF DDR_REFRESH_SIG_q = "1001" THEN + if DDR_REFRESH_SIG_q = "1001" then -- ALLE BANKS SCHLIESSEN VRAS <= vcc; @@ -1230,51 +1230,51 @@ BEGIN VA10_2 <= vcc; FIFO_BANK_NOT_OK <= vcc; DDR_SM_d <= "100001"; - ELSE + else VCAS <= vcc; VRAS <= vcc; DDR_SM_d <= "100000"; - END IF; + end if; - WHEN "100000" => + when "100000" => DDR_SM_d <= "100001"; - WHEN "100001" => + when "100001" => DDR_SM_d <= "100010"; - WHEN "100010" => + when "100010" => DDR_SM_d <= "100011"; - WHEN "100011" => + when "100011" => -- LEERSCHLAUFE DDR_SM_d <= "000100"; - WHEN "000100" => + when "000100" => DDR_SM_d <= "000101"; - WHEN "000101" => + when "000101" => DDR_SM_d <= "000110"; - WHEN "000110" => + when "000110" => DDR_SM_d <= "000111"; - WHEN "000111" => + when "000111" => DDR_SM_d <= "000000"; - WHEN OTHERS => - END CASE; - stdVec6 := (OTHERS => '0'); -- no storage needed - END PROCESS; + when others => + end case; + stdVec6 := (others => '0'); -- no storage needed + end process; -- ------------------------------------------------------------- -- BLITTER ---------------------- -- --------------------------------------- BLITTER_REQ_clk <= DDRCLK0; BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); - BLITTER_ROW_ADR <= BLITTER_ADR(26 DOWNTO 14); + BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); BLITTER_BA(1) <= BLITTER_ADR(13); BLITTER_BA(0) <= BLITTER_ADR(12); - BLITTER_COL_ADR <= BLITTER_ADR(11 DOWNTO 2); + BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); -- ---------------------------------------------------------------------------- -- FIFO --------------------------------- @@ -1284,7 +1284,7 @@ BEGIN (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); - FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 DOWNTO 10); + FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & @@ -1311,16 +1311,16 @@ BEGIN (std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) + unsigned'("00000000000000000000001")))); - VIDEO_BASE_ADR(22 DOWNTO 20) <= VIDEO_BASE_X_D_q; - VIDEO_BASE_ADR(19 DOWNTO 12) <= VIDEO_BASE_H_D_q; - VIDEO_BASE_ADR(11 DOWNTO 4) <= VIDEO_BASE_M_D_q; - VIDEO_BASE_ADR(3 DOWNTO 0) <= VIDEO_BASE_L_D_q(7 DOWNTO 4); - VDM_SEL <= VIDEO_BASE_L_D_q(3 DOWNTO 0); + VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D_q; + VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D_q; + VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D_q; + VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D_q(7 downto 4); + VDM_SEL <= VIDEO_BASE_L_D_q(3 downto 0); -- AKTUELLE VIDEO ADRESSE - VIDEO_ACT_ADR(26 DOWNTO 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - + VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - unsigned(std_logic_vector'("00000000000000" & FIFO_MW))); - VIDEO_ACT_ADR(3 DOWNTO 0) <= VDM_SEL; + VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL; -- --------------------------------------------------------------------------------------- -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS @@ -1352,53 +1352,53 @@ BEGIN VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; -- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000110"); + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000110"); -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; -- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000001"); - VIDEO_BASE_M_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000001"); + VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; -- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000000"); - VIDEO_BASE_H_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000"); + VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; - VIDEO_BASE_X_D_d <= FB_AD(26 DOWNTO 24); + VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); -- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000100"); + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000100"); -- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000011"); + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000011"); -- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000010"); + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) -- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), -- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - fb_ad(31 DOWNTO 24) <= "00000" & video_base_x_d_d WHEN video_base_h and not nfb_oe ELSE - "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h and not nfb_oe ELSE - (OTHERS => 'Z'); + fb_ad(31 downto 24) <= "00000" & video_base_x_d_d when video_base_h and not nfb_oe else + "00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else + (others => 'Z'); u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 DOWNTO 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 DOWNTO 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 DOWNTO 16)); + (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or + (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or + (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - FB_AD(23 DOWNTO 16) <= u0_tridata; + FB_AD(23 downto 16) <= u0_tridata; -- Assignments added to explicitly combine the @@ -1421,7 +1421,7 @@ BEGIN VA(11) <= VA11_1 or VA11_2; VA(12) <= VA12_1 or VA12_2; --- Define power SIGNAL(s) +-- Define power signal(s) vcc <= '1'; gnd <= '0'; -END ARCHITECTURE rtl; +end architecture rtl; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index a7a6b00..a98c78a 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -52,67 +52,68 @@ -- CREATED BY FREDI ASCHWANDEN -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -LIBRARY ieee; - USE ieee.std_logic_1164.all; - USE ieee.numeric_std.all; -ENTITY video_mod_mux_clutctr IS - PORT +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity video_mod_mux_clutctr is + port ( - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 downto 0); - CLK33M : IN std_logic; - CLK25M : IN std_logic; - BLITTER_RUN : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_D : IN std_logic_vector(8 downto 0); - VR_BUSY : IN std_logic; - COLOR8 : OUT std_logic; - ACP_CLUT_RD : OUT std_logic; - COLOR1 : OUT std_logic; - FALCON_CLUT_RDH : OUT std_logic; - FALCON_CLUT_RDL : OUT std_logic; - FALCON_CLUT_WR : OUT std_logic_vector(3 downto 0); - ST_CLUT_RD : OUT std_logic; - ST_CLUT_WR : OUT std_logic_vector(1 downto 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 downto 0); - HSYNC : OUT std_logic; - VSYNC : OUT std_logic; - nBLANK : OUT std_logic; - nSYNC : OUT std_logic; - nPD_VGA : OUT std_logic; - FIFO_RDE : OUT std_logic; - COLOR2 : OUT std_logic; - color4 : OUT std_logic; - PIXEL_CLK : OUT std_logic; - CLUT_OFF : OUT std_logic_vector(3 downto 0); - BLITTER_ON : OUT std_logic; - VIDEO_RAM_CTR : OUT std_logic_vector(15 downto 0); - VIDEO_MOD_TA : OUT std_logic; - BORDER_COLOR : OUT std_logic_vector(23 downto 0); - CCSEL : OUT std_logic_vector(2 downto 0); - ACP_CLUT_WR : OUT std_logic_vector(3 downto 0); - INTER_ZEI : OUT std_logic; - DOP_FIFO_CLR : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - CLR_FIFO : OUT std_logic; - FB_AD : OUT std_logic_vector(31 downto 0) + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_WR : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + CLK33M : in std_logic; + CLK25M : in std_logic; + BLITTER_RUN : in std_logic; + CLK_VIDEO : in std_logic; + VR_D : in std_logic_vector(8 downto 0); + VR_BUSY : in std_logic; + COLOR8 : out std_logic; + ACP_CLUT_RD : out std_logic; + COLOR1 : out std_logic; + FALCON_CLUT_RDH : out std_logic; + FALCON_CLUT_RDL : out std_logic; + FALCON_CLUT_WR : out std_logic_vector(3 downto 0); + ST_CLUT_RD : out std_logic; + ST_CLUT_WR : out std_logic_vector(1 downto 0); + CLUT_MUX_ADR : out std_logic_vector(3 downto 0); + HSYNC : out std_logic; + VSYNC : out std_logic; + nBLANK : out std_logic; + nSYNC : out std_logic; + nPD_VGA : out std_logic; + FIFO_RDE : out std_logic; + COLOR2 : out std_logic; + color4 : out std_logic; + PIXEL_CLK : out std_logic; + CLUT_OFF : out std_logic_vector(3 downto 0); + BLITTER_ON : out std_logic; + VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); + VIDEO_MOD_TA : out std_logic; + BORDER_COLOR : out std_logic_vector(23 downto 0); + CCSEL : out std_logic_vector(2 downto 0); + ACP_CLUT_WR : out std_logic_vector(3 downto 0); + INTER_ZEI : out std_logic; + DOP_FIFO_CLR : out std_logic; + VIDEO_RECONFIG : out std_logic; + VR_WR : out std_logic; + VR_RD : out std_logic; + CLR_FIFO : out std_logic; + FB_AD : out std_logic_vector(31 downto 0) ); -END video_mod_mux_clutctr; +end video_mod_mux_clutctr; -ARCHITECTURE rtl OF video_mod_mux_clutctr IS +architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT -- LÄNGE HSYNC PULS IN PIXEL_CLK @@ -124,398 +125,387 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - SIGNAL VR_DOUT : std_logic_vector(8 downto 0); - SIGNAL VR_DOUT_d : std_logic_vector(8 downto 0); - SIGNAL VR_DOUT_q : std_logic_vector(8 downto 0); - SIGNAL VR_FRQ : unsigned(7 downto 0); - SIGNAL VR_FRQ_d : std_logic_vector(7 downto 0); - SIGNAL VR_FRQ_q : std_logic_vector(7 downto 0); - SIGNAL FB_B : std_logic_vector(3 downto 0); - SIGNAL FB_16B : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); - SIGNAL FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); - SIGNAL FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); - SIGNAL FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); - SIGNAL CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1 : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0 : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); - SIGNAL ACP_VCTR : std_logic_vector(31 downto 0); - SIGNAL ACP_VCTR_d : std_logic_vector(31 downto 0); - SIGNAL ACP_VCTR_q : std_logic_vector(31 downto 0); - SIGNAL BORDER_COLOR_d : std_logic_vector(23 downto 0); - SIGNAL BORDER_COLOR_q : std_logic_vector(23 downto 0); - SIGNAL SYS_CTR : std_logic_vector(6 downto 0); - SIGNAL SYS_CTR_d : std_logic_vector(6 downto 0); - SIGNAL SYS_CTR_q : std_logic_vector(6 downto 0); - SIGNAL LOF : std_logic_vector(15 downto 0); - SIGNAL LOF_d : std_logic_vector(15 downto 0); - SIGNAL LOF_q : std_logic_vector(15 downto 0); - SIGNAL LWD : std_logic_vector(15 downto 0); - SIGNAL LWD_d : std_logic_vector(15 downto 0); - SIGNAL LWD_q : std_logic_vector(15 downto 0); - SIGNAL HSYNC_I : std_logic_vector(7 downto 0); - SIGNAL HSYNC_I_d : std_logic_vector(7 downto 0); - SIGNAL HSYNC_I_q : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN_d : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN_q : std_logic_vector(7 downto 0); - SIGNAL VSYNC_I : std_logic_vector(2 downto 0); - SIGNAL VSYNC_I_d : std_logic_vector(2 downto 0); - SIGNAL VSYNC_I_q : std_logic_vector(2 downto 0); - SIGNAL VHCNT : std_logic_vector(11 downto 0); - SIGNAL VHCNT_d : std_logic_vector(11 downto 0); - SIGNAL VHCNT_q : std_logic_vector(11 downto 0); - SIGNAL SUB_PIXEL_CNT : std_logic_vector(6 downto 0); - SIGNAL SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); - SIGNAL SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); - SIGNAL VVCNT : std_logic_vector(10 downto 0); - SIGNAL VVCNT_d : std_logic_vector(10 downto 0); - SIGNAL VVCNT_q : std_logic_vector(10 downto 0); - SIGNAL VERZ2 : std_logic_vector(9 downto 0); - SIGNAL VERZ2_d : std_logic_vector(9 downto 0); - SIGNAL VERZ2_q : std_logic_vector(9 downto 0); - SIGNAL VERZ1 : std_logic_vector(9 downto 0); - SIGNAL VERZ1_d : std_logic_vector(9 downto 0); - SIGNAL VERZ1_q : std_logic_vector(9 downto 0); - SIGNAL VERZ0 : std_logic_vector(9 downto 0); - SIGNAL VERZ0_d : std_logic_vector(9 downto 0); - SIGNAL VERZ0_q : std_logic_vector(9 downto 0); - SIGNAL RAND : std_logic_vector(6 downto 0) := (OTHERS => '0'); - SIGNAL RAND_d : std_logic_vector(6 downto 0); - SIGNAL RAND_q : std_logic_vector(6 downto 0); - SIGNAL CCSEL_d : std_logic_vector(2 downto 0); - SIGNAL CCSEL_q : std_logic_vector(2 downto 0); - SIGNAL ATARI_HH : std_logic_vector(31 downto 0) := (OTHERS => '0'); - SIGNAL ATARI_HH_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_HH_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_HL : std_logic_vector(31 downto 0) := (OTHERS => '0'); - SIGNAL ATARI_HL_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_HL_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL_q : std_logic_vector(31 downto 0); - SIGNAL RAND_LINKS : std_logic_vector(11 downto 0); - SIGNAL HDIS_START : std_logic_vector(11 downto 0); - SIGNAL HDIS_END : std_logic_vector(11 downto 0); - SIGNAL RAND_RECHTS : std_logic_vector(11 downto 0); - SIGNAL HS_START : std_logic_vector(11 downto 0); - SIGNAL H_TOTAL : std_logic_vector(11 downto 0); - SIGNAL HDIS_LEN : std_logic_vector(11 downto 0); - SIGNAL MULF : std_logic_vector(5 downto 0); - SIGNAL HHT : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HHT_d : std_logic_vector(11 downto 0); - SIGNAL HHT_q : std_logic_vector(11 downto 0); - SIGNAL HBE : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HBE_d : std_logic_vector(11 downto 0); - SIGNAL HBE_q : std_logic_vector(11 downto 0); - SIGNAL HDB : std_logic_vector(11 downto 0); - SIGNAL HDB_d : std_logic_vector(11 downto 0); - SIGNAL HDB_q : std_logic_vector(11 downto 0); - SIGNAL HDE : std_logic_vector(11 downto 0); - SIGNAL HDE_d : std_logic_vector(11 downto 0); - SIGNAL HDE_q : std_logic_vector(11 downto 0); - SIGNAL HBB : std_logic_vector(11 downto 0); - SIGNAL HBB_d : std_logic_vector(11 downto 0); - SIGNAL HBB_q : std_logic_vector(11 downto 0); - SIGNAL HSS : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HSS_d : std_logic_vector(11 downto 0); - SIGNAL HSS_q : std_logic_vector(11 downto 0); - SIGNAL RAND_OBEN : std_logic_vector(10 downto 0); - SIGNAL VDIS_START : std_logic_vector(10 downto 0); - SIGNAL VDIS_END : std_logic_vector(10 downto 0); - SIGNAL RAND_UNTEN : std_logic_vector(10 downto 0); - SIGNAL VS_START : std_logic_vector(10 downto 0); - SIGNAL V_TOTAL : std_logic_vector(10 downto 0); - SIGNAL VBE : std_logic_vector(10 downto 0); - SIGNAL VBE_d : std_logic_vector(10 downto 0); - SIGNAL VBE_q : std_logic_vector(10 downto 0); - SIGNAL VDB : std_logic_vector(10 downto 0); - SIGNAL VDB_d : std_logic_vector(10 downto 0); - SIGNAL VDB_q : std_logic_vector(10 downto 0); - SIGNAL VDE : std_logic_vector(10 downto 0); - SIGNAL VDE_d : std_logic_vector(10 downto 0); - SIGNAL VDE_q : std_logic_vector(10 downto 0); - SIGNAL VBB : std_logic_vector(10 downto 0); - SIGNAL VBB_d : std_logic_vector(10 downto 0); - SIGNAL VBB_q : std_logic_vector(10 downto 0); - SIGNAL VSS : std_logic_vector(10 downto 0); - SIGNAL VSS_d : std_logic_vector(10 downto 0); - SIGNAL VSS_q : std_logic_vector(10 downto 0); - SIGNAL VFT : std_logic_vector(10 downto 0); - SIGNAL VFT_d : std_logic_vector(10 downto 0); - SIGNAL VFT_q : std_logic_vector(10 downto 0); - SIGNAL VCO : std_logic_vector(8 downto 0); - SIGNAL VCO_d : std_logic_vector(8 downto 0); - SIGNAL VCO_ena : std_logic_vector(8 downto 0); - SIGNAL VCO_q : std_logic_vector(8 downto 0); - SIGNAL VCNTRL : std_logic_vector(3 downto 0) := (OTHERS => '0'); - SIGNAL VCNTRL_d : std_logic_vector(3 downto 0); - SIGNAL VCNTRL_q : std_logic_vector(3 downto 0); - SIGNAL u0_data : std_logic_vector(15 downto 0); - SIGNAL u0_tridata : std_logic_vector(15 downto 0); - SIGNAL u1_data : std_logic_vector(15 downto 0); - SIGNAL u1_tridata : std_logic_vector(15 downto 0); - -- SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; - SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic; - -- SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; - SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; - SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + signal VR_DOUT : std_logic_vector(8 downto 0); + signal VR_DOUT_d : std_logic_vector(8 downto 0); + signal VR_DOUT_q : std_logic_vector(8 downto 0); + signal VR_FRQ : unsigned(7 downto 0); + signal VR_FRQ_d : std_logic_vector(7 downto 0); + signal VR_FRQ_q : std_logic_vector(7 downto 0); + signal FB_B : std_logic_vector(3 downto 0); + signal FB_16B : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); + signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); + signal CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1 : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0 : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); + signal ACP_VCTR : std_logic_vector(31 downto 0); + signal ACP_VCTR_d : std_logic_vector(31 downto 0); + signal ACP_VCTR_q : std_logic_vector(31 downto 0); + signal BORDER_COLOR_d : std_logic_vector(23 downto 0); + signal BORDER_COLOR_q : std_logic_vector(23 downto 0); + signal SYS_CTR : std_logic_vector(6 downto 0); + signal SYS_CTR_d : std_logic_vector(6 downto 0); + signal SYS_CTR_q : std_logic_vector(6 downto 0); + signal LOF : std_logic_vector(15 downto 0); + signal LOF_d : std_logic_vector(15 downto 0); + signal LOF_q : std_logic_vector(15 downto 0); + signal LWD : std_logic_vector(15 downto 0); + signal LWD_d : std_logic_vector(15 downto 0); + signal LWD_q : std_logic_vector(15 downto 0); + signal HSYNC_I : std_logic_vector(7 downto 0); + signal HSYNC_I_d : std_logic_vector(7 downto 0); + signal HSYNC_I_q : std_logic_vector(7 downto 0); + signal HSY_LEN : std_logic_vector(7 downto 0); + signal HSY_LEN_d : std_logic_vector(7 downto 0); + signal HSY_LEN_q : std_logic_vector(7 downto 0); + signal VSYNC_I : std_logic_vector(2 downto 0); + signal VSYNC_I_d : std_logic_vector(2 downto 0); + signal VSYNC_I_q : std_logic_vector(2 downto 0); + signal VHCNT : std_logic_vector(11 downto 0); + signal VHCNT_d : std_logic_vector(11 downto 0); + signal VHCNT_q : std_logic_vector(11 downto 0); + signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); + signal VVCNT : std_logic_vector(10 downto 0); + signal VVCNT_d : std_logic_vector(10 downto 0); + signal VVCNT_q : std_logic_vector(10 downto 0); + signal VERZ2 : std_logic_vector(9 downto 0); + signal VERZ2_d : std_logic_vector(9 downto 0); + signal VERZ2_q : std_logic_vector(9 downto 0); + signal VERZ1 : std_logic_vector(9 downto 0); + signal VERZ1_d : std_logic_vector(9 downto 0); + signal VERZ1_q : std_logic_vector(9 downto 0); + signal VERZ0 : std_logic_vector(9 downto 0); + signal VERZ0_d : std_logic_vector(9 downto 0); + signal VERZ0_q : std_logic_vector(9 downto 0); + signal RAND : std_logic_vector(6 downto 0) := (others => '0'); + signal RAND_d : std_logic_vector(6 downto 0); + signal RAND_q : std_logic_vector(6 downto 0); + signal CCSEL_d : std_logic_vector(2 downto 0); + signal CCSEL_q : std_logic_vector(2 downto 0); + signal ATARI_HH : std_logic_vector(31 downto 0) := (others => '0'); + signal ATARI_HH_d : std_logic_vector(31 downto 0); + signal ATARI_HH_q : std_logic_vector(31 downto 0); + signal ATARI_VH : std_logic_vector(31 downto 0); + signal ATARI_VH_d : std_logic_vector(31 downto 0); + signal ATARI_VH_q : std_logic_vector(31 downto 0); + signal ATARI_HL : std_logic_vector(31 downto 0) := (others => '0'); + signal ATARI_HL_d : std_logic_vector(31 downto 0); + signal ATARI_HL_q : std_logic_vector(31 downto 0); + signal ATARI_VL : std_logic_vector(31 downto 0); + signal ATARI_VL_d : std_logic_vector(31 downto 0); + signal ATARI_VL_q : std_logic_vector(31 downto 0); + signal RAND_LINKS : std_logic_vector(11 downto 0); + signal HDIS_START : std_logic_vector(11 downto 0); + signal HDIS_END : std_logic_vector(11 downto 0); + signal RAND_RECHTS : std_logic_vector(11 downto 0); + signal HS_START : std_logic_vector(11 downto 0); + signal H_TOTAL : std_logic_vector(11 downto 0); + signal HDIS_LEN : std_logic_vector(11 downto 0); + signal MULF : std_logic_vector(5 downto 0); + signal HHT : std_logic_vector(11 downto 0) := (others => '0'); + signal HHT_d : std_logic_vector(11 downto 0); + signal HHT_q : std_logic_vector(11 downto 0); + signal HBE : std_logic_vector(11 downto 0) := (others => '0'); + signal HBE_d : std_logic_vector(11 downto 0); + signal HBE_q : std_logic_vector(11 downto 0); + signal HDB : std_logic_vector(11 downto 0); + signal HDB_d : std_logic_vector(11 downto 0); + signal HDB_q : std_logic_vector(11 downto 0); + signal HDE : std_logic_vector(11 downto 0); + signal HDE_d : std_logic_vector(11 downto 0); + signal HDE_q : std_logic_vector(11 downto 0); + signal HBB : std_logic_vector(11 downto 0); + signal HBB_d : std_logic_vector(11 downto 0); + signal HBB_q : std_logic_vector(11 downto 0); + signal HSS : std_logic_vector(11 downto 0) := (others => '0'); + signal HSS_d : std_logic_vector(11 downto 0); + signal HSS_q : std_logic_vector(11 downto 0); + signal RAND_OBEN : std_logic_vector(10 downto 0); + signal VDIS_START : std_logic_vector(10 downto 0); + signal VDIS_END : std_logic_vector(10 downto 0); + signal RAND_UNTEN : std_logic_vector(10 downto 0); + signal VS_START : std_logic_vector(10 downto 0); + signal V_TOTAL : std_logic_vector(10 downto 0); + signal VBE : std_logic_vector(10 downto 0); + signal VBE_d : std_logic_vector(10 downto 0); + signal VBE_q : std_logic_vector(10 downto 0); + signal VDB : std_logic_vector(10 downto 0); + signal VDB_d : std_logic_vector(10 downto 0); + signal VDB_q : std_logic_vector(10 downto 0); + signal VDE : std_logic_vector(10 downto 0); + signal VDE_d : std_logic_vector(10 downto 0); + signal VDE_q : std_logic_vector(10 downto 0); + signal VBB : std_logic_vector(10 downto 0); + signal VBB_d : std_logic_vector(10 downto 0); + signal VBB_q : std_logic_vector(10 downto 0); + signal VSS : std_logic_vector(10 downto 0); + signal VSS_d : std_logic_vector(10 downto 0); + signal VSS_q : std_logic_vector(10 downto 0); + signal VFT : std_logic_vector(10 downto 0); + signal VFT_d : std_logic_vector(10 downto 0); + signal VFT_q : std_logic_vector(10 downto 0); + signal VCO : std_logic_vector(8 downto 0); + signal VCO_d : std_logic_vector(8 downto 0); + signal VCO_ena : std_logic_vector(8 downto 0); + signal VCO_q : std_logic_vector(8 downto 0); + signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); + signal VCNTRL_d : std_logic_vector(3 downto 0); + signal VCNTRL_q : std_logic_vector(3 downto 0); + signal u0_data : std_logic_vector(15 downto 0); + signal u0_tridata : std_logic_vector(15 downto 0); + signal u1_data : std_logic_vector(15 downto 0); + signal u1_tridata : std_logic_vector(15 downto 0); + -- signal ST_SHIFT_MODE0_clk_ctrl : std_logic; + signal ST_SHIFT_MODE0_ena_ctrl : std_logic; + -- signal FALCON_SHIFT_MODE0_clk_ctrl : std_logic; + signal FALCON_SHIFT_MODE8_ena_ctrl : std_logic; + signal FALCON_SHIFT_MODE0_ena_ctrl : std_logic; - SIGNAL ACP_VCTR24_ena_ctrl : std_logic; - SIGNAL ACP_VCTR16_ena_ctrl : std_logic; - SIGNAL ACP_VCTR8_ena_ctrl : std_logic; - SIGNAL ACP_VCTR6_ena_ctrl : std_logic; - SIGNAL ACP_VCTR0_ena_ctrl : std_logic; + signal ACP_VCTR24_ena_ctrl : std_logic; + signal ACP_VCTR16_ena_ctrl : std_logic; + signal ACP_VCTR8_ena_ctrl : std_logic; + signal ACP_VCTR6_ena_ctrl : std_logic; + signal ACP_VCTR0_ena_ctrl : std_logic; - SIGNAL ATARI_HH24_ena_ctrl : std_logic; - SIGNAL ATARI_HH16_ena_ctrl : std_logic; - SIGNAL ATARI_HH8_ena_ctrl : std_logic; - SIGNAL ATARI_HH0_ena_ctrl : std_logic; - SIGNAL ATARI_VH24_ena_ctrl : std_logic; - SIGNAL ATARI_VH16_ena_ctrl : std_logic; - SIGNAL ATARI_VH8_ena_ctrl : std_logic; - SIGNAL ATARI_VH0_ena_ctrl : std_logic; - SIGNAL ATARI_HL24_ena_ctrl : std_logic; - SIGNAL ATARI_HL16_ena_ctrl : std_logic; - SIGNAL ATARI_HL8_ena_ctrl : std_logic; - SIGNAL ATARI_HL0_ena_ctrl : std_logic; - SIGNAL ATARI_VL0_clk_ctrl : std_logic; - SIGNAL ATARI_VL24_ena_ctrl : std_logic; - SIGNAL ATARI_VL16_ena_ctrl : std_logic; - SIGNAL ATARI_VL8_ena_ctrl : std_logic; - SIGNAL ATARI_VL0_ena_ctrl : std_logic; - SIGNAL VR_DOUT0_ena_ctrl : std_logic; - SIGNAL VR_FRQ0_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR16_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR8_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR0_ena_ctrl : std_logic; - SIGNAL SYS_CTR0_ena_ctrl : std_logic; - SIGNAL LOF8_ena_ctrl : std_logic; - SIGNAL LOF0_ena_ctrl : std_logic; - SIGNAL LWD8_ena_ctrl : std_logic; - SIGNAL LWD0_ena_ctrl : std_logic; - SIGNAL HHT8_ena_ctrl : std_logic; - SIGNAL HHT0_ena_ctrl : std_logic; - SIGNAL HBE8_ena_ctrl : std_logic; - SIGNAL HBE0_ena_ctrl : std_logic; - SIGNAL HDB8_ena_ctrl : std_logic; - SIGNAL HDB0_ena_ctrl : std_logic; - SIGNAL HDE8_ena_ctrl : std_logic; - SIGNAL HDE0_ena_ctrl : std_logic; - SIGNAL HBB8_ena_ctrl : std_logic; - SIGNAL HBB0_ena_ctrl : std_logic; - SIGNAL HSS0_clk_ctrl : std_logic; - SIGNAL HSS8_ena_ctrl : std_logic; - SIGNAL HSS0_ena_ctrl : std_logic; - SIGNAL VBE8_ena_ctrl : std_logic; - SIGNAL VBE0_ena_ctrl : std_logic; - SIGNAL VDB8_ena_ctrl : std_logic; - SIGNAL VDB0_ena_ctrl : std_logic; - SIGNAL VDE8_ena_ctrl : std_logic; - SIGNAL VDE0_ena_ctrl : std_logic; - SIGNAL VBB8_ena_ctrl : std_logic; - SIGNAL VBB0_ena_ctrl : std_logic; - SIGNAL VSS8_ena_ctrl : std_logic; - SIGNAL VSS0_ena_ctrl : std_logic; - SIGNAL VFT8_ena_ctrl : std_logic; - SIGNAL VFT0_ena_ctrl : std_logic; - SIGNAL VCO0_ena_ctrl : std_logic; - SIGNAL VCNTRL0_ena_ctrl : std_logic; - SIGNAL VVCNT0_ena_ctrl : std_logic; - SIGNAL VSYNC_I0_ena_ctrl : std_logic; - SIGNAL SUB_PIXEL_CNT0_ena_ctrl : std_logic; - SIGNAL COLOR8_2 : std_logic; - SIGNAL COLOR8_1 : std_logic; - SIGNAL COLOR1_3 : std_logic; - SIGNAL COLOR1_2 : std_logic; - SIGNAL COLOR1_1 : std_logic; - SIGNAL COLOR4_2 : std_logic; - SIGNAL COLOR4_1 : std_logic; - SIGNAL COLOR16_2 : std_logic; - SIGNAL COLOR16_1 : std_logic; - SIGNAL gnd : std_logic; - SIGNAL u1_enabledt : std_logic; - SIGNAL u0_enabledt : std_logic; - SIGNAL VCNTRL_CS : std_logic; - SIGNAL VCO_CS : std_logic; - SIGNAL VFT_CS : std_logic; - SIGNAL VSS_CS : std_logic; - SIGNAL VBB_CS : std_logic; - SIGNAL VDE_CS : std_logic; - SIGNAL VDB_CS : std_logic; - SIGNAL VBE_CS : std_logic; - SIGNAL DOP_FIFO_CLR_q : std_logic; - SIGNAL DOP_FIFO_CLR_d : std_logic; - SIGNAL DOP_ZEI_q : std_logic; - SIGNAL DOP_ZEI_d : std_logic; - SIGNAL DOP_ZEI : std_logic; - SIGNAL INTER_ZEI_q : std_logic; - SIGNAL INTER_ZEI_d : std_logic; - SIGNAL ST_VIDEO : std_logic; - SIGNAL FALCON_VIDEO : std_logic; - SIGNAL HSS_CS : std_logic; - SIGNAL HBB_CS : std_logic; - SIGNAL HDE_CS : std_logic; - SIGNAL HDB_CS : std_logic; - SIGNAL HBE_CS : std_logic; - SIGNAL HHT_CS : std_logic; - SIGNAL ATARI_VL_CS : std_logic; - SIGNAL ATARI_HL_CS : std_logic; - SIGNAL ATARI_VH_CS : std_logic; - SIGNAL ATARI_HH_CS : std_logic; - SIGNAL ATARI_SYNC : std_logic; - SIGNAL COLOR24 : std_logic; - SIGNAL COLOR16 : std_logic; - SIGNAL SYNC_PIX2_q : std_logic; - SIGNAL SYNC_PIX2_d : std_logic; - SIGNAL SYNC_PIX2 : std_logic; - SIGNAL SYNC_PIX1_q : std_logic; - SIGNAL SYNC_PIX1_d : std_logic; - SIGNAL SYNC_PIX1 : std_logic; - SIGNAL SYNC_PIX_q : std_logic; - SIGNAL SYNC_PIX_d : std_logic; - SIGNAL SYNC_PIX : std_logic; - SIGNAL START_ZEILE_q : std_logic; - SIGNAL START_ZEILE_ena : std_logic; - SIGNAL START_ZEILE_d : std_logic; - SIGNAL START_ZEILE : std_logic; - SIGNAL CLR_FIFO_q : std_logic; - SIGNAL CLR_FIFO_ena : std_logic; - SIGNAL CLR_FIFO_d : std_logic; - SIGNAL FIFO_RDE_q : std_logic; - SIGNAL FIFO_RDE_d : std_logic; - SIGNAL RAND_ON : std_logic; - SIGNAL VCO_OFF_q : std_logic; - SIGNAL VCO_OFF_d : std_logic; - SIGNAL VCO_OFF : std_logic; - SIGNAL VCO_ON_q : std_logic; - SIGNAL VCO_ON_d : std_logic; - SIGNAL VCO_ON : std_logic; - SIGNAL VCO_ZL_q : std_logic; - SIGNAL VCO_ZL_ena : std_logic; - SIGNAL VCO_ZL_d : std_logic; - SIGNAL VCO_ZL : std_logic; - SIGNAL VDTRON_q : std_logic; - SIGNAL VDTRON_d : std_logic; - SIGNAL VDTRON : std_logic; - SIGNAL DPO_OFF_q : std_logic; - SIGNAL DPO_OFF_d : std_logic; - SIGNAL DPO_OFF : std_logic; - SIGNAL DPO_ON_q : std_logic; - SIGNAL DPO_ON_d : std_logic; - SIGNAL DPO_ON : std_logic; - SIGNAL DPO_ZL_q : std_logic; - SIGNAL DPO_ZL_ena : std_logic; - SIGNAL DPO_ZL_d : std_logic; - SIGNAL DPO_ZL : std_logic; - SIGNAL DISP_ON_q : std_logic; - SIGNAL DISP_ON_d : std_logic; - SIGNAL DISP_ON : std_logic; - SIGNAL nBLANK_q : std_logic; - SIGNAL nBLANK_d : std_logic; - SIGNAL VSYNC_START_q : std_logic; - SIGNAL VSYNC_START_ena : std_logic; - SIGNAL VSYNC_START_d : std_logic; - SIGNAL VSYNC_START : std_logic; - SIGNAL VSYNC_q : std_logic; - SIGNAL VSYNC_d : std_logic; - SIGNAL LAST_q : std_logic; - SIGNAL LAST_d : std_logic; - SIGNAL LAST : std_logic; - SIGNAL HSYNC_START_q : std_logic; - SIGNAL HSYNC_START_d : std_logic; - SIGNAL HSYNC_START : std_logic; - SIGNAL HSYNC_q : std_logic; - SIGNAL HSYNC_d : std_logic; - SIGNAL CLUT_TA_q : std_logic; - SIGNAL CLUT_TA_d : std_logic; - SIGNAL CLUT_TA : std_logic; - SIGNAL LWD_CS : std_logic; - SIGNAL LOF_CS : std_logic; - SIGNAL SYS_CTR_CS : std_logic; - SIGNAL ACP_VIDEO_ON : std_logic; - SIGNAL BORDER_COLOR_CS : std_logic; - SIGNAL ACP_VCTR_CS : std_logic; - SIGNAL FALCON_SHIFT_MODE_CS : std_logic; - SIGNAL ST_SHIFT_MODE_CS : std_logic; - SIGNAL ST_CLUT : std_logic; - SIGNAL ST_CLUT_CS : std_logic; - SIGNAL FALCON_CLUT : std_logic; - SIGNAL FALCON_CLUT_CS : std_logic; - SIGNAL VIDEO_RECONFIG_q : std_logic; - SIGNAL VIDEO_RECONFIG_d : std_logic; - SIGNAL VIDEO_PLL_RECONFIG_CS : std_logic; - SIGNAL VR_WR_q : std_logic; - SIGNAL VR_WR_d : std_logic; - SIGNAL VIDEO_PLL_CONFIG_CS : std_logic; - SIGNAL ACP_CLUT : std_logic; - SIGNAL ACP_CLUT_CS : std_logic; - SIGNAL CLK13M_q : std_logic; - SIGNAL CLK13M_d : std_logic; - SIGNAL CLK13M : std_logic; - SIGNAL CLK17M_q : std_logic; - SIGNAL CLK17M_d : std_logic; - SIGNAL CLK17M : std_logic; - SIGNAL color4_i : std_logic; - SIGNAL pixel_clk_i : std_logic; + signal ATARI_HH24_ena_ctrl : std_logic; + signal ATARI_HH16_ena_ctrl : std_logic; + signal ATARI_HH8_ena_ctrl : std_logic; + signal ATARI_HH0_ena_ctrl : std_logic; + signal ATARI_VH24_ena_ctrl : std_logic; + signal ATARI_VH16_ena_ctrl : std_logic; + signal ATARI_VH8_ena_ctrl : std_logic; + signal ATARI_VH0_ena_ctrl : std_logic; + signal ATARI_HL24_ena_ctrl : std_logic; + signal ATARI_HL16_ena_ctrl : std_logic; + signal ATARI_HL8_ena_ctrl : std_logic; + signal ATARI_HL0_ena_ctrl : std_logic; + signal ATARI_VL0_clk_ctrl : std_logic; + signal ATARI_VL24_ena_ctrl : std_logic; + signal ATARI_VL16_ena_ctrl : std_logic; + signal ATARI_VL8_ena_ctrl : std_logic; + signal ATARI_VL0_ena_ctrl : std_logic; + signal VR_DOUT0_ena_ctrl : std_logic; + signal VR_FRQ0_ena_ctrl : std_logic; + signal BORDER_COLOR16_ena_ctrl : std_logic; + signal BORDER_COLOR8_ena_ctrl : std_logic; + signal BORDER_COLOR0_ena_ctrl : std_logic; + signal SYS_CTR0_ena_ctrl : std_logic; + signal LOF8_ena_ctrl : std_logic; + signal LOF0_ena_ctrl : std_logic; + signal LWD8_ena_ctrl : std_logic; + signal LWD0_ena_ctrl : std_logic; + signal HHT8_ena_ctrl : std_logic; + signal HHT0_ena_ctrl : std_logic; + signal HBE8_ena_ctrl : std_logic; + signal HBE0_ena_ctrl : std_logic; + signal HDB8_ena_ctrl : std_logic; + signal HDB0_ena_ctrl : std_logic; + signal HDE8_ena_ctrl : std_logic; + signal HDE0_ena_ctrl : std_logic; + signal HBB8_ena_ctrl : std_logic; + signal HBB0_ena_ctrl : std_logic; + signal HSS0_clk_ctrl : std_logic; + signal HSS8_ena_ctrl : std_logic; + signal HSS0_ena_ctrl : std_logic; + signal VBE8_ena_ctrl : std_logic; + signal VBE0_ena_ctrl : std_logic; + signal VDB8_ena_ctrl : std_logic; + signal VDB0_ena_ctrl : std_logic; + signal VDE8_ena_ctrl : std_logic; + signal VDE0_ena_ctrl : std_logic; + signal VBB8_ena_ctrl : std_logic; + signal VBB0_ena_ctrl : std_logic; + signal VSS8_ena_ctrl : std_logic; + signal VSS0_ena_ctrl : std_logic; + signal VFT8_ena_ctrl : std_logic; + signal VFT0_ena_ctrl : std_logic; + signal VCO0_ena_ctrl : std_logic; + signal VCNTRL0_ena_ctrl : std_logic; + signal VVCNT0_ena_ctrl : std_logic; + signal VSYNC_I0_ena_ctrl : std_logic; + signal SUB_PIXEL_CNT0_ena_ctrl : std_logic; + signal COLOR8_2 : std_logic; + signal COLOR8_1 : std_logic; + signal COLOR1_3 : std_logic; + signal COLOR1_2 : std_logic; + signal COLOR1_1 : std_logic; + signal COLOR4_2 : std_logic; + signal COLOR4_1 : std_logic; + signal COLOR16_2 : std_logic; + signal COLOR16_1 : std_logic; + signal gnd : std_logic; + signal u1_enabledt : std_logic; + signal u0_enabledt : std_logic; + signal VCNTRL_CS : std_logic; + signal VCO_CS : std_logic; + signal VFT_CS : std_logic; + signal VSS_CS : std_logic; + signal VBB_CS : std_logic; + signal VDE_CS : std_logic; + signal VDB_CS : std_logic; + signal VBE_CS : std_logic; + signal DOP_FIFO_CLR_q : std_logic; + signal DOP_FIFO_CLR_d : std_logic; + signal DOP_ZEI_q : std_logic; + signal DOP_ZEI_d : std_logic; + signal DOP_ZEI : std_logic; + signal INTER_ZEI_q : std_logic; + signal INTER_ZEI_d : std_logic; + signal ST_VIDEO : std_logic; + signal FALCON_VIDEO : std_logic; + signal HSS_CS : std_logic; + signal HBB_CS : std_logic; + signal HDE_CS : std_logic; + signal HDB_CS : std_logic; + signal HBE_CS : std_logic; + signal HHT_CS : std_logic; + signal ATARI_VL_CS : std_logic; + signal ATARI_HL_CS : std_logic; + signal ATARI_VH_CS : std_logic; + signal ATARI_HH_CS : std_logic; + signal ATARI_SYNC : std_logic; + signal COLOR24 : std_logic; + signal COLOR16 : std_logic; + signal SYNC_PIX2_q : std_logic; + signal SYNC_PIX2_d : std_logic; + signal SYNC_PIX2 : std_logic; + signal SYNC_PIX1_q : std_logic; + signal SYNC_PIX1_d : std_logic; + signal SYNC_PIX1 : std_logic; + signal SYNC_PIX_q : std_logic; + signal SYNC_PIX_d : std_logic; + signal SYNC_PIX : std_logic; + signal START_ZEILE_q : std_logic; + signal START_ZEILE_ena : std_logic; + signal START_ZEILE_d : std_logic; + signal START_ZEILE : std_logic; + signal CLR_FIFO_q : std_logic; + signal CLR_FIFO_ena : std_logic; + signal CLR_FIFO_d : std_logic; + signal FIFO_RDE_q : std_logic; + signal FIFO_RDE_d : std_logic; + signal RAND_ON : std_logic; + signal VCO_OFF_q : std_logic; + signal VCO_OFF_d : std_logic; + signal VCO_OFF : std_logic; + signal VCO_ON_q : std_logic; + signal VCO_ON_d : std_logic; + signal VCO_ON : std_logic; + signal VCO_ZL_q : std_logic; + signal VCO_ZL_ena : std_logic; + signal VCO_ZL_d : std_logic; + signal VCO_ZL : std_logic; + signal VDTRON_q : std_logic; + signal VDTRON_d : std_logic; + signal VDTRON : std_logic; + signal DPO_OFF_q : std_logic; + signal DPO_OFF_d : std_logic; + signal DPO_OFF : std_logic; + signal DPO_ON_q : std_logic; + signal DPO_ON_d : std_logic; + signal DPO_ON : std_logic; + signal DPO_ZL_q : std_logic; + signal DPO_ZL_ena : std_logic; + signal DPO_ZL_d : std_logic; + signal DPO_ZL : std_logic; + signal DISP_ON_q : std_logic; + signal DISP_ON_d : std_logic; + signal DISP_ON : std_logic; + signal nBLANK_q : std_logic; + signal nBLANK_d : std_logic; + signal VSYNC_START_q : std_logic; + signal VSYNC_START_ena : std_logic; + signal VSYNC_START_d : std_logic; + signal VSYNC_START : std_logic; + signal VSYNC_q : std_logic; + signal VSYNC_d : std_logic; + signal LAST_q : std_logic; + signal LAST_d : std_logic; + signal LAST : std_logic; + signal HSYNC_START_q : std_logic; + signal HSYNC_START_d : std_logic; + signal HSYNC_START : std_logic; + signal HSYNC_q : std_logic; + signal HSYNC_d : std_logic; + signal CLUT_TA_q : std_logic; + signal CLUT_TA_d : std_logic; + signal CLUT_TA : std_logic; + signal LWD_CS : std_logic; + signal LOF_CS : std_logic; + signal SYS_CTR_CS : std_logic; + signal ACP_VIDEO_ON : std_logic; + signal BORDER_COLOR_CS : std_logic; + signal ACP_VCTR_CS : std_logic; + signal FALCON_SHIFT_MODE_CS : std_logic; + signal ST_SHIFT_MODE_CS : std_logic; + signal ST_CLUT : std_logic; + signal ST_CLUT_CS : std_logic; + signal FALCON_CLUT : std_logic; + signal FALCON_CLUT_CS : std_logic; + signal VIDEO_RECONFIG_q : std_logic; + signal VIDEO_RECONFIG_d : std_logic; + signal VIDEO_PLL_RECONFIG_CS : std_logic; + signal VR_WR_q : std_logic; + signal VR_WR_d : std_logic; + signal VIDEO_PLL_CONFIG_CS : std_logic; + signal ACP_CLUT : std_logic; + signal ACP_CLUT_CS : std_logic; + signal CLK13M_q : std_logic; + signal CLK13M_d : std_logic; + signal CLK13M : std_logic; + signal CLK17M_q : std_logic; + signal CLK17M_d : std_logic; + signal CLK17M : std_logic; + signal color4_i : std_logic; + signal pixel_clk_i : std_logic; -- Sub Module Interface Section - - COMPONENT lpm_bustri_WORD - PORT - ( - data : IN std_logic_vector(15 downto 0); - enabledt : IN std_logic; - tridata : BUFFER std_logic_vector(15 downto 0) - ); - END COMPONENT lpm_bustri_WORD; - - FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS - VARIABLE ret : std_logic; - BEGIN - IF x THEN + function to_std_logic(X : in boolean) return std_logic is + variable ret : std_logic; + begin + if x then ret := '1'; else ret := '0'; - END IF; - RETURN ret; - END FUNCTION to_std_logic; + end if; + return ret; + end function to_std_logic; -- sizeIt replicates a value to an array of specific length. - FUNCTION sizeit(a : std_Logic; len : integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector(len - 1 downto 0); - BEGIN - FOR i IN rep'RANGE LOOP + function sizeit(a : std_Logic; len : integer) return std_logic_vector is + variable rep : std_logic_vector(len - 1 downto 0); + begin + for i in rep'range loop rep(i) := a; - END LOOP; - RETURN rep; - END FUNCTION sizeit; - -BEGIN + end loop; + return rep; + end function sizeit; +begin -- Sub Module Section u0 : entity work.lpm_bustri_WORD - PORT MAP + port map ( data => u0_data, enabledt => u0_enabledt, tridata => u0_tridata ); - u1 : lpm_bustri_WORD - PORT MAP + u1 : entity work.lpm_bustri_WORD + port map ( data => u1_data, enabledt => u1_enabledt, @@ -526,56 +516,56 @@ BEGIN CLUT_MUX_ADR <= CLUT_MUX_ADR_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; - END IF; - END PROCESS; + end if; + end process; HSYNC <= HSYNC_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then HSYNC_q <= HSYNC_d; - END IF; - END PROCESS; + end if; + end process; VSYNC <= VSYNC_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then VSYNC_q <= VSYNC_d; - END IF; - END PROCESS; + end if; + end process; nBLANK <= nBLANK_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then nBLANK_q <= nBLANK_d; - END IF; - END PROCESS; + end if; + end process; FIFO_RDE <= FIFO_RDE_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then FIFO_RDE_q <= FIFO_RDE_d; - END IF; - END PROCESS; + end if; + end process; BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - IF BORDER_COLOR16_ena_ctrl = '1' THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + if BORDER_COLOR16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); - END IF; - IF BORDER_COLOR8_ena_ctrl = '1' THEN + end if; + if BORDER_COLOR8_ena_ctrl = '1' THEN border_color_q(15 downto 8) <= border_color_d(15 downto 8); END IF; IF BORDER_COLOR0_ena_ctrl = '1' THEN @@ -1141,14 +1131,14 @@ BEGIN -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 10) = "000000000000000000"); + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 10) = "000000000000000000"); ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); - ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); + ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS, 4) and sizeIt(not nFB_WR, 4); CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not VIDEO_MOD_TA); -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 10) = "1111100110"); + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 10) = "1111100110"); -- HIGH WORD FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); @@ -1541,7 +1531,8 @@ BEGIN std_logic_vector'(d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else std_logic_vector'(d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else std_logic_vector'(d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else - std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1'; + std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else + (others => '0'); -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or @@ -1580,9 +1571,10 @@ BEGIN -- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- rand_links <= HBE_q when acp_video_on else - 12d"12" when not acp_video_on and atari_sync and vcntrl(2) else + 12d"21" when not acp_video_on and atari_sync and vcntrl(2) else 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else - std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync; + std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else + (others => '0'); /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or @@ -1593,7 +1585,7 @@ BEGIN -- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or - ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); + ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); @@ -1621,16 +1613,16 @@ BEGIN (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or - ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and - sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) - and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or - (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not - ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or + ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(ST_VIDEO,11)) or + ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); @@ -1805,6 +1797,6 @@ BEGIN COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; COLOR8 <= COLOR8_1 or COLOR8_2; - -- Define power SIGNAL(s) + -- Define power signal(s) gnd <= '0'; END ARCHITECTURE rtl;