Sync with Fredi's source tree 13/06/2015

Parallel port fix.

FPGA_by_Fredi/altiobuf_bidir0.cmp

@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altiobuf_bidir0
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataio		: INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+end component;