forked from Firebee/FPGA_Config
hold time fix test
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@@ -449,9 +449,18 @@ BEGIN
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END IF;
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END PROCESS;
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BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
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BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
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BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
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-- try if an aditional FF will help hold timing
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PROCESS
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BEGIN
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WAIT UNTIL rising_edge(main_clk);
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BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
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BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
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BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
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END PROCESS;
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-- BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
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-- BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
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-- BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
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PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN
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IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN
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