diff --git a/FPGA_by_Fredi/.gitignore b/FPGA_by_Fredi/.gitignore
index 56c4ab3..7a6e03d 100644
--- a/FPGA_by_Fredi/.gitignore
+++ b/FPGA_by_Fredi/.gitignore
@@ -1,6 +1,8 @@
-
+datetime.vhd
 db
 incremental_db
+greybox_tmp
+*.bak
 *.rpt
 *.summary
 *.sof
@@ -8,5 +10,6 @@ incremental_db
 *.pin
 *.smsg
 *.jdi
+*.cdf
 PLLJ_PLLSPE_INFO.txt
 
diff --git a/FPGA_by_Fredi/FPGA_DATE.inc b/FPGA_by_Fredi/FPGA_DATE.inc
deleted file mode 100644
index 2aab8ca..0000000
--- a/FPGA_by_Fredi/FPGA_DATE.inc
+++ /dev/null
@@ -1,23 +0,0 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION FPGA_DATE 
-(
-
-)
-
-RETURNS (
-	result[31..0]
-);
diff --git a/FPGA_by_Fredi/FPGA_DATE.qip b/FPGA_by_Fredi/FPGA_DATE.qip
deleted file mode 100644
index 8a1183f..0000000
--- a/FPGA_by_Fredi/FPGA_DATE.qip
+++ /dev/null
@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.tdf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.inc"]
diff --git a/FPGA_by_Fredi/FPGA_DATE.tdf b/FPGA_by_Fredi/FPGA_DATE.tdf
deleted file mode 100644
index 5a3bc40..0000000
--- a/FPGA_by_Fredi/FPGA_DATE.tdf
+++ /dev/null
@@ -1,79 +0,0 @@
--- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: lpm_constant 
-
--- ============================================================
--- File Name: FPGA_DATE.tdf
--- Megafunction Name(s):
--- 			lpm_constant
---
--- Simulation Library Files(s):
--- 			
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
--- Clearbox generated function header
-FUNCTION FPGA_DATE_lpm_constant_f19 ()
-RETURNS ( result[31..0]);
-
-
-
-
-SUBDESIGN FPGA_DATE
-(
-	result[31..0]	 : OUTPUT;
-)
-
-VARIABLE
-
-	FPGA_DATE_lpm_constant_f19_component : FPGA_DATE_lpm_constant_f19;
-
-BEGIN
-
-	result[31..0] = FPGA_DATE_lpm_constant_f19_component.result[31..0];
-END;
-
-
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "16"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "570826775"
--- Retrieval info: PRIVATE: nBit NUMERIC "32"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "570826775"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
--- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
--- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.tdf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
deleted file mode 100644
index de971cf..0000000
--- a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
+++ /dev/null
@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=21062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_e19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00100001000001100010000000010111";
-END;
---VALID FILE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
deleted file mode 100644
index 025fbc8..0000000
--- a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
+++ /dev/null
@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=22062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_f19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00100010000001100010000000010111";
-END;
---VALID FILE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf
deleted file mode 100644
index 55f9ec1..0000000
--- a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf
+++ /dev/null
@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=05062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_g19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00000101000001100010000000010111";
-END;
---VALID FILE
diff --git a/FPGA_by_Fredi/altpll1.bsf b/FPGA_by_Fredi/altpll1.bsf
index c0cf5ba..0b27464 100644
--- a/FPGA_by_Fredi/altpll1.bsf
+++ b/FPGA_by_Fredi/altpll1.bsf
@@ -1,100 +1,100 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 272 184)
-	(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 25 180)(font "Arial" ))
-	(port
-		(pt 0 64)
-		(input)
-		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 40 64)(line_width 1))
-	)
-	(port
-		(pt 272 64)
-		(output)
-		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
-		(line (pt 272 64)(pt 224 64)(line_width 1))
-	)
-	(port
-		(pt 272 80)
-		(output)
-		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
-		(line (pt 272 80)(pt 224 80)(line_width 1))
-	)
-	(port
-		(pt 272 96)
-		(output)
-		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
-		(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
-		(line (pt 272 96)(pt 224 96)(line_width 1))
-	)
-	(port
-		(pt 272 112)
-		(output)
-		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
-		(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
-		(line (pt 272 112)(pt 224 112)(line_width 1))
-	)
-	(drawing
-		(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
-		(text "Clk " (rect 51 96 68 108)(font "Arial" ))
-		(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
-		(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
-		(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
-		(text "c0" (rect 54 111 64 123)(font "Arial" ))
-		(text "16/11" (rect 83 111 106 123)(font "Arial" ))
-		(text "0.00" (rect 127 111 145 123)(font "Arial" ))
-		(text "50.00" (rect 160 111 183 123)(font "Arial" ))
-		(text "c1" (rect 54 126 64 138)(font "Arial" ))
-		(text "16/33" (rect 83 126 106 138)(font "Arial" ))
-		(text "0.00" (rect 127 126 145 138)(font "Arial" ))
-		(text "50.00" (rect 160 126 183 138)(font "Arial" ))
-		(text "c2" (rect 54 141 64 153)(font "Arial" ))
-		(text "1024/1375" (rect 73 141 116 153)(font "Arial" ))
-		(text "0.00" (rect 127 141 145 153)(font "Arial" ))
-		(text "50.00" (rect 160 141 183 153)(font "Arial" ))
-		(line (pt 0 0)(pt 273 0)(line_width 1))
-		(line (pt 273 0)(pt 273 185)(line_width 1))
-		(line (pt 0 185)(pt 273 185)(line_width 1))
-		(line (pt 0 0)(pt 0 185)(line_width 1))
-		(line (pt 48 94)(pt 189 94)(line_width 1))
-		(line (pt 48 108)(pt 189 108)(line_width 1))
-		(line (pt 48 123)(pt 189 123)(line_width 1))
-		(line (pt 48 138)(pt 189 138)(line_width 1))
-		(line (pt 48 153)(pt 189 153)(line_width 1))
-		(line (pt 48 94)(pt 48 153)(line_width 1))
-		(line (pt 70 94)(pt 70 153)(line_width 3))
-		(line (pt 118 94)(pt 118 153)(line_width 3))
-		(line (pt 153 94)(pt 153 153)(line_width 3))
-		(line (pt 188 94)(pt 188 153)(line_width 1))
-		(line (pt 40 48)(pt 224 48)(line_width 1))
-		(line (pt 224 48)(pt 224 168)(line_width 1))
-		(line (pt 40 168)(pt 224 168)(line_width 1))
-		(line (pt 40 48)(pt 40 168)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 272 176)
+	(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 161 26 172)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 272 64)
+		(output)
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 80)
+		(output)
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 96)
+		(output)
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 112)
+		(output)
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
+		(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
+		(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 91 227 192)(font "Arial" ))
+		(text "DC (%)" (rect 133 91 298 192)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
+		(text "16/11" (rect 71 104 164 218)(font "Arial" ))
+		(text "0.00" (rect 104 104 227 218)(font "Arial" ))
+		(text "50.00" (rect 137 104 298 218)(font "Arial" ))
+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
+		(text "16/33" (rect 71 117 165 244)(font "Arial" ))
+		(text "0.00" (rect 104 117 227 244)(font "Arial" ))
+		(text "50.00" (rect 137 117 298 244)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
+		(text "32/43" (rect 71 130 166 270)(font "Arial" ))
+		(text "0.00" (rect 104 130 227 270)(font "Arial" ))
+		(text "50.00" (rect 137 130 298 270)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0))
+		(line (pt 273 0)(pt 273 177))
+		(line (pt 0 177)(pt 273 177))
+		(line (pt 0 0)(pt 0 177))
+		(line (pt 48 89)(pt 165 89))
+		(line (pt 48 101)(pt 165 101))
+		(line (pt 48 114)(pt 165 114))
+		(line (pt 48 127)(pt 165 127))
+		(line (pt 48 140)(pt 165 140))
+		(line (pt 48 89)(pt 48 140))
+		(line (pt 68 89)(pt 68 140)(line_width 3))
+		(line (pt 95 89)(pt 95 140)(line_width 3))
+		(line (pt 130 89)(pt 130 140)(line_width 3))
+		(line (pt 164 89)(pt 164 140))
+		(line (pt 40 48)(pt 223 48))
+		(line (pt 223 48)(pt 223 159))
+		(line (pt 40 159)(pt 223 159))
+		(line (pt 40 48)(pt 40 159))
+		(line (pt 271 64)(pt 223 64))
+		(line (pt 271 80)(pt 223 80))
+		(line (pt 271 96)(pt 223 96))
+		(line (pt 271 112)(pt 223 112))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll1.cmp b/FPGA_by_Fredi/altpll1.cmp
index 300576d..75df12e 100644
--- a/FPGA_by_Fredi/altpll1.cmp
+++ b/FPGA_by_Fredi/altpll1.cmp
@@ -1,25 +1,25 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component altpll1
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll1
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll1.inc b/FPGA_by_Fredi/altpll1.inc
index 0923ad2..aafe483 100644
--- a/FPGA_by_Fredi/altpll1.inc
+++ b/FPGA_by_Fredi/altpll1.inc
@@ -1,26 +1,26 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION altpll1 
-(
-	inclk0
-)
-
-RETURNS (
-	c0,
-	c1,
-	c2,
-	locked
-);
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll1 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	locked
+);
diff --git a/FPGA_by_Fredi/altpll1.ppf b/FPGA_by_Fredi/altpll1.ppf
index 0f38a28..d292d4b 100644
--- a/FPGA_by_Fredi/altpll1.ppf
+++ b/FPGA_by_Fredi/altpll1.ppf
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll1.qip b/FPGA_by_Fredi/altpll1.qip
index ec03f05..01791b7 100644
--- a/FPGA_by_Fredi/altpll1.qip
+++ b/FPGA_by_Fredi/altpll1.qip
@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
diff --git a/FPGA_by_Fredi/altpll1.vhd b/FPGA_by_Fredi/altpll1.vhd
index 001d73b..a797b2a 100644
--- a/FPGA_by_Fredi/altpll1.vhd
+++ b/FPGA_by_Fredi/altpll1.vhd
@@ -1,423 +1,423 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: altpll1.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY altpll1 IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END altpll1;
-
-
-ARCHITECTURE SYN OF altpll1 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire3    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
-	sub_wire1    <= sub_wire0(0);
-	c0    <= sub_wire1;
-	c1    <= sub_wire2;
-	c2    <= sub_wire3;
-	locked    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 11,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 16,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 33,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 16,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 1375,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 1024,
-		clk2_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 30303,
-		intended_device_family => "Cyclone III",
-		lpm_type => "altpll",
-		operation_mode => "SOURCE_SYNCHRONOUS",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "OFF",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0,
-		locked => sub_wire4
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll1.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll1 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END altpll1;
+
+
+ARCHITECTURE SYN OF altpll1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 16,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 33,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 16,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 43,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 32,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "43"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.558140"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "32"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "43"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "32"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/FPGA_DATE.bsf b/FPGA_by_Fredi/compile_date.bsf
similarity index 55%
rename from FPGA_by_Fredi/FPGA_DATE.bsf
rename to FPGA_by_Fredi/compile_date.bsf
index 44e6599..6d1a049 100644
--- a/FPGA_by_Fredi/FPGA_DATE.bsf
+++ b/FPGA_by_Fredi/compile_date.bsf
@@ -1,42 +1,29 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 88 48)
-	(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
-	(port
-		(pt 88 24)
-		(output)
-		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 85 -31 98 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 88 24)(pt 72 24)(line_width 3))
-	)
-	(drawing
-		(text "570826775" (rect 27 18 72 30)(font "Arial" ))
-		(text "32" (rect 77 25 87 37)(font "Arial" ))
-		(line (pt 16 16)(pt 72 16)(line_width 1))
-		(line (pt 72 16)(pt 72 32)(line_width 1))
-		(line (pt 72 32)(pt 16 32)(line_width 1))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 72 28)(pt 80 20)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 64 64)
+	(text "compile_date" (rect 5 0 56 12)(font "Arial" ))
+	(text "inst" (rect 8 32 20 44)(font "Arial" ))
+	(drawing
+		(rectangle (rect 16 16 32 32)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/compile_date.vhd b/FPGA_by_Fredi/compile_date.vhd
new file mode 100644
index 0000000..8834c8c
--- /dev/null
+++ b/FPGA_by_Fredi/compile_date.vhd
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.datetime.all;
+
+entity compile_date is
+    port
+    (
+        datetime    : out std_ulogic_vector(31 downto 0)
+    );
+end entity compile_date;
+
+architecture rtl of compile_date is
+begin
+    datetime <= work.datetime.DATE_HEX_DMY;
+end architecture rtl;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
index dfd4093..9507cbf 100644
--- a/FPGA_by_Fredi/firebee1.bdf
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -1,6089 +1,6083 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-//#pragma file_not_in_maxplusii_format
-(header "graphic" (version "1.3"))
-(properties
-	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
-)
-(pin
-	(input)
-	(rect 208 1392 376 1408)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "FB_ALE" (rect 9 0 49 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 160 1408 208 1424))
-)
-(pin
-	(input)
-	(rect 992 936 1160 952)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nFB_WR" (rect 9 0 53 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 952 992 968))
-)
-(pin
-	(input)
-	(rect 992 960 1160 976)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS1" (rect 9 0 56 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 976 992 992))
-)
-(pin
-	(input)
-	(rect 992 984 1160 1000)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS2" (rect 9 0 56 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1000 992 1016))
-)
-(pin
-	(input)
-	(rect 1008 360 1176 376)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS3" (rect 9 0 56 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 960 376 1008 392))
-)
-(pin
-	(input)
-	(rect 992 1008 1160 1024)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "FB_SIZE0" (rect 9 0 59 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1024 992 1040))
-)
-(pin
-	(input)
-	(rect 992 1032 1160 1048)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "FB_SIZE1" (rect 9 0 59 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1048 992 1064))
-)
-(pin
-	(input)
-	(rect 992 1056 1160 1072)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nFB_BURST" (rect 9 0 71 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1072 992 1088))
-)
-(pin
-	(input)
-	(rect 936 1168 1104 1184)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "LP_BUSY" (rect 9 0 58 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1184 936 1200))
-)
-(pin
-	(input)
-	(rect 856 1200 1024 1216)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nACSI_DRQ" (rect 9 0 71 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 808 1216 856 1232))
-)
-(pin
-	(input)
-	(rect 856 1224 1024 1240)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "nACSI_INT" (rect 9 0 64 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 808 1240 856 1256))
-)
-(pin
-	(input)
-	(rect 936 1392 1104 1408)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "RxD" (rect 9 0 31 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1408 936 1424))
-)
-(pin
-	(input)
-	(rect 936 1416 1104 1432)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "CTS" (rect 9 0 30 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1432 936 1448))
-)
-(pin
-	(input)
-	(rect 936 1440 1104 1456)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "RI" (rect 9 0 20 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1456 936 1472))
-)
-(pin
-	(input)
-	(rect 936 1464 1104 1480)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "DCD" (rect 9 0 33 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1480 936 1496))
-)
-(pin
-	(input)
-	(rect 608 1488 776 1504)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "AMKB_RX" (rect 9 0 58 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 520 1472 608 1504))
-)
-(pin
-	(input)
-	(rect 608 1512 776 1528)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "PIC_AMKB_RX" (rect 9 0 83 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 560 1528 608 1544))
-)
-(pin
-	(input)
-	(rect 936 1544 1104 1560)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "IDE_RDY" (rect 9 0 58 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1560 936 1576))
-)
-(pin
-	(input)
-	(rect 936 1568 1104 1584)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "IDE_INT" (rect 9 0 51 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1584 936 1600))
-)
-(pin
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-		(pt 408 744)
-		(bidir)
-		)
-	(mapper
-		(pt 408 768)
-		(bidir)
-		)
-	(mapper
-		(pt 408 792)
-		(bidir)
-		)
-	(mapper
-		(pt 408 816)
-		(bidir)
-		)
-	(mapper
-		(pt 408 840)
-		(bidir)
-		)
-	(mapper
-		(pt 0 856)
-		(bidir)
-		)
-	(mapper
-		(pt 408 872)
-		(bidir)
-		)
-	(mapper
-		(pt 408 896)
-		(bidir)
-		)
-	(mapper
-		(pt 408 920)
-		(bidir)
-		)
-	(mapper
-		(pt 408 944)
-		(bidir)
-		)
-	(mapper
-		(pt 0 912)
-		(bidir)
-		)
-	(mapper
-		(pt 0 936)
-		(bidir)
-		)
-	(mapper
-		(pt 0 960)
-		(bidir)
-		)
-	(mapper
-		(pt 0 984)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1008)
-		(bidir)
-		)
-	(mapper
-		(pt 408 976)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1000)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1072)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1096)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1256)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1040)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1064)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1088)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1112)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1136)
-		(bidir)
-		)
-	(mapper
-		(pt 0 432)
-		(bidir)
-		)
-	(mapper
-		(pt 0 464)
-		(bidir)
-		)
-	(mapper
-		(pt 0 488)
-		(bidir)
-		)
-	(mapper
-		(pt 0 520)
-		(bidir)
-		)
-	(mapper
-		(pt 0 544)
-		(bidir)
-		)
-	(mapper
-		(pt 0 568)
-		(bidir)
-		)
-	(mapper
-		(pt 0 592)
-		(bidir)
-		)
-	(mapper
-		(pt 0 320)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 344)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1168)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1192)
-		(bidir)
-		)
-	(mapper
-		(pt 0 368)
-		(bidir)
-		)
-	(mapper
-		(pt 0 392)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 408 48)
-		(bidir)
-		)
-	(mapper
-		(pt 408 16)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1240)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1304)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1200)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1344)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1280)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1224)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1120)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1048)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1024)
-		(bidir)
-		)
-	(mapper
-		(pt 0 32)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1368)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1264)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1336)
-		(bidir)
-		)
-	(mapper
-		(pt 0 888)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1480)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1504)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1392)
-		(bidir)
-		)
-	(mapper
-		(pt 408 1544)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1408)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1488)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1440)
-		(bidir)
-		)
-	(mapper
-		(pt 0 1464)
-		(bidir)
-		)
-)
-(block
-	(rect 1264 2944 1672 3560)
-	(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" ))	(block_io "CLK33M" (input))
-	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "nFB_BURST" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "nRSTO" (input))
-	(block_io "nFB_CS3" (input))
-	(block_io "nSRCS" (output))
-	(block_io "nSRBLE" (output))
-	(block_io "nSRBHE" (output))
-	(block_io "nSRWE" (output))
-	(block_io "nSROE" (output))
-	(block_io "DSP_INT" (output))
-	(block_io "DSP_TA" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(block_io "IO[17..0]" (bidir))
-	(block_io "SRD[15..0]" (bidir))
-	(mapper
-		(pt 408 416)
-		(bidir)
-		)
-	(mapper
-		(pt 408 392)
-		(bidir)
-		)
-	(mapper
-		(pt 408 368)
-		(bidir)
-		)
-	(mapper
-		(pt 408 320)
-		(bidir)
-		)
-	(mapper
-		(pt 408 344)
-		(bidir)
-		)
-	(mapper
-		(pt 408 296)
-		(bidir)
-		)
-	(mapper
-		(pt 408 40)
-		(bidir)
-		)
-	(mapper
-		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 248)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 272)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 408 72)
-		(bidir)
-		)
-	(mapper
-		(pt 408 576)
-		(bidir)
-		)
-	(mapper
-		(pt 0 320)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 408 440)
-		(bidir)
-		)
-)
-(block
-	(rect 1264 2344 1672 2920)
-	(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8)))	(text "nobody" (rect 5 562 41 574)(font "Arial" ))	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "PIC_INT" (input))
-	(block_io "E0_INT" (input))
-	(block_io "DVI_INT" (input))
-	(block_io "nPCI_INTA" (input))
-	(block_io "nPCI_INTB" (input))
-	(block_io "nPCI_INTC" (input))
-	(block_io "nPCI_INTD" (input))
-	(block_io "nMFP_INT" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "DSP_INT" (input))
-	(block_io "VSYNC" (input))
-	(block_io "HSYNC" (input))
-	(block_io "DMA_DRQ" (input))
-	(block_io "nRSTO" (input))
-	(block_io "VIDEO_TA" (input))
-	(block_io "FPGA_DATE[31..0]" (input))
-	(block_io "nIRQ[7..2]" (output))
-	(block_io "INT_HANDLER_TA" (output))
-	(block_io "ACP_CONF[31..0]" (output))
-	(block_io "TIN0" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(mapper
-		(pt 408 56)
-		(bidir)
-		)
-	(mapper
-		(pt 408 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 256)
-		(bidir)
-		)
-	(mapper
-		(pt 0 280)
-		(bidir)
-		)
-	(mapper
-		(pt 0 304)
-		(bidir)
-		)
-	(mapper
-		(pt 0 376)
-		(bidir)
-		)
-	(mapper
-		(pt 0 400)
-		(bidir)
-		)
-	(mapper
-		(pt 0 328)
-		(bidir)
-		)
-	(mapper
-		(pt 0 352)
-		(bidir)
-		)
-	(mapper
-		(pt 0 432)
-		(bidir)
-		)
-	(mapper
-		(pt 0 456)
-		(bidir)
-		)
-	(mapper
-		(pt 0 480)
-		(bidir)
-		)
-	(mapper
-		(pt 0 504)
-		(bidir)
-		)
-	(mapper
-		(pt 408 504)
-		(bidir)
-		)
-	(mapper
-		(pt 0 528)
-		(bidir)
-		)
-	(mapper
-		(pt 408 240)
-		(bidir)
-		)
-	(mapper
-		(pt 408 296)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 32)
-		(bidir)
-		)
-	(mapper
-		(pt 0 552)
-		(bidir)
-		)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 2384 1749 2396)(font "Arial" ))
-	(pt 1832 2400)
-	(pt 1672 2400)
-	(bus)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 8 1749 20)(font "Arial" ))
-	(pt 1832 24)
-	(pt 1672 24)
-	(bus)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1146 328 1221 340)(font "Arial" ))
-	(pt 1112 344)
-	(pt 1264 344)
-	(bus)
-)
-(connector
-	(text "nFB_WR" (rect 1162 184 1206 196)(font "Arial" ))
-	(pt 1152 200)
-	(pt 1264 200)
-)
-(connector
-	(text "nFB_CS1" (rect 1154 208 1201 220)(font "Arial" ))
-	(pt 1152 224)
-	(pt 1264 224)
-)
-(connector
-	(text "FB_SIZE0" (rect 1154 256 1204 268)(font "Arial" ))
-	(pt 1152 272)
-	(pt 1264 272)
-)
-(connector
-	(text "FB_SIZE1" (rect 1154 280 1204 292)(font "Arial" ))
-	(pt 1152 296)
-	(pt 1264 296)
-)
-(connector
-	(text "nFB_CS2" (rect 1162 232 1209 244)(font "Arial" ))
-	(pt 1152 248)
-	(pt 1264 248)
-)
-(connector
-	(text "nBLANK" (rect 1682 184 1723 196)(font "Arial" ))
-	(pt 1672 200)
-	(pt 1832 200)
-)
-(connector
-	(text "nSYNC" (rect 1682 208 1719 220)(font "Arial" ))
-	(pt 1672 224)
-	(pt 1832 224)
-)
-(connector
-	(text "nFB_CS3" (rect 1186 352 1233 364)(font "Arial" ))
-	(pt 1264 368)
-	(pt 1176 368)
-)
-(connector
-	(text "nPD_VGA" (rect 1682 256 1731 268)(font "Arial" ))
-	(pt 1672 272)
-	(pt 1832 272)
-)
-(connector
-	(text "PIC_INT" (rect 1162 2584 1204 2596)(font "Arial" ))
-	(pt 1152 2600)
-	(pt 1264 2600)
-)
-(connector
-	(text "nIRQ[7..2]" (rect 1682 2408 1733 2420)(font "Arial" ))
-	(pt 1672 2424)
-	(pt 1832 2424)
-	(bus)
-)
-(connector
-	(text "nFB_OE" (rect 1170 160 1211 172)(font "Arial" ))
-	(pt 1264 176)
-	(pt 1160 176)
-)
-(connector
-	(text "nPCI_INTA" (rect 1162 2728 1217 2740)(font "Arial" ))
-	(pt 1152 2744)
-	(pt 1264 2744)
-)
-(connector
-	(text "nPCI_INTB" (rect 1162 2704 1217 2716)(font "Arial" ))
-	(pt 1152 2720)
-	(pt 1264 2720)
-)
-(connector
-	(text "nPCI_INTC" (rect 1162 2680 1218 2692)(font "Arial" ))
-	(pt 1152 2696)
-	(pt 1264 2696)
-)
-(connector
-	(text "nPCI_INTD" (rect 1162 2656 1218 2668)(font "Arial" ))
-	(pt 1152 2672)
-	(pt 1264 2672)
-)
-(connector
-	(text "nMFP_INT" (rect 1162 2760 1213 2772)(font "Arial" ))
-	(pt 1152 2776)
-	(pt 1264 2776)
-)
-(connector
-	(text "E0_INT" (rect 1162 2608 1198 2620)(font "Arial" ))
-	(pt 1152 2624)
-	(pt 1264 2624)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 2968 1749 2980)(font "Arial" ))
-	(pt 1832 2984)
-	(pt 1672 2984)
-	(bus)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1146 3224 1221 3236)(font "Arial" ))
-	(pt 1112 3240)
-	(pt 1264 3240)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 1162 3008 1216 3020)(font "Arial" ))
-	(pt 1152 3024)
-	(pt 1264 3024)
-)
-(connector
-	(text "CLK33M" (rect 1210 2984 1251 2996)(font "Arial" ))
-	(pt 1200 3000)
-	(pt 1264 3000)
-)
-(connector
-	(text "nFB_WR" (rect 1170 3056 1214 3068)(font "Arial" ))
-	(pt 1264 3072)
-	(pt 1160 3072)
-)
-(connector
-	(text "nFB_CS1" (rect 1162 3080 1209 3092)(font "Arial" ))
-	(pt 1264 3096)
-	(pt 1160 3096)
-)
-(connector
-	(text "nFB_CS2" (rect 1170 3104 1217 3116)(font "Arial" ))
-	(pt 1264 3120)
-	(pt 1160 3120)
-)
-(connector
-	(text "FB_SIZE0" (rect 1162 3152 1212 3164)(font "Arial" ))
-	(pt 1264 3168)
-	(pt 1160 3168)
-)
-(connector
-	(text "FB_SIZE1" (rect 1162 3176 1212 3188)(font "Arial" ))
-	(pt 1264 3192)
-	(pt 1160 3192)
-)
-(connector
-	(text "nFB_BURST" (rect 1162 3200 1224 3212)(font "Arial" ))
-	(pt 1264 3216)
-	(pt 1160 3216)
-)
-(connector
-	(text "nRSTO" (rect 1170 3248 1205 3260)(font "Arial" ))
-	(pt 1264 3264)
-	(pt 1160 3264)
-)
-(connector
-	(text "nFB_OE" (rect 1170 3032 1211 3044)(font "Arial" ))
-	(pt 1264 3048)
-	(pt 1160 3048)
-)
-(connector
-	(text "DSP_INT" (rect 1130 2832 1176 2844)(font "Arial" ))
-	(pt 1264 2848)
-	(pt 1120 2848)
-)
-(connector
-	(text "DSP_INT" (rect 1682 3000 1728 3012)(font "Arial" ))
-	(pt 1816 3016)
-	(pt 1672 3016)
-)
-(connector
-	(text "CLK500k" (rect 482 2040 526 2052)(font "Arial" ))
-	(pt 472 2056)
-	(pt 544 2056)
-)
-(connector
-	(pt 528 2416)
-	(pt 616 2416)
-)
-(connector
-	(text "FB_ALE" (rect 1194 304 1234 316)(font "Arial" ))
-	(pt 1264 320)
-	(pt 1184 320)
-)
-(connector
-	(text "DDRCLK[3..0]" (rect 1162 136 1233 148)(font "Arial" ))
-	(pt 1152 152)
-	(pt 1264 152)
-	(bus)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 1178 112 1266 124)(font "Arial" ))
-	(pt 1168 128)
-	(pt 1264 128)
-)
-(connector
-	(text "VD[31..0]" (rect 1682 288 1729 300)(font "Arial" ))
-	(pt 1672 304)
-	(pt 2648 304)
-	(bus)
-)
-(connector
-	(text "VA[12..0]" (rect 1682 312 1728 324)(font "Arial" ))
-	(pt 1672 328)
-	(pt 2528 328)
-	(bus)
-)
-(connector
-	(text "nVWE" (rect 1682 336 1712 348)(font "Arial" ))
-	(pt 1672 352)
-	(pt 2400 352)
-)
-(connector
-	(text "nVCAS" (rect 1690 360 1725 372)(font "Arial" ))
-	(pt 1672 376)
-	(pt 2304 376)
-)
-(connector
-	(text "nVRAS" (rect 1690 384 1725 396)(font "Arial" ))
-	(pt 1672 400)
-	(pt 2208 400)
-)
-(connector
-	(text "nVCS" (rect 1690 408 1718 420)(font "Arial" ))
-	(pt 1672 424)
-	(pt 2040 424)
-)
-(connector
-	(text "VCKE" (rect 1690 432 1719 444)(font "Arial" ))
-	(pt 1672 448)
-	(pt 1944 448)
-)
-(connector
-	(text "VSYNC" (rect 1682 136 1720 148)(font "Arial" ))
-	(pt 1672 152)
-	(pt 1832 152)
-)
-(connector
-	(text "HSYNC" (rect 1682 160 1722 172)(font "Arial" ))
-	(pt 1672 176)
-	(pt 1832 176)
-)
-(connector
-	(text "VB[7..0]" (rect 1754 112 1794 124)(font "Arial" ))
-	(pt 1672 128)
-	(pt 1912 128)
-	(bus)
-)
-(connector
-	(text "VG[7..0]" (rect 1842 88 1883 100)(font "Arial" ))
-	(pt 1672 104)
-	(pt 2000 104)
-	(bus)
-)
-(connector
-	(text "VR[7..0]" (rect 1922 64 1963 76)(font "Arial" ))
-	(pt 1672 80)
-	(pt 2080 80)
-	(bus)
-)
-(connector
-	(text "CLK25M" (rect 1202 608 1243 620)(font "Arial" ))
-	(pt 1192 624)
-	(pt 1264 624)
-)
-(connector
-	(text "TIMEBASE[17]" (rect 354 2120 425 2132)(font "Arial" ))
-	(pt 440 2136)
-	(pt 344 2136)
-)
-(connector
-	(text "TIMEBASE[17..0]" (rect 706 2048 790 2060)(font "Arial" ))
-	(pt 688 2064)
-	(pt 808 2064)
-	(bus)
-)
-(connector
-	(text "HSYNC" (rect 1130 2784 1170 2796)(font "Arial" ))
-	(pt 1264 2800)
-	(pt 1120 2800)
-)
-(connector
-	(text "VSYNC" (rect 1130 2808 1168 2820)(font "Arial" ))
-	(pt 1264 2824)
-	(pt 1120 2824)
-)
-(connector
-	(pt 488 2136)
-	(pt 608 2136)
-)
-(connector
-	(text "nFB_TA" (rect 1946 720 1984 732)(font "Arial" ))
-	(pt 1944 736)
-	(pt 2056 736)
-)
-(connector
-	(text "INT_HANDLER_TA" (rect 1682 2832 1777 2844)(font "Arial" ))
-	(pt 1672 2848)
-	(pt 1808 2848)
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-(connector
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-	(pt 1672 3520)
-	(pt 1792 3520)
-)
-(connector
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-	(pt 1672 712)
-	(pt 1880 712)
-)
-(connector
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-	(pt 1880 744)
-	(pt 1800 744)
-)
-(connector
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-	(pt 1880 728)
-	(pt 1800 728)
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-(connector
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-)
-(connector
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-	(pt 2504 888)
-)
-(connector
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-	(pt 2504 760)
-)
-(connector
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-	(pt 2440 760)
-	(pt 2504 760)
-)
-(connector
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-	(pt 2536 760)
-)
-(connector
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-	(pt 1184 104)
-	(pt 1264 104)
-)
-(connector
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-	(pt 1184 56)
-	(pt 1264 56)
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-(connector
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-	(pt 1672 472)
-	(pt 1832 472)
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-(connector
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-	(pt 2384 -48)
-	(pt 2464 -48)
-)
-(connector
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-	(pt 2384 72)
-	(pt 2464 72)
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-(connector
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-	(pt 2464 40)
-	(pt 2384 40)
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-(connector
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-(connector
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-(connector
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-(connector
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-	(pt 1816 -32)
-	(pt 1896 -32)
-)
-(connector
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-	(pt 2136 -64)
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-(connector
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-	(pt 1744 248)
-	(pt 1672 248)
-)
-(connector
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-	(pt 2384 200)
-	(pt 2464 200)
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-(connector
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-	(pt 2456 136)
-)
-(connector
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-	(pt 2456 168)
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-(connector
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-)
-(connector
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-	(pt 2440 184)
-)
-(connector
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-	(pt 2696 168)
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-(connector
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-	(pt 2424 160)
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-(connector
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-	(pt 2440 160)
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-(connector
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-	(pt 1264 3144)
-	(pt 1160 3144)
-)
-(connector
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-	(pt 2136 1768)
-)
-(connector
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-	(pt 2136 1816)
-)
-(connector
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-	(pt 1264 2872)
-	(pt 1120 2872)
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-(connector
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-(connector
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-	(pt 2136 1792)
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-(connector
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-	(pt 2136 1840)
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-(connector
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-	(pt 464 1368)
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-)
-(connector
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-	(pt 608 1392)
-	(pt 760 1392)
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-)
-(connector
-	(text "DDR_SYNC_66M" (rect 378 1368 466 1380)(font "Arial" ))
-	(pt 368 1384)
-	(pt 464 1384)
-)
-(connector
-	(text "FB_ALE" (rect 386 1384 426 1396)(font "Arial" ))
-	(pt 376 1400)
-	(pt 464 1400)
-)
-(connector
-	(text "ACP_CONF[31..0]" (rect 1682 2568 1774 2580)(font "Arial" ))
-	(pt 1672 2584)
-	(pt 1832 2584)
-	(bus)
-)
-(connector
-	(text "TIN0" (rect 1682 2624 1705 2636)(font "Arial" ))
-	(pt 1832 2640)
-	(pt 1672 2640)
-)
-(connector
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-	(pt 1856 -48)
-)
-(connector
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-	(pt 1856 -64)
-)
-(connector
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-	(pt 1896 -64)
-)
-(connector
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-	(pt 2424 -64)
-)
-(connector
-	(pt 2424 -80)
-	(pt 2424 -64)
-)
-(connector
-	(text "DDRCLK[0]" (rect 762 -296 821 -284)(font "Arial" ))
-	(pt 752 -280)
-	(pt 848 -280)
-)
-(connector
-	(text "DDRCLK[1]" (rect 762 -272 821 -260)(font "Arial" ))
-	(pt 752 -256)
-	(pt 848 -256)
-)
-(connector
-	(text "DDRCLK[2]" (rect 762 -248 821 -236)(font "Arial" ))
-	(pt 752 -232)
-	(pt 848 -232)
-)
-(connector
-	(text "DDRCLK[3]" (rect 762 -224 821 -212)(font "Arial" ))
-	(pt 752 -208)
-	(pt 848 -208)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 762 -200 850 -188)(font "Arial" ))
-	(pt 752 -184)
-	(pt 848 -184)
-)
-(connector
-	(pt 408 672)
-	(pt 472 672)
-)
-(connector
-	(text "VIDEO_RECONFIG" (rect 74 496 173 508)(font "Arial" ))
-	(pt 192 512)
-	(pt 64 512)
-)
-(connector
-	(pt 408 640)
-	(pt 472 640)
-)
-(connector
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-	(pt 512 624)
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-(connector
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-	(pt 496 568)
-	(pt 408 568)
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-)
-(connector
-	(text "MAIN_CLK" (rect 122 664 176 676)(font "Arial" ))
-	(pt 112 680)
-	(pt 192 680)
-)
-(connector
-	(pt 536 720)
-	(pt 408 720)
-)
-(connector
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-	(pt 1064 616)
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-(connector
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-	(pt 1072 592)
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-(connector
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-	(pt 472 664)
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-(connector
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-(connector
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-(connector
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-(connector
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-	(pt 1072 592)
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-	(pt 1064 616)
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-	(pt 192 584)
-	(pt 72 584)
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-(connector
-	(pt 1064 808)
-	(pt 80 808)
-)
-(connector
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-(connector
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-(connector
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-(connector
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-	(pt 192 600)
-	(pt 72 600)
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-(connector
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-	(pt 64 528)
-	(pt 192 528)
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-(connector
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-	(pt 64 544)
-	(pt 192 544)
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-(connector
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-	(pt 1144 480)
-	(pt 1264 480)
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-)
-(connector
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-	(pt 2040 544)
-	(pt 1960 544)
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-(connector
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-	(pt 1888 544)
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-)
-(connector
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-	(pt 1888 568)
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-(connector
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-	(pt 1944 568)
-	(pt 1888 568)
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-(connector
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-	(pt 1960 520)
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-(connector
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-	(pt 1960 520)
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-(connector
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-	(pt 1672 576)
-	(pt 1792 576)
-)
-(connector
-	(text "VR_WR" (rect 1698 592 1738 604)(font "Arial" ))
-	(pt 1672 608)
-	(pt 1792 608)
-)
-(connector
-	(text "VR_BUSY" (rect 418 496 469 508)(font "Arial" ))
-	(pt 408 512)
-	(pt 480 512)
-)
-(connector
-	(text "VR_BUSY" (rect 1170 448 1221 460)(font "Arial" ))
-	(pt 1144 464)
-	(pt 1264 464)
-)
-(connector
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-	(pt 1792 592)
-	(pt 1672 592)
-)
-(connector
-	(text "nRSTO" (rect -86 680 -51 692)(font "Arial" ))
-	(pt -96 696)
-	(pt -16 696)
-)
-(connector
-	(pt 32 696)
-	(pt 192 696)
-)
-(connector
-	(text "FB_AD[24..16]" (rect 82 552 155 564)(font "Arial" ))
-	(pt 72 568)
-	(pt 192 568)
-	(bus)
-)
-(connector
-	(text "CLK48M" (rect 538 552 579 564)(font "Arial" ))
-	(pt 528 568)
-	(pt 608 568)
-)
-(connector
-	(text "CLK_VIDEO" (rect 1162 552 1223 564)(font "Arial" ))
-	(pt 984 568)
-	(pt 1264 568)
-)
-(connector
-	(text "CLK33M" (rect 1202 584 1243 596)(font "Arial" ))
-	(pt 1264 600)
-	(pt 1192 600)
-)
-(connector
-	(text "HSYNC" (rect 2314 -96 2354 -84)(font "Arial" ))
-	(pt 2304 -80)
-	(pt 2424 -80)
-)
-(connector
-	(pt 2424 -80)
-	(pt 2464 -80)
-)
-(connector
-	(text "VSYNC" (rect 1746 -80 1784 -68)(font "Arial" ))
-	(pt 1736 -64)
-	(pt 1856 -64)
-)
-(connector
-	(text "DVI_INT" (rect 858 2632 900 2644)(font "Arial" ))
-	(pt 848 2648)
-	(pt 1264 2648)
-)
-(connector
-	(text "MAIN_CLK" (rect 330 -296 384 -284)(font "Arial" ))
-	(pt 264 -280)
-	(pt 400 -280)
-)
-(connector
-	(pt 400 -280)
-	(pt 448 -280)
-)
-(connector
-	(text "CLK33MDIR" (rect 234 296 295 308)(font "Arial" ))
-	(pt 224 312)
-	(pt 288 312)
-)
-(connector
-	(pt 800 160)
-	(pt 400 160)
-)
-(connector
-	(text "CLK33M" (rect 858 144 899 156)(font "Arial" ))
-	(pt 848 160)
-	(pt 952 160)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 776 1749 788)(font "Arial" ))
-	(pt 1832 792)
-	(pt 1672 792)
-	(bus)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1146 1072 1221 1084)(font "Arial" ))
-	(pt 1112 1088)
-	(pt 1264 1088)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 1162 784 1216 796)(font "Arial" ))
-	(pt 1152 800)
-	(pt 1264 800)
-)
-(connector
-	(text "CLK33M" (rect 1210 760 1251 772)(font "Arial" ))
-	(pt 1200 776)
-	(pt 1264 776)
-)
-(connector
-	(text "CLK2M" (rect 1202 808 1237 820)(font "Arial" ))
-	(pt 1192 824)
-	(pt 1264 824)
-)
-(connector
-	(text "CLK500k" (rect 1202 832 1246 844)(font "Arial" ))
-	(pt 1192 848)
-	(pt 1264 848)
-)
-(connector
-	(text "nRSTO" (rect 1170 1120 1205 1132)(font "Arial" ))
-	(pt 1264 1136)
-	(pt 1160 1136)
-)
-(connector
-	(text "CLK2M4576" (rect 1202 856 1261 868)(font "Arial" ))
-	(pt 1192 872)
-	(pt 1264 872)
-)
-(connector
-	(text "nMFP_INT" (rect 1682 2072 1733 2084)(font "Arial" ))
-	(pt 1672 2088)
-	(pt 1784 2088)
-)
-(connector
-	(text "VSYNC" (rect 1130 1920 1168 1932)(font "Arial" ))
-	(pt 1264 1936)
-	(pt 1120 1936)
-)
-(connector
-	(text "HSYNC" (rect 1130 1896 1170 1908)(font "Arial" ))
-	(pt 1264 1912)
-	(pt 1120 1912)
-)
-(connector
-	(text "nBLANK" (rect 1154 1968 1195 1980)(font "Arial" ))
-	(pt 1264 1984)
-	(pt 1144 1984)
-)
-(connector
-	(text "DMA_DRQ" (rect 1682 2096 1736 2108)(font "Arial" ))
-	(pt 1784 2112)
-	(pt 1672 2112)
-)
-(connector
-	(text "FDC_CLK" (rect 1202 880 1252 892)(font "Arial" ))
-	(pt 1192 896)
-	(pt 1264 896)
-)
-(connector
-	(text "FB_ALE" (rect 1186 1992 1226 2004)(font "Arial" ))
-	(pt 1144 2008)
-	(pt 1264 2008)
-)
-(connector
-	(text "nACSI_ACK" (rect 1682 928 1742 940)(font "Arial" ))
-	(pt 1672 944)
-	(pt 1832 944)
-)
-(connector
-	(text "nFB_WR" (rect 1170 928 1214 940)(font "Arial" ))
-	(pt 1160 944)
-	(pt 1264 944)
-)
-(connector
-	(text "nACSI_RESET" (rect 1682 952 1755 964)(font "Arial" ))
-	(pt 1672 968)
-	(pt 1832 968)
-)
-(connector
-	(text "nFB_CS1" (rect 1162 952 1209 964)(font "Arial" ))
-	(pt 1160 968)
-	(pt 1264 968)
-)
-(connector
-	(text "nACSI_CS" (rect 1682 976 1735 988)(font "Arial" ))
-	(pt 1672 992)
-	(pt 1832 992)
-)
-(connector
-	(text "nFB_CS2" (rect 1170 976 1217 988)(font "Arial" ))
-	(pt 1160 992)
-	(pt 1264 992)
-)
-(connector
-	(text "ACSI_DIR" (rect 1682 1000 1733 1012)(font "Arial" ))
-	(pt 1672 1016)
-	(pt 1832 1016)
-)
-(connector
-	(text "FB_SIZE0" (rect 1162 1000 1212 1012)(font "Arial" ))
-	(pt 1160 1016)
-	(pt 1264 1016)
-)
-(connector
-	(text "ACSI_A1" (rect 1682 1024 1726 1036)(font "Arial" ))
-	(pt 1672 1040)
-	(pt 1832 1040)
-)
-(connector
-	(text "FB_SIZE1" (rect 1162 1024 1212 1036)(font "Arial" ))
-	(pt 1160 1040)
-	(pt 1264 1040)
-)
-(connector
-	(text "nFB_BURST" (rect 1162 1048 1224 1060)(font "Arial" ))
-	(pt 1160 1064)
-	(pt 1264 1064)
-)
-(connector
-	(text "SCSI_PAR" (rect 1682 1080 1736 1092)(font "Arial" ))
-	(pt 1672 1096)
-	(pt 1840 1096)
-)
-(connector
-	(text "nDACK0" (rect 1202 1096 1244 1108)(font "Arial" ))
-	(pt 1160 1112)
-	(pt 1264 1112)
-)
-(connector
-	(text "nSCSI_ACK" (rect 1682 1104 1742 1116)(font "Arial" ))
-	(pt 1672 1120)
-	(pt 1840 1120)
-)
-(connector
-	(text "nSCSI_ATN" (rect 1682 1128 1741 1140)(font "Arial" ))
-	(pt 1672 1144)
-	(pt 1840 1144)
-)
-(connector
-	(text "SCSI_DIR" (rect 1682 1152 1733 1164)(font "Arial" ))
-	(pt 1672 1168)
-	(pt 1840 1168)
-)
-(connector
-	(text "LP_BUSY" (rect 1114 1160 1163 1172)(font "Arial" ))
-	(pt 1104 1176)
-	(pt 1264 1176)
-)
-(connector
-	(text "nSCSI_RST" (rect 1682 1176 1741 1188)(font "Arial" ))
-	(pt 1672 1192)
-	(pt 1840 1192)
-)
-(connector
-	(text "nACSI_DRQ" (rect 1034 1192 1096 1204)(font "Arial" ))
-	(pt 1024 1208)
-	(pt 1264 1208)
-)
-(connector
-	(text "nSCSI_SEL" (rect 1680 1200 1737 1212)(font "Arial" ))
-	(pt 1672 1216)
-	(pt 1840 1216)
-)
-(connector
-	(text "nACSI_INT" (rect 1034 1216 1089 1228)(font "Arial" ))
-	(pt 1024 1232)
-	(pt 1264 1232)
-)
-(connector
-	(text "nSCSI_BUSY" (rect 1682 1224 1750 1236)(font "Arial" ))
-	(pt 1672 1240)
-	(pt 1840 1240)
-)
-(connector
-	(text "nSCSI_DRQ" (rect 1114 1248 1176 1260)(font "Arial" ))
-	(pt 1104 1264)
-	(pt 1264 1264)
-)
-(connector
-	(text "nSCSI_C_D" (rect 1114 1272 1174 1284)(font "Arial" ))
-	(pt 1104 1288)
-	(pt 1264 1288)
-)
-(connector
-	(text "nSCSI_I_O" (rect 1114 1296 1169 1308)(font "Arial" ))
-	(pt 1104 1312)
-	(pt 1264 1312)
-)
-(connector
-	(text "TxD" (rect 1682 1312 1702 1324)(font "Arial" ))
-	(pt 1672 1328)
-	(pt 1840 1328)
-)
-(connector
-	(text "nSCSI_MSG" (rect 1114 1320 1175 1332)(font "Arial" ))
-	(pt 1104 1336)
-	(pt 1264 1336)
-)
-(connector
-	(text "RTS" (rect 1682 1336 1703 1348)(font "Arial" ))
-	(pt 1672 1352)
-	(pt 1840 1352)
-)
-(connector
-	(text "DTR" (rect 1680 1360 1702 1372)(font "Arial" ))
-	(pt 1672 1376)
-	(pt 1848 1376)
-)
-(connector
-	(text "RxD" (rect 1114 1384 1136 1396)(font "Arial" ))
-	(pt 1104 1400)
-	(pt 1264 1400)
-)
-(connector
-	(text "AMKB_TX" (rect 1946 1392 1993 1404)(font "Arial" ))
-	(pt 1672 1408)
-	(pt 2112 1408)
-)
-(connector
-	(text "CTS" (rect 1114 1408 1135 1420)(font "Arial" ))
-	(pt 1104 1424)
-	(pt 1264 1424)
-)
-(connector
-	(text "IDE_RES" (rect 1682 1424 1729 1436)(font "Arial" ))
-	(pt 1672 1440)
-	(pt 1848 1440)
-)
-(connector
-	(text "RI" (rect 1114 1432 1125 1444)(font "Arial" ))
-	(pt 1104 1448)
-	(pt 1264 1448)
-)
-(connector
-	(text "nIDE_CS0" (rect 1682 1448 1733 1460)(font "Arial" ))
-	(pt 1672 1464)
-	(pt 1848 1464)
-)
-(connector
-	(text "DCD" (rect 1114 1456 1138 1468)(font "Arial" ))
-	(pt 1104 1472)
-	(pt 1264 1472)
-)
-(connector
-	(text "nIDE_CS1" (rect 1682 1472 1733 1484)(font "Arial" ))
-	(pt 1672 1488)
-	(pt 1856 1488)
-)
-(connector
-	(text "nIDE_WR" (rect 1682 1496 1731 1508)(font "Arial" ))
-	(pt 1672 1512)
-	(pt 1848 1512)
-)
-(connector
-	(text "PIC_AMKB_RX" (rect 786 1504 860 1516)(font "Arial" ))
-	(pt 776 1520)
-	(pt 1264 1520)
-)
-(connector
-	(text "nIDE_RD" (rect 1682 1520 1729 1532)(font "Arial" ))
-	(pt 1672 1536)
-	(pt 1848 1536)
-)
-(connector
-	(text "IDE_RDY" (rect 1114 1536 1163 1548)(font "Arial" ))
-	(pt 1104 1552)
-	(pt 1264 1552)
-)
-(connector
-	(text "nCF_CS0" (rect 1682 1544 1730 1556)(font "Arial" ))
-	(pt 1672 1560)
-	(pt 1848 1560)
-)
-(connector
-	(text "IDE_INT" (rect 1114 1560 1156 1572)(font "Arial" ))
-	(pt 1104 1576)
-	(pt 1264 1576)
-)
-(connector
-	(text "nCF_CS1" (rect 1682 1568 1730 1580)(font "Arial" ))
-	(pt 1672 1584)
-	(pt 1848 1584)
-)
-(connector
-	(text "WP_CF_CARD" (rect 1112 1584 1188 1596)(font "Arial" ))
-	(pt 1104 1600)
-	(pt 1264 1600)
-)
-(connector
-	(text "nROM3" (rect 1754 1600 1790 1612)(font "Arial" ))
-	(pt 1672 1616)
-	(pt 1920 1616)
-)
-(connector
-	(text "nROM4" (rect 1754 1624 1790 1636)(font "Arial" ))
-	(pt 1672 1640)
-	(pt 1920 1640)
-)
-(connector
-	(text "nINDEX" (rect 1050 1640 1088 1652)(font "Arial" ))
-	(pt 1040 1656)
-	(pt 1264 1656)
-)
-(connector
-	(text "nRP_UDS" (rect 1744 1648 1794 1660)(font "Arial" ))
-	(pt 1672 1664)
-	(pt 1920 1664)
-)
-(connector
-	(text "TRACK00" (rect 1050 1664 1098 1676)(font "Arial" ))
-	(pt 1040 1680)
-	(pt 1264 1680)
-)
-(connector
-	(text "nRP_LDS" (rect 1746 1672 1794 1684)(font "Arial" ))
-	(pt 1672 1688)
-	(pt 1920 1688)
-)
-(connector
-	(text "nWP" (rect 1050 1688 1073 1700)(font "Arial" ))
-	(pt 1040 1704)
-	(pt 1264 1704)
-)
-(connector
-	(text "DSA_D" (rect 1682 1704 1718 1716)(font "Arial" ))
-	(pt 1672 1720)
-	(pt 1856 1720)
-)
-(connector
-	(text "nRD_DATA" (rect 1050 1712 1106 1724)(font "Arial" ))
-	(pt 1040 1728)
-	(pt 1264 1728)
-)
-(connector
-	(text "nDCHG" (rect 1050 1736 1088 1748)(font "Arial" ))
-	(pt 1040 1752)
-	(pt 1264 1752)
-)
-(connector
-	(text "SD_DATA0" (rect 1114 1768 1169 1780)(font "Arial" ))
-	(pt 1104 1784)
-	(pt 1264 1784)
-)
-(connector
-	(text "SD_DATA1" (rect 1114 1792 1169 1804)(font "Arial" ))
-	(pt 1104 1808)
-	(pt 1264 1808)
-)
-(connector
-	(text "SD_DATA2" (rect 1114 1816 1169 1828)(font "Arial" ))
-	(pt 1104 1832)
-	(pt 1264 1832)
-)
-(connector
-	(text "WR_GATE" (rect 1690 1824 1743 1836)(font "Arial" ))
-	(pt 1672 1840)
-	(pt 1800 1840)
-)
-(connector
-	(text "SD_CARD_DEDECT" (rect 1138 1840 1241 1852)(font "Arial" ))
-	(pt 1128 1856)
-	(pt 1264 1856)
-)
-(connector
-	(text "nSDSEL" (rect 1682 1848 1723 1860)(font "Arial" ))
-	(pt 1672 1864)
-	(pt 1856 1864)
-)
-(connector
-	(text "SD_WP" (rect 1114 1864 1152 1876)(font "Arial" ))
-	(pt 1104 1880)
-	(pt 1264 1880)
-)
-(connector
-	(text "YM_QA" (rect 1762 1904 1799 1916)(font "Arial" ))
-	(pt 1672 1920)
-	(pt 1928 1920)
-)
-(connector
-	(text "YM_QB" (rect 1762 1928 1799 1940)(font "Arial" ))
-	(pt 1672 1944)
-	(pt 1928 1944)
-)
-(connector
-	(text "YM_QC" (rect 1762 1952 1800 1964)(font "Arial" ))
-	(pt 1672 1968)
-	(pt 1928 1968)
-)
-(connector
-	(text "SD_CD_DATA3" (rect 1682 1984 1759 1996)(font "Arial" ))
-	(pt 1672 2000)
-	(pt 1856 2000)
-)
-(connector
-	(text "SD_CDM_D1" (rect 1682 2008 1748 2020)(font "Arial" ))
-	(pt 1672 2024)
-	(pt 1856 2024)
-)
-(connector
-	(text "SD_CLK" (rect 1682 2032 1724 2044)(font "Arial" ))
-	(pt 1672 2048)
-	(pt 1856 2048)
-)
-(connector
-	(text "nFB_OE" (rect 1170 904 1211 916)(font "Arial" ))
-	(pt 1160 920)
-	(pt 1264 920)
-)
-(connector
-	(text "SCSI_D[7..0]" (rect 1786 1056 1852 1068)(font "Arial" ))
-	(pt 1672 1072)
-	(pt 1936 1072)
-	(bus)
-)
-(connector
-	(text "AMKB_RX" (rect 786 1480 835 1492)(font "Arial" ))
-	(pt 776 1496)
-	(pt 1264 1496)
-)
-(connector
-	(text "FALCON_IO_TA" (rect 1682 744 1763 756)(font "Arial" ))
-	(pt 1672 760)
-	(pt 1880 760)
-)
-(connector
-	(text "STEP_DIR" (rect 1682 1752 1735 1764)(font "Arial" ))
-	(pt 1672 1768)
-	(pt 1856 1768)
-)
-(connector
-	(text "WR_DATA" (rect 1682 1800 1735 1812)(font "Arial" ))
-	(pt 1672 1816)
-	(pt 1856 1816)
-)
-(connector
-	(text "MOT_ON" (rect 1626 1728 1670 1740)(font "Arial" ))
-	(pt 1672 1744)
-	(pt 1800 1744)
-)
-(connector
-	(text "STEP" (rect 1626 1776 1653 1788)(font "Arial" ))
-	(pt 1672 1792)
-	(pt 1800 1792)
-)
-(connector
-	(text "HD_DD" (rect 1050 1616 1088 1628)(font "Arial" ))
-	(pt 1040 1632)
-	(pt 1264 1632)
-)
-(connector
-	(pt 400 248)
-	(pt 440 248)
-)
-(connector
-	(pt 400 160)
-	(pt 400 248)
-)
-(connector
-	(text "nRSTO" (rect 1026 424 1061 436)(font "Arial" ))
-	(pt 1016 440)
-	(pt 1104 440)
-)
-(connector
-	(pt 920 432)
-	(pt 952 432)
-)
-(connector
-	(pt 760 448)
-	(pt 952 448)
-)
-(connector
-	(pt 824 440)
-	(pt 952 440)
-)
-(connector
-	(pt 920 328)
-	(pt 920 432)
-)
-(connector
-	(pt 1888 2192)
-	(pt 1888 2176)
-)
-(connector
-	(pt 1848 2176)
-	(pt 1888 2176)
-)
-(connector
-	(pt 1848 2176)
-	(pt 1848 2208)
-)
-(connector
-	(pt 1848 2208)
-	(pt 1864 2208)
-)
-(connector
-	(text "CLK2M" (rect 1778 2192 1813 2204)(font "Arial" ))
-	(pt 1768 2208)
-	(pt 1848 2208)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1146 2552 1221 2564)(font "Arial" ))
-	(pt 1112 2568)
-	(pt 1264 2568)
-	(bus)
-)
-(connector
-	(text "nFB_WR" (rect 1162 2432 1206 2444)(font "Arial" ))
-	(pt 1152 2448)
-	(pt 1264 2448)
-)
-(connector
-	(text "nFB_CS1" (rect 1154 2456 1201 2468)(font "Arial" ))
-	(pt 1152 2472)
-	(pt 1264 2472)
-)
-(connector
-	(text "FB_SIZE0" (rect 1154 2504 1204 2516)(font "Arial" ))
-	(pt 1152 2520)
-	(pt 1264 2520)
-)
-(connector
-	(text "FB_SIZE1" (rect 1154 2528 1204 2540)(font "Arial" ))
-	(pt 1152 2544)
-	(pt 1264 2544)
-)
-(connector
-	(text "MAIN_CLK" (rect 1162 2384 1216 2396)(font "Arial" ))
-	(pt 1152 2400)
-	(pt 1264 2400)
-)
-(connector
-	(text "nFB_CS2" (rect 1162 2480 1209 2492)(font "Arial" ))
-	(pt 1152 2496)
-	(pt 1264 2496)
-)
-(connector
-	(text "nFB_OE" (rect 1170 2408 1211 2420)(font "Arial" ))
-	(pt 1264 2424)
-	(pt 1160 2424)
-)
-(connector
-	(text "nRSTO" (rect 1170 2360 1205 2372)(font "Arial" ))
-	(pt 1264 2376)
-	(pt 1160 2376)
-)
-(connector
-	(pt 1912 2208)
-	(pt 1960 2208)
-)
-(connector
-	(text "MIDI_IN" (rect 1682 2208 1723 2220)(font "Arial" ))
-	(pt 1672 2224)
-	(pt 1864 2224)
-)
-(connector
-	(text "MIDI_OLR" (rect 1682 2272 1733 2284)(font "Arial" ))
-	(pt 1672 2288)
-	(pt 1920 2288)
-)
-(connector
-	(text "MIDI_TLR" (rect 1682 2232 1731 2244)(font "Arial" ))
-	(pt 1672 2248)
-	(pt 1832 2248)
-)
-(connector
-	(pt 824 440)
-	(pt 824 296)
-)
-(connector
-	(pt 824 296)
-	(pt 712 296)
-)
-(connector
-	(pt 376 -16)
-	(pt 368 -16)
-)
-(connector
-	(pt 400 -16)
-	(pt 464 -16)
-)
-(connector
-	(pt 400 -280)
-	(pt 400 -16)
-)
-(connector
-	(pt 400 -16)
-	(pt 400 160)
-)
-(connector
-	(text "CLK25M" (rect 802 -32 843 -20)(font "Arial" ))
-	(pt 736 -16)
-	(pt 920 -16)
-)
-(connector
-	(text "CLK2M" (rect 810 -8 845 4)(font "Arial" ))
-	(pt 736 0)
-	(pt 808 0)
-)
-(connector
-	(text "CLK500k" (rect 834 8 878 20)(font "Arial" ))
-	(pt 736 16)
-	(pt 832 16)
-)
-(connector
-	(text "CLK2M4576" (rect 810 24 869 36)(font "Arial" ))
-	(pt 736 32)
-	(pt 808 32)
-)
-(connector
-	(text "CLK48M" (rect 722 232 763 244)(font "Arial" ))
-	(pt 712 248)
-	(pt 808 248)
-)
-(connector
-	(text "FDC_CLK" (rect 786 256 836 268)(font "Arial" ))
-	(pt 712 264)
-	(pt 784 264)
-)
-(connector
-	(text "CLK24M576" (rect 722 272 781 284)(font "Arial" ))
-	(pt 816 280)
-	(pt 712 280)
-)
-(connector
-	(text "nFB_CS3" (rect 1162 2136 1209 2148)(font "Arial" ))
-	(pt 1152 2152)
-	(pt 1264 2152)
-)
-(connector
-	(text "nDREQ0" (rect 1722 2120 1765 2132)(font "Arial" ))
-	(pt 1672 2136)
-	(pt 1848 2136)
-)
-(connector
-	(text "Video_TA" (rect 1178 2216 1224 2228)(font "Arial" ))
-	(pt 1168 2232)
-	(pt 1264 2232)
-)
-(connector
-	(text "ACP_CONF[31..0]" (rect 1146 2064 1238 2076)(font "Arial" ))
-	(pt 1136 2080)
-	(pt 1264 2080)
-	(bus)
-)
-(connector
-	(text "BLITTER_INT" (rect 1698 640 1765 652)(font "Arial" ))
-	(pt 1672 656)
-	(pt 1792 656)
-)
-(connector
-	(text "BLITTER_INT" (rect 1154 2168 1221 2180)(font "Arial" ))
-	(pt 1264 2184)
-	(pt 1144 2184)
-)
-(connector
-	(text "DSP_INT" (rect 1154 2192 1200 2204)(font "Arial" ))
-	(pt 1264 2208)
-	(pt 1144 2208)
-)
-(connector
-	(text "FPGA_DATE[31..0]" (rect 938 2880 1033 2892)(font "Arial" ))
-	(pt 928 2896)
-	(pt 1264 2896)
-	(bus)
-)
-(connector
-	(pt 920 328)
-	(pt 1080 328)
-)
-(connector
-	(pt 1080 328)
-	(pt 1080 48)
-)
-(connector
-	(pt 736 48)
-	(pt 1080 48)
-)
-(connector
-	(text "ACSI_D[7..0]" (rect 1754 880 1820 892)(font "Arial" ))
-	(pt 1672 896)
-	(pt 1904 896)
-	(bus)
-)
-(connector
-	(text "IO[17..0]" (rect 2178 3224 2221 3236)(font "Arial" ))
-	(pt 1672 3240)
-	(pt 2320 3240)
-	(bus)
-)
-(connector
-	(text "nSRWE" (rect 1682 3344 1720 3356)(font "Arial" ))
-	(pt 1672 3360)
-	(pt 1816 3360)
-)
-(connector
-	(text "nSRBHE" (rect 1682 3320 1725 3332)(font "Arial" ))
-	(pt 1672 3336)
-	(pt 1904 3336)
-)
-(connector
-	(text "nSRBLE" (rect 1682 3296 1723 3308)(font "Arial" ))
-	(pt 1672 3312)
-	(pt 1992 3312)
-)
-(connector
-	(text "nSRCS" (rect 1682 3272 1718 3284)(font "Arial" ))
-	(pt 1672 3288)
-	(pt 2112 3288)
-)
-(connector
-	(text "SRD[15..0]" (rect 2074 3248 2129 3260)(font "Arial" ))
-	(pt 1672 3264)
-	(pt 2216 3264)
-	(bus)
-)
-(connector
-	(text "LP_D[7..0]" (rect 2154 800 2207 812)(font "Arial" ))
-	(pt 1672 816)
-	(pt 2304 816)
-	(bus)
-)
-(connector
-	(text "LP_STR" (rect 2042 824 2082 836)(font "Arial" ))
-	(pt 1672 840)
-	(pt 2192 840)
-)
-(connector
-	(text "LP_DIR" (rect 1922 848 1960 860)(font "Arial" ))
-	(pt 1672 864)
-	(pt 2072 864)
-)
-(connector
-	(text "nSROE" (rect 1682 3368 1718 3380)(font "Arial" ))
-	(pt 1672 3384)
-	(pt 1768 3384)
-)
-(junction (pt 2504 760))
-(junction (pt 1856 -64))
-(junction (pt 2424 -80))
-(junction (pt 400 -280))
-(junction (pt 400 160))
-(junction (pt 1848 2208))
-(junction (pt 400 -16))
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.4"))
+(properties
+	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
+)
+(pin
+	(input)
+	(rect 208 1392 376 1408)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "FB_ALE" (rect 9 0 51 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 160 1408 208 1424))
+)
+(pin
+	(input)
+	(rect 992 936 1160 952)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nFB_WR" (rect 9 0 55 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 952 992 968))
+)
+(pin
+	(input)
+	(rect 992 960 1160 976)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 9 0 57 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 976 992 992))
+)
+(pin
+	(input)
+	(rect 992 984 1160 1000)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS2" (rect 9 0 58 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1000 992 1016))
+)
+(pin
+	(input)
+	(rect 1008 360 1176 376)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS3" (rect 9 0 58 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 960 376 1008 392))
+)
+(pin
+	(input)
+	(rect 992 1008 1160 1024)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE0" (rect 9 0 60 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1024 992 1040))
+)
+(pin
+	(input)
+	(rect 992 1032 1160 1048)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE1" (rect 9 0 59 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1048 992 1064))
+)
+(pin
+	(input)
+	(rect 992 1056 1160 1072)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nFB_BURST" (rect 9 0 73 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1072 992 1088))
+)
+(pin
+	(input)
+	(rect 936 1168 1104 1184)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "LP_BUSY" (rect 9 0 60 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1184 936 1200))
+)
+(pin
+	(input)
+	(rect 856 1200 1024 1216)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nACSI_DRQ" (rect 9 0 72 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 808 1216 856 1232))
+)
+(pin
+	(input)
+	(rect 856 1224 1024 1240)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "nACSI_INT" (rect 9 0 66 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 808 1240 856 1256))
+)
+(pin
+	(input)
+	(rect 936 1392 1104 1408)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "RxD" (rect 9 0 32 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1408 936 1424))
+)
+(pin
+	(input)
+	(rect 936 1416 1104 1432)
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "CTS" (rect 9 0 32 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
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+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 128)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 416)
+		(bidir)
+		)
+	(mapper
+		(pt 408 320)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
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+	(mapper
+		(pt 0 368)
+		(bidir)
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+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 568)
+		(bidir)
+		)
+	(mapper
+		(pt 408 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 648)
+		(bidir)
+		)
+	(mapper
+		(pt 0 672)
+		(bidir)
+		)
+	(mapper
+		(pt 0 616)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 656)
+		(bidir)
+		)
+	(mapper
+		(pt 408 640)
+		(bidir)
+		)
+	(mapper
+		(pt 408 624)
+		(bidir)
+		)
+	(mapper
+		(pt 0 512)
+		(bidir)
+		)
+	(mapper
+		(pt 408 704)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 744 1672 2312)
+	(text "FalconIO_SDCard_IDE_CF" (rect 5 5 160 18)(font "Arial" (font_size 8)))	(text "Wolfgang_Foerster_and_Fredi_Aschwanden" (rect 5 1554 224 1565)(font "Arial" ))	(block_io "CLK33M" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "CLK2M" (input))
+	(block_io "CLK500k" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "LP_BUSY" (input))
+	(block_io "nACSI_DRQ" (input))
+	(block_io "nACSI_INT" (input))
+	(block_io "nSCSI_DRQ" (input))
+	(block_io "nSCSI_MSG" (input))
+	(block_io "MIDI_IN" (input))
+	(block_io "RxD" (input))
+	(block_io "CTS" (input))
+	(block_io "RI" (input))
+	(block_io "DCD" (input))
+	(block_io "AMKB_RX" (input))
+	(block_io "PIC_AMKB_RX" (input))
+	(block_io "IDE_RDY" (input))
+	(block_io "IDE_INT" (input))
+	(block_io "WP_CS_CARD" (input))
+	(block_io "nINDEX" (input))
+	(block_io "TRACK00" (input))
+	(block_io "nRD_DATA" (input))
+	(block_io "nDCHG" (input))
+	(block_io "SD_DATA0" (input))
+	(block_io "SD_DATA1" (input))
+	(block_io "SD_DATA2" (input))
+	(block_io "SD_CARD_DEDECT" (input))
+	(block_io "SD_WP" (input))
+	(block_io "nDACK0" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "WP_CF_CARD" (input))
+	(block_io "nWP" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nSCSI_C_D" (input))
+	(block_io "nSCSI_I_O" (input))
+	(block_io "CLK2M4576" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "nBLANK" (input))
+	(block_io "FDC_CLK" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "HD_DD" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "VIDEO_TA" (input))
+	(block_io "ACP_CONF[31..0]" (input))
+	(block_io "BLITTER_INT" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "nIDE_CS1" (output))
+	(block_io "nIDE_CS0" (output))
+	(block_io "LP_STR" (output))
+	(block_io "LP_DIR" (output))
+	(block_io "nACSI_ACK" (output))
+	(block_io "nACSI_RESET" (output))
+	(block_io "nACSI_CS" (output))
+	(block_io "ACSI_DIR" (output))
+	(block_io "ACSI_A1" (output))
+	(block_io "nSCSI_ACK" (output))
+	(block_io "nSCSI_ATN" (output))
+	(block_io "SCSI_DIR" (output))
+	(block_io "SD_CLK" (output))
+	(block_io "YM_QA" (output))
+	(block_io "YM_QC" (output))
+	(block_io "YM_QB" (output))
+	(block_io "nSDSEL" (output))
+	(block_io "STEP" (output))
+	(block_io "MOT_ON" (output))
+	(block_io "nRP_LDS" (output))
+	(block_io "nRP_UDS" (output))
+	(block_io "nROM4" (output))
+	(block_io "nROM3" (output))
+	(block_io "nCF_CS1" (output))
+	(block_io "nCF_CS0" (output))
+	(block_io "nIDE_RD" (output))
+	(block_io "nIDE_WR" (output))
+	(block_io "AMKB_TX" (output))
+	(block_io "IDE_RES" (output))
+	(block_io "DTR" (output))
+	(block_io "RTS" (output))
+	(block_io "TxD" (output))
+	(block_io "MIDI_OLR" (output))
+	(block_io "nDREQ0" (output))
+	(block_io "DSA_D" (output))
+	(block_io "nMFP_INT" (output))
+	(block_io "FALCON_IO_TA" (output))
+	(block_io "STEP_DIR" (output))
+	(block_io "WR_DATA" (output))
+	(block_io "WR_GATE" (output))
+	(block_io "DMA_DRQ" (output))
+	(block_io "MIDI_TLR" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "LP_D[7..0]" (bidir))
+	(block_io "ACSI_D[7..0]" (bidir))
+	(block_io "SCSI_D[7..0]" (bidir))
+	(block_io "SCSI_PAR" (bidir))
+	(block_io "nSCSI_SEL" (bidir))
+	(block_io "nSCSI_BUSY" (bidir))
+	(block_io "nSCSI_RST" (bidir))
+	(block_io "SD_CD_DATA3" (bidir))
+	(block_io "SD_CDM_D1" (bidir))
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(pt 0 80)
+		(bidir)
+		)
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+		(bidir)
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+		)
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 408 120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 352)
+		(bidir)
+		)
+	(mapper
+		(pt 408 328)
+		(bidir)
+		)
+	(mapper
+		(pt 408 448)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 608)
+		(bidir)
+		)
+	(mapper
+		(pt 408 632)
+		(bidir)
+		)
+	(mapper
+		(pt 408 584)
+		(bidir)
+		)
+	(mapper
+		(pt 0 656)
+		(bidir)
+		)
+	(mapper
+		(pt 0 680)
+		(bidir)
+		)
+	(mapper
+		(pt 0 704)
+		(bidir)
+		)
+	(mapper
+		(pt 0 728)
+		(bidir)
+		)
+	(mapper
+		(pt 0 752)
+		(bidir)
+		)
+	(mapper
+		(pt 0 776)
+		(bidir)
+		)
+	(mapper
+		(pt 408 664)
+		(bidir)
+		)
+	(mapper
+		(pt 0 808)
+		(bidir)
+		)
+	(mapper
+		(pt 0 832)
+		(bidir)
+		)
+	(mapper
+		(pt 408 696)
+		(bidir)
+		)
+	(mapper
+		(pt 408 720)
+		(bidir)
+		)
+	(mapper
+		(pt 408 744)
+		(bidir)
+		)
+	(mapper
+		(pt 408 768)
+		(bidir)
+		)
+	(mapper
+		(pt 408 792)
+		(bidir)
+		)
+	(mapper
+		(pt 408 816)
+		(bidir)
+		)
+	(mapper
+		(pt 408 840)
+		(bidir)
+		)
+	(mapper
+		(pt 0 856)
+		(bidir)
+		)
+	(mapper
+		(pt 408 872)
+		(bidir)
+		)
+	(mapper
+		(pt 408 896)
+		(bidir)
+		)
+	(mapper
+		(pt 408 920)
+		(bidir)
+		)
+	(mapper
+		(pt 408 944)
+		(bidir)
+		)
+	(mapper
+		(pt 0 912)
+		(bidir)
+		)
+	(mapper
+		(pt 0 936)
+		(bidir)
+		)
+	(mapper
+		(pt 0 960)
+		(bidir)
+		)
+	(mapper
+		(pt 0 984)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1008)
+		(bidir)
+		)
+	(mapper
+		(pt 408 976)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1000)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1072)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1096)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1040)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1064)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1088)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1112)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1136)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 464)
+		(bidir)
+		)
+	(mapper
+		(pt 0 488)
+		(bidir)
+		)
+	(mapper
+		(pt 0 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 544)
+		(bidir)
+		)
+	(mapper
+		(pt 0 568)
+		(bidir)
+		)
+	(mapper
+		(pt 0 592)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1168)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1192)
+		(bidir)
+		)
+	(mapper
+		(pt 0 368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 48)
+		(bidir)
+		)
+	(mapper
+		(pt 408 16)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1304)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1280)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1048)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1024)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
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+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1264)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1336)
+		(bidir)
+		)
+	(mapper
+		(pt 0 888)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1480)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1392)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1544)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1408)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1488)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1440)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1464)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 2944 1672 3560)
+	(text "DSP" (rect 5 5 32 18)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 74 613)(font "Arial" ))	(block_io "CLK33M" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nSRCS" (output))
+	(block_io "nSRBLE" (output))
+	(block_io "nSRBHE" (output))
+	(block_io "nSRWE" (output))
+	(block_io "nSROE" (output))
+	(block_io "DSP_INT" (output))
+	(block_io "DSP_TA" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "IO[17..0]" (bidir))
+	(block_io "SRD[15..0]" (bidir))
+	(mapper
+		(pt 408 416)
+		(bidir)
+		)
+	(mapper
+		(pt 408 392)
+		(bidir)
+		)
+	(mapper
+		(pt 408 368)
+		(bidir)
+		)
+	(mapper
+		(pt 408 320)
+		(bidir)
+		)
+	(mapper
+		(pt 408 344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 40)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 408 576)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 440)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 2344 1672 2920)
+	(text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8)))	(text "nobody" (rect 5 562 42 573)(font "Arial" ))	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "PIC_INT" (input))
+	(block_io "E0_INT" (input))
+	(block_io "DVI_INT" (input))
+	(block_io "nPCI_INTA" (input))
+	(block_io "nPCI_INTB" (input))
+	(block_io "nPCI_INTC" (input))
+	(block_io "nPCI_INTD" (input))
+	(block_io "nMFP_INT" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DMA_DRQ" (input))
+	(block_io "nRSTO" (input))
+	(block_io "VIDEO_TA" (input))
+	(block_io "FPGA_DATE[31..0]" (input))
+	(block_io "nIRQ[7..2]" (output))
+	(block_io "INT_HANDLER_TA" (output))
+	(block_io "ACP_CONF[31..0]" (output))
+	(block_io "TIN0" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 408 56)
+		(bidir)
+		)
+	(mapper
+		(pt 408 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 280)
+		(bidir)
+		)
+	(mapper
+		(pt 0 304)
+		(bidir)
+		)
+	(mapper
+		(pt 0 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 400)
+		(bidir)
+		)
+	(mapper
+		(pt 0 328)
+		(bidir)
+		)
+	(mapper
+		(pt 0 352)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 0 480)
+		(bidir)
+		)
+	(mapper
+		(pt 0 504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 504)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 552)
+		(bidir)
+		)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 2384 1748 2395)(font "Arial" ))
+	(pt 1832 2400)
+	(pt 1672 2400)
+	(bus)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 8 1748 19)(font "Arial" ))
+	(pt 1832 24)
+	(pt 1672 24)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 328 1220 339)(font "Arial" ))
+	(pt 1112 344)
+	(pt 1264 344)
+	(bus)
+)
+(connector
+	(text "nFB_WR" (rect 1162 184 1208 195)(font "Arial" ))
+	(pt 1152 200)
+	(pt 1264 200)
+)
+(connector
+	(text "nFB_CS1" (rect 1154 208 1202 219)(font "Arial" ))
+	(pt 1152 224)
+	(pt 1264 224)
+)
+(connector
+	(text "FB_SIZE0" (rect 1154 256 1205 267)(font "Arial" ))
+	(pt 1152 272)
+	(pt 1264 272)
+)
+(connector
+	(text "FB_SIZE1" (rect 1154 280 1204 291)(font "Arial" ))
+	(pt 1152 296)
+	(pt 1264 296)
+)
+(connector
+	(text "nFB_CS2" (rect 1162 232 1211 243)(font "Arial" ))
+	(pt 1152 248)
+	(pt 1264 248)
+)
+(connector
+	(text "nBLANK" (rect 1682 184 1726 195)(font "Arial" ))
+	(pt 1672 200)
+	(pt 1832 200)
+)
+(connector
+	(text "nSYNC" (rect 1682 208 1720 219)(font "Arial" ))
+	(pt 1672 224)
+	(pt 1832 224)
+)
+(connector
+	(text "nFB_CS3" (rect 1186 352 1235 363)(font "Arial" ))
+	(pt 1264 368)
+	(pt 1176 368)
+)
+(connector
+	(text "nPD_VGA" (rect 1682 256 1736 267)(font "Arial" ))
+	(pt 1672 272)
+	(pt 1832 272)
+)
+(connector
+	(text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" ))
+	(pt 1152 2600)
+	(pt 1264 2600)
+)
+(connector
+	(text "nIRQ[7..2]" (rect 1682 2408 1732 2419)(font "Arial" ))
+	(pt 1672 2424)
+	(pt 1832 2424)
+	(bus)
+)
+(connector
+	(text "nFB_OE" (rect 1170 160 1213 171)(font "Arial" ))
+	(pt 1264 176)
+	(pt 1160 176)
+)
+(connector
+	(text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" ))
+	(pt 1152 2744)
+	(pt 1264 2744)
+)
+(connector
+	(text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" ))
+	(pt 1152 2720)
+	(pt 1264 2720)
+)
+(connector
+	(text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" ))
+	(pt 1152 2696)
+	(pt 1264 2696)
+)
+(connector
+	(text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" ))
+	(pt 1152 2672)
+	(pt 1264 2672)
+)
+(connector
+	(text "nMFP_INT" (rect 1162 2760 1217 2771)(font "Arial" ))
+	(pt 1152 2776)
+	(pt 1264 2776)
+)
+(connector
+	(text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" ))
+	(pt 1152 2624)
+	(pt 1264 2624)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" ))
+	(pt 1832 2984)
+	(pt 1672 2984)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" ))
+	(pt 1112 3240)
+	(pt 1264 3240)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" ))
+	(pt 1152 3024)
+	(pt 1264 3024)
+)
+(connector
+	(text "CLK33M" (rect 1210 2984 1254 2995)(font "Arial" ))
+	(pt 1200 3000)
+	(pt 1264 3000)
+)
+(connector
+	(text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" ))
+	(pt 1264 3072)
+	(pt 1160 3072)
+)
+(connector
+	(text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" ))
+	(pt 1264 3096)
+	(pt 1160 3096)
+)
+(connector
+	(text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" ))
+	(pt 1264 3120)
+	(pt 1160 3120)
+)
+(connector
+	(text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" ))
+	(pt 1264 3168)
+	(pt 1160 3168)
+)
+(connector
+	(text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" ))
+	(pt 1264 3192)
+	(pt 1160 3192)
+)
+(connector
+	(text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" ))
+	(pt 1264 3216)
+	(pt 1160 3216)
+)
+(connector
+	(text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" ))
+	(pt 1264 3264)
+	(pt 1160 3264)
+)
+(connector
+	(text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" ))
+	(pt 1264 3048)
+	(pt 1160 3048)
+)
+(connector
+	(text "DSP_INT" (rect 1130 2832 1178 2843)(font "Arial" ))
+	(pt 1264 2848)
+	(pt 1120 2848)
+)
+(connector
+	(text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" ))
+	(pt 1816 3016)
+	(pt 1672 3016)
+)
+(connector
+	(text "CLK500k" (rect 482 2040 529 2051)(font "Arial" ))
+	(pt 472 2056)
+	(pt 544 2056)
+)
+(connector
+	(pt 528 2416)
+	(pt 616 2416)
+)
+(connector
+	(text "FB_ALE" (rect 1194 304 1236 315)(font "Arial" ))
+	(pt 1264 320)
+	(pt 1184 320)
+)
+(connector
+	(text "DDRCLK[3..0]" (rect 1162 136 1232 147)(font "Arial" ))
+	(pt 1152 152)
+	(pt 1264 152)
+	(bus)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 1178 112 1267 123)(font "Arial" ))
+	(pt 1168 128)
+	(pt 1264 128)
+)
+(connector
+	(text "VD[31..0]" (rect 1682 288 1728 299)(font "Arial" ))
+	(pt 1672 304)
+	(pt 2648 304)
+	(bus)
+)
+(connector
+	(text "VA[12..0]" (rect 1682 312 1728 323)(font "Arial" ))
+	(pt 1672 328)
+	(pt 2528 328)
+	(bus)
+)
+(connector
+	(text "nVWE" (rect 1682 336 1715 347)(font "Arial" ))
+	(pt 1672 352)
+	(pt 2400 352)
+)
+(connector
+	(text "nVCAS" (rect 1690 360 1727 371)(font "Arial" ))
+	(pt 1672 376)
+	(pt 2304 376)
+)
+(connector
+	(text "nVRAS" (rect 1690 384 1727 395)(font "Arial" ))
+	(pt 1672 400)
+	(pt 2208 400)
+)
+(connector
+	(text "nVCS" (rect 1690 408 1720 419)(font "Arial" ))
+	(pt 1672 424)
+	(pt 2040 424)
+)
+(connector
+	(text "VCKE" (rect 1690 432 1721 443)(font "Arial" ))
+	(pt 1672 448)
+	(pt 1944 448)
+)
+(connector
+	(text "VSYNC" (rect 1682 136 1722 147)(font "Arial" ))
+	(pt 1672 152)
+	(pt 1832 152)
+)
+(connector
+	(text "HSYNC" (rect 1682 160 1722 171)(font "Arial" ))
+	(pt 1672 176)
+	(pt 1832 176)
+)
+(connector
+	(text "VB[7..0]" (rect 1754 112 1794 123)(font "Arial" ))
+	(pt 1672 128)
+	(pt 1912 128)
+	(bus)
+)
+(connector
+	(text "VG[7..0]" (rect 1842 88 1883 99)(font "Arial" ))
+	(pt 1672 104)
+	(pt 2000 104)
+	(bus)
+)
+(connector
+	(text "VR[7..0]" (rect 1922 64 1962 75)(font "Arial" ))
+	(pt 1672 80)
+	(pt 2080 80)
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+)
+(connector
+	(text "CLK25M" (rect 1202 608 1246 619)(font "Arial" ))
+	(pt 1192 624)
+	(pt 1264 624)
+)
+(connector
+	(text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" ))
+	(pt 440 2136)
+	(pt 344 2136)
+)
+(connector
+	(text "TIMEBASE[17..0]" (rect 706 2048 792 2059)(font "Arial" ))
+	(pt 688 2064)
+	(pt 808 2064)
+	(bus)
+)
+(connector
+	(text "HSYNC" (rect 1130 2784 1170 2795)(font "Arial" ))
+	(pt 1264 2800)
+	(pt 1120 2800)
+)
+(connector
+	(text "VSYNC" (rect 1130 2808 1170 2819)(font "Arial" ))
+	(pt 1264 2824)
+	(pt 1120 2824)
+)
+(connector
+	(pt 488 2136)
+	(pt 608 2136)
+)
+(connector
+	(text "nFB_TA" (rect 1946 720 1989 731)(font "Arial" ))
+	(pt 1944 736)
+	(pt 2056 736)
+)
+(connector
+	(text "INT_HANDLER_TA" (rect 1682 2832 1781 2843)(font "Arial" ))
+	(pt 1672 2848)
+	(pt 1808 2848)
+)
+(connector
+	(text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" ))
+	(pt 1672 3520)
+	(pt 1792 3520)
+)
+(connector
+	(text "Video_TA" (rect 1682 696 1732 707)(font "Arial" ))
+	(pt 1672 712)
+	(pt 1880 712)
+)
+(connector
+	(text "INT_HANDLER_TA" (rect 1810 728 1909 739)(font "Arial" ))
+	(pt 1880 744)
+	(pt 1800 744)
+)
+(connector
+	(text "DSP_TA" (rect 1810 712 1856 723)(font "Arial" ))
+	(pt 1880 728)
+	(pt 1800 728)
+)
+(connector
+	(pt 2680 888)
+	(pt 2712 888)
+)
+(connector
+	(pt 2632 888)
+	(pt 2504 888)
+)
+(connector
+	(pt 2504 888)
+	(pt 2504 760)
+)
+(connector
+	(text "DDRCLK[0]" (rect 2450 744 2507 755)(font "Arial" ))
+	(pt 2440 760)
+	(pt 2504 760)
+)
+(connector
+	(pt 2504 760)
+	(pt 2536 760)
+)
+(connector
+	(text "MAIN_CLK" (rect 1186 88 1243 99)(font "Arial" ))
+	(pt 1184 104)
+	(pt 1264 104)
+)
+(connector
+	(text "nRSTO" (rect 1194 40 1232 51)(font "Arial" ))
+	(pt 1184 56)
+	(pt 1264 56)
+)
+(connector
+	(text "BA[1..0]" (rect 1682 456 1722 467)(font "Arial" ))
+	(pt 1672 472)
+	(pt 1832 472)
+	(bus)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" ))
+	(pt 2384 -48)
+	(pt 2464 -48)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 56 2455 67)(font "Arial" ))
+	(pt 2384 72)
+	(pt 2464 72)
+)
+(connector
+	(text "nBLANK" (rect 2394 24 2438 35)(font "Arial" ))
+	(pt 2464 40)
+	(pt 2384 40)
+)
+(connector
+	(text "nBLANK" (rect 2394 40 2438 51)(font "Arial" ))
+	(pt 2464 56)
+	(pt 2384 56)
+)
+(connector
+	(pt 2696 -80)
+	(pt 2712 -80)
+)
+(connector
+	(pt 2696 40)
+	(pt 2712 40)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1826 -48 1887 -37)(font "Arial" ))
+	(pt 1816 -32)
+	(pt 1896 -32)
+)
+(connector
+	(pt 2128 -64)
+	(pt 2136 -64)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1682 232 1743 243)(font "Arial" ))
+	(pt 1744 248)
+	(pt 1672 248)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" ))
+	(pt 2384 200)
+	(pt 2464 200)
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+(connector
+	(pt 2456 168)
+	(pt 2456 136)
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+(connector
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+	(pt 2440 184)
+	(pt 2440 160)
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+	(text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" ))
+	(pt 1264 3144)
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+)
+(connector
+	(pt 1904 1768)
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+(connector
+	(pt 1904 1816)
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+(connector
+	(text "DMA_DRQ" (rect 1130 2856 1186 2867)(font "Arial" ))
+	(pt 1264 2872)
+	(pt 1120 2872)
+)
+(connector
+	(pt 1848 1744)
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+(connector
+	(pt 1848 1792)
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+(connector
+	(pt 1848 1840)
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+(connector
+	(text "FB_AD[31..0]" (rect 370 1352 436 1363)(font "Arial" ))
+	(pt 352 1368)
+	(pt 464 1368)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 642 1376 716 1387)(font "Arial" ))
+	(pt 608 1392)
+	(pt 760 1392)
+	(bus)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 378 1368 467 1379)(font "Arial" ))
+	(pt 368 1384)
+	(pt 464 1384)
+)
+(connector
+	(text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" ))
+	(pt 376 1400)
+	(pt 464 1400)
+)
+(connector
+	(text "ACP_CONF[31..0]" (rect 1682 2568 1772 2579)(font "Arial" ))
+	(pt 1672 2584)
+	(pt 1832 2584)
+	(bus)
+)
+(connector
+	(text "TIN0" (rect 1682 2624 1707 2635)(font "Arial" ))
+	(pt 1832 2640)
+	(pt 1672 2640)
+)
+(connector
+	(pt 1896 -48)
+	(pt 1856 -48)
+)
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+	(pt 1856 -48)
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+(connector
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+	(pt 2424 -80)
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+)
+(connector
+	(text "DDRCLK[0]" (rect 762 -296 819 -285)(font "Arial" ))
+	(pt 752 -280)
+	(pt 848 -280)
+)
+(connector
+	(text "DDRCLK[1]" (rect 762 -272 819 -261)(font "Arial" ))
+	(pt 752 -256)
+	(pt 848 -256)
+)
+(connector
+	(text "DDRCLK[2]" (rect 762 -248 819 -237)(font "Arial" ))
+	(pt 752 -232)
+	(pt 848 -232)
+)
+(connector
+	(text "DDRCLK[3]" (rect 762 -224 819 -213)(font "Arial" ))
+	(pt 752 -208)
+	(pt 848 -208)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 762 -200 851 -189)(font "Arial" ))
+	(pt 752 -184)
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+)
+(connector
+	(pt 408 672)
+	(pt 472 672)
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+	(text "VIDEO_RECONFIG" (rect 74 496 174 507)(font "Arial" ))
+	(pt 192 512)
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+)
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+	(pt 408 640)
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+)
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+	(pt 408 624)
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+	(text "VR_D[8..0]" (rect 418 552 472 563)(font "Arial" ))
+	(pt 496 568)
+	(pt 408 568)
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+)
+(connector
+	(text "MAIN_CLK" (rect 122 664 179 675)(font "Arial" ))
+	(pt 112 680)
+	(pt 192 680)
+)
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+	(pt 536 720)
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+	(text "FB_ADR[8..6]" (rect 82 584 150 595)(font "Arial" ))
+	(pt 192 600)
+	(pt 72 600)
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+)
+(connector
+	(text "VR_RD" (rect 98 512 136 523)(font "Arial" ))
+	(pt 64 528)
+	(pt 192 528)
+)
+(connector
+	(text "VR_WR" (rect 98 528 139 539)(font "Arial" ))
+	(pt 64 544)
+	(pt 192 544)
+)
+(connector
+	(text "VR_D[8..0]" (rect 1170 464 1224 475)(font "Arial" ))
+	(pt 1144 480)
+	(pt 1264 480)
+	(bus)
+)
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+	(text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" ))
+	(pt 2040 544)
+	(pt 1960 544)
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+	(pt 1672 544)
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+	(pt 1888 544)
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+	(text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" ))
+	(pt 1944 568)
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+	(pt 1672 520)
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+	(pt 1960 544)
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+	(text "VIDEO_RECONFIG" (rect 1674 560 1774 571)(font "Arial" ))
+	(pt 1672 576)
+	(pt 1792 576)
+)
+(connector
+	(text "VR_WR" (rect 1698 592 1739 603)(font "Arial" ))
+	(pt 1672 608)
+	(pt 1792 608)
+)
+(connector
+	(text "VR_BUSY" (rect 418 496 472 507)(font "Arial" ))
+	(pt 408 512)
+	(pt 480 512)
+)
+(connector
+	(text "VR_BUSY" (rect 1170 448 1224 459)(font "Arial" ))
+	(pt 1144 464)
+	(pt 1264 464)
+)
+(connector
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+(connector
+	(pt 736 48)
+	(pt 1080 48)
+)
+(connector
+	(text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" ))
+	(pt 1672 896)
+	(pt 1904 896)
+	(bus)
+)
+(connector
+	(text "IO[17..0]" (rect 2178 3224 2220 3235)(font "Arial" ))
+	(pt 1672 3240)
+	(pt 2320 3240)
+	(bus)
+)
+(connector
+	(text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" ))
+	(pt 1672 3360)
+	(pt 1816 3360)
+)
+(connector
+	(text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" ))
+	(pt 1672 3336)
+	(pt 1904 3336)
+)
+(connector
+	(text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" ))
+	(pt 1672 3312)
+	(pt 1992 3312)
+)
+(connector
+	(text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" ))
+	(pt 1672 3288)
+	(pt 2112 3288)
+)
+(connector
+	(text "SRD[15..0]" (rect 2074 3248 2128 3259)(font "Arial" ))
+	(pt 1672 3264)
+	(pt 2216 3264)
+	(bus)
+)
+(connector
+	(text "LP_D[7..0]" (rect 2154 800 2207 811)(font "Arial" ))
+	(pt 1672 816)
+	(pt 2304 816)
+	(bus)
+)
+(connector
+	(text "LP_STR" (rect 2042 824 2085 835)(font "Arial" ))
+	(pt 1672 840)
+	(pt 2192 840)
+)
+(connector
+	(text "LP_DIR" (rect 1922 848 1962 859)(font "Arial" ))
+	(pt 1672 864)
+	(pt 2072 864)
+)
+(connector
+	(text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" ))
+	(pt 1672 3384)
+	(pt 1768 3384)
+)
+(connector
+	(text "FPGA_DATE[31..0]" (rect 938 2880 1034 2891)(font "Arial" ))
+	(pt 928 2896)
+	(pt 1264 2896)
+	(bus)
+)
+(junction (pt 2504 760))
+(junction (pt 1856 -64))
+(junction (pt 2424 -80))
+(junction (pt 400 -280))
+(junction (pt 400 160))
+(junction (pt 1848 2208))
+(junction (pt 400 -16))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index 33428b5..7ffeb7f 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Wed Aug 28 16:04:24 2019
+Sun Jul 11 19:34:46 2021
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index 98e45e8..8edd04d 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -1,828 +1,844 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-# Date created = 12:45:00  November 06, 2010
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		firebee1_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 8.1
-set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_G2 -to MAIN_CLK
-set_location_assignment PIN_Y3 -to FB_AD[0]
-set_location_assignment PIN_Y6 -to FB_AD[1]
-set_location_assignment PIN_AA3 -to FB_AD[2]
-set_location_assignment PIN_AB3 -to FB_AD[3]
-set_location_assignment PIN_W6 -to FB_AD[4]
-set_location_assignment PIN_V7 -to FB_AD[5]
-set_location_assignment PIN_AA4 -to FB_AD[6]
-set_location_assignment PIN_AB4 -to FB_AD[7]
-set_location_assignment PIN_AA5 -to FB_AD[8]
-set_location_assignment PIN_AB5 -to FB_AD[9]
-set_location_assignment PIN_W7 -to FB_AD[10]
-set_location_assignment PIN_Y7 -to FB_AD[11]
-set_location_assignment PIN_U9 -to FB_AD[12]
-set_location_assignment PIN_V8 -to FB_AD[13]
-set_location_assignment PIN_W8 -to FB_AD[14]
-set_location_assignment PIN_AA7 -to FB_AD[15]
-set_location_assignment PIN_AB7 -to FB_AD[16]
-set_location_assignment PIN_Y8 -to FB_AD[17]
-set_location_assignment PIN_V9 -to FB_AD[18]
-set_location_assignment PIN_V10 -to FB_AD[19]
-set_location_assignment PIN_T10 -to FB_AD[20]
-set_location_assignment PIN_U10 -to FB_AD[21]
-set_location_assignment PIN_AA8 -to FB_AD[22]
-set_location_assignment PIN_AB8 -to FB_AD[23]
-set_location_assignment PIN_T11 -to FB_AD[24]
-set_location_assignment PIN_AA9 -to FB_AD[25]
-set_location_assignment PIN_AB9 -to FB_AD[26]
-set_location_assignment PIN_U11 -to FB_AD[27]
-set_location_assignment PIN_V11 -to FB_AD[28]
-set_location_assignment PIN_W10 -to FB_AD[29]
-set_location_assignment PIN_Y10 -to FB_AD[30]
-set_location_assignment PIN_AA10 -to FB_AD[31]
-set_location_assignment PIN_R7 -to FB_ALE
-set_location_assignment PIN_N19 -to LED_FPGA_OK
-set_location_assignment PIN_AB10 -to CLK24M576
-set_location_assignment PIN_J1 -to CLKUSB
-set_location_assignment PIN_T4 -to CLK25M
-set_location_assignment PIN_U8 -to FB_SIZE0
-set_location_assignment PIN_Y4 -to FB_SIZE1
-set_location_assignment PIN_T3 -to nFB_BURST
-set_location_assignment PIN_T8 -to nFB_CS1
-set_location_assignment PIN_T9 -to nFB_CS2
-set_location_assignment PIN_V6 -to nFB_CS3
-set_location_assignment PIN_R6 -to nFB_OE
-set_location_assignment PIN_T5 -to nFB_WR
-set_location_assignment PIN_R5 -to TIN0
-set_location_assignment PIN_T21 -to nMASTER
-set_location_assignment PIN_E11 -to nDREQ1
-set_location_assignment PIN_A12 -to nDACK1
-set_location_assignment PIN_B12 -to nDACK0
-set_location_assignment PIN_T22 -to TOUT0
-set_location_assignment PIN_AB17 -to DDR_CLK
-set_location_assignment PIN_AA17 -to nDDR_CLK
-set_location_assignment PIN_AB18 -to nVCAS
-set_location_assignment PIN_T18 -to nVCS
-set_location_assignment PIN_W17 -to nVRAS
-set_location_assignment PIN_Y17 -to nVWE
-set_location_assignment PIN_W20 -to VA[0]
-set_location_assignment PIN_W22 -to VA[1]
-set_location_assignment PIN_W21 -to VA[2]
-set_location_assignment PIN_Y22 -to VA[3]
-set_location_assignment PIN_AA22 -to VA[4]
-set_location_assignment PIN_Y21 -to VA[5]
-set_location_assignment PIN_AA21 -to VA[6]
-set_location_assignment PIN_AA20 -to VA[7]
-set_location_assignment PIN_AB20 -to VA[8]
-set_location_assignment PIN_AB19 -to VA[9]
-set_location_assignment PIN_V21 -to VA[10]
-set_location_assignment PIN_U19 -to VA[11]
-set_location_assignment PIN_AA18 -to VA[12]
-set_location_assignment PIN_U15 -to VCKE
-set_location_assignment PIN_M22 -to VD[0]
-set_location_assignment PIN_M21 -to VD[1]
-set_location_assignment PIN_P22 -to VD[2]
-set_location_assignment PIN_R20 -to VD[3]
-set_location_assignment PIN_P21 -to VD[4]
-set_location_assignment PIN_R17 -to VD[5]
-set_location_assignment PIN_R19 -to VD[6]
-set_location_assignment PIN_U21 -to VD[7]
-set_location_assignment PIN_V22 -to VD[8]
-set_location_assignment PIN_R18 -to VD[9]
-set_location_assignment PIN_P17 -to VD[10]
-set_location_assignment PIN_R21 -to VD[11]
-set_location_assignment PIN_N17 -to VD[12]
-set_location_assignment PIN_P20 -to VD[13]
-set_location_assignment PIN_R22 -to VD[14]
-set_location_assignment PIN_N20 -to VD[15]
-set_location_assignment PIN_T12 -to VD[16]
-set_location_assignment PIN_Y13 -to VD[17]
-set_location_assignment PIN_AA13 -to VD[18]
-set_location_assignment PIN_V14 -to VD[19]
-set_location_assignment PIN_U13 -to VD[20]
-set_location_assignment PIN_V15 -to VD[21]
-set_location_assignment PIN_W14 -to VD[22]
-set_location_assignment PIN_AB16 -to VD[23]
-set_location_assignment PIN_AB15 -to VD[24]
-set_location_assignment PIN_AA14 -to VD[25]
-set_location_assignment PIN_AB14 -to VD[26]
-set_location_assignment PIN_V13 -to VD[27]
-set_location_assignment PIN_W13 -to VD[28]
-set_location_assignment PIN_AB13 -to VD[29]
-set_location_assignment PIN_V12 -to VD[30]
-set_location_assignment PIN_U12 -to VD[31]
-set_location_assignment PIN_AA16 -to VDM[0]
-set_location_assignment PIN_V16 -to VDM[1]
-set_location_assignment PIN_U20 -to VDM[2]
-set_location_assignment PIN_T17 -to VDM[3]
-set_location_assignment PIN_AA15 -to VDQS[0]
-set_location_assignment PIN_W15 -to VDQS[1]
-set_location_assignment PIN_U22 -to VDQS[2]
-set_location_assignment PIN_T16 -to VDQS[3]
-set_location_assignment PIN_V1 -to nPD_VGA
-set_location_assignment PIN_G18 -to VB[0]
-set_location_assignment PIN_H17 -to VB[1]
-set_location_assignment PIN_C22 -to VB[2]
-set_location_assignment PIN_C21 -to VB[3]
-set_location_assignment PIN_B22 -to VB[4]
-set_location_assignment PIN_B21 -to VB[5]
-set_location_assignment PIN_C20 -to VB[6]
-set_location_assignment PIN_D20 -to VB[7]
-set_location_assignment PIN_H19 -to VG[0]
-set_location_assignment PIN_E22 -to VG[1]
-set_location_assignment PIN_E21 -to VG[2]
-set_location_assignment PIN_H18 -to VG[3]
-set_location_assignment PIN_J17 -to VG[4]
-set_location_assignment PIN_H16 -to VG[5]
-set_location_assignment PIN_D22 -to VG[6]
-set_location_assignment PIN_D21 -to VG[7]
-set_location_assignment PIN_J22 -to VR[0]
-set_location_assignment PIN_J21 -to VR[1]
-set_location_assignment PIN_H22 -to VR[2]
-set_location_assignment PIN_H21 -to VR[3]
-set_location_assignment PIN_K17 -to VR[4]
-set_location_assignment PIN_K18 -to VR[5]
-set_location_assignment PIN_J18 -to VR[6]
-set_location_assignment PIN_F22 -to VR[7]
-set_location_assignment PIN_M6 -to ACSI_A1
-set_location_assignment PIN_B1 -to ACSI_D[0]
-set_location_assignment PIN_G5 -to ACSI_D[1]
-set_location_assignment PIN_E3 -to ACSI_D[2]
-set_location_assignment PIN_C2 -to ACSI_D[3]
-set_location_assignment PIN_C1 -to ACSI_D[4]
-set_location_assignment PIN_D2 -to ACSI_D[5]
-set_location_assignment PIN_H7 -to ACSI_D[6]
-set_location_assignment PIN_H6 -to ACSI_D[7]
-set_location_assignment PIN_L6 -to ACSI_DIR
-set_location_assignment PIN_N1 -to AMKB_TX
-set_location_assignment PIN_F15 -to DSA_D
-set_location_assignment PIN_D15 -to DTR
-set_location_assignment PIN_A11 -to DVI_INT
-set_location_assignment PIN_G21 -to E0_INT
-set_location_assignment PIN_M5 -to IDE_RES
-set_location_assignment PIN_A8 -to IO[0]
-set_location_assignment PIN_A7 -to IO[1]
-set_location_assignment PIN_B7 -to IO[2]
-set_location_assignment PIN_A6 -to IO[3]
-set_location_assignment PIN_B6 -to IO[4]
-set_location_assignment PIN_E9 -to IO[5]
-set_location_assignment PIN_C8 -to IO[6]
-set_location_assignment PIN_C7 -to IO[7]
-set_location_assignment PIN_G10 -to IO[8]
-set_location_assignment PIN_A15 -to IO[9]
-set_location_assignment PIN_B15 -to IO[10]
-set_location_assignment PIN_C13 -to IO[11]
-set_location_assignment PIN_D13 -to IO[12]
-set_location_assignment PIN_E13 -to IO[13]
-set_location_assignment PIN_A14 -to IO[14]
-set_location_assignment PIN_B14 -to IO[15]
-set_location_assignment PIN_A13 -to IO[16]
-set_location_assignment PIN_B13 -to IO[17]
-set_location_assignment PIN_F7 -to LP_D[0]
-set_location_assignment PIN_C4 -to LP_D[1]
-set_location_assignment PIN_C3 -to LP_D[2]
-set_location_assignment PIN_E7 -to LP_D[3]
-set_location_assignment PIN_D6 -to LP_D[4]
-set_location_assignment PIN_B3 -to LP_D[5]
-set_location_assignment PIN_A3 -to LP_D[6]
-set_location_assignment PIN_G8 -to LP_D[7]
-set_location_assignment PIN_E6 -to LP_STR
-set_location_assignment PIN_H5 -to MIDI_OLR
-set_location_assignment PIN_B2 -to MIDI_TLR
-set_location_assignment PIN_M4 -to nACSI_ACK
-set_location_assignment PIN_M2 -to nACSI_CS
-set_location_assignment PIN_M1 -to nACSI_RESET
-set_location_assignment PIN_W2 -to nCF_CS0
-set_location_assignment PIN_W1 -to nCF_CS1
-set_location_assignment PIN_T7 -to nFB_TA
-set_location_assignment PIN_R2 -to nIDE_CS0
-set_location_assignment PIN_R1 -to nIDE_CS1
-set_location_assignment PIN_P1 -to nIDE_RD
-set_location_assignment PIN_P2 -to nIDE_WR
-set_location_assignment PIN_F21 -to nIRQ[2]
-set_location_assignment PIN_H20 -to nIRQ[3]
-set_location_assignment PIN_F20 -to nIRQ[4]
-set_location_assignment PIN_P5 -to nIRQ[5]
-set_location_assignment PIN_P7 -to nIRQ[6]
-set_location_assignment PIN_N7 -to nIRQ[7]
-set_location_assignment PIN_AA1 -to nPCI_INTA
-set_location_assignment PIN_V4 -to nPCI_INTB
-set_location_assignment PIN_V3 -to nPCI_INTC
-set_location_assignment PIN_P6 -to nPCI_INTD
-set_location_assignment PIN_P3 -to nROM3
-set_location_assignment PIN_U2 -to nROM4
-set_location_assignment PIN_N5 -to nRP_LDS
-set_location_assignment PIN_P4 -to nRP_UDS
-set_location_assignment PIN_N2 -to nSCSI_ACK
-set_location_assignment PIN_M3 -to nSCSI_ATN
-set_location_assignment PIN_N8 -to nSCSI_BUSY
-set_location_assignment PIN_N6 -to nSCSI_RST
-set_location_assignment PIN_M8 -to nSCSI_SEL
-set_location_assignment PIN_B20 -to nSDSEL
-set_location_assignment PIN_B4 -to nSRBHE
-set_location_assignment PIN_A4 -to nSRBLE
-set_location_assignment PIN_B8 -to nSRCS
-set_location_assignment PIN_F11 -to nSROE
-set_location_assignment PIN_F8 -to nSRWE
-set_location_assignment PIN_G14 -to nWR
-set_location_assignment PIN_D17 -to nWR_GATE
-set_location_assignment PIN_AA2 -to PIC_INT
-set_location_assignment PIN_B18 -to RTS
-set_location_assignment PIN_J6 -to SCSI_D[0]
-set_location_assignment PIN_E1 -to SCSI_D[1]
-set_location_assignment PIN_F2 -to SCSI_D[2]
-set_location_assignment PIN_F1 -to SCSI_D[3]
-set_location_assignment PIN_G4 -to SCSI_D[4]
-set_location_assignment PIN_G3 -to SCSI_D[5]
-set_location_assignment PIN_L8 -to SCSI_D[6]
-set_location_assignment PIN_K8 -to SCSI_D[7]
-set_location_assignment PIN_J7 -to SCSI_DIR
-set_location_assignment PIN_M7 -to SCSI_PAR
-set_location_assignment PIN_F13 -to SD_CD_DATA3
-set_location_assignment PIN_C15 -to SD_CLK
-set_location_assignment PIN_E14 -to SD_CMD_D1
-set_location_assignment PIN_B5 -to SRD[0]
-set_location_assignment PIN_A5 -to SRD[1]
-set_location_assignment PIN_C6 -to SRD[2]
-set_location_assignment PIN_G11 -to SRD[3]
-set_location_assignment PIN_C10 -to SRD[4]
-set_location_assignment PIN_F9 -to SRD[5]
-set_location_assignment PIN_E10 -to SRD[6]
-set_location_assignment PIN_H11 -to SRD[7]
-set_location_assignment PIN_B9 -to SRD[8]
-set_location_assignment PIN_A10 -to SRD[9]
-set_location_assignment PIN_A9 -to SRD[10]
-set_location_assignment PIN_B10 -to SRD[11]
-set_location_assignment PIN_D10 -to SRD[12]
-set_location_assignment PIN_F10 -to SRD[13]
-set_location_assignment PIN_G9 -to SRD[14]
-set_location_assignment PIN_H10 -to SRD[15]
-set_location_assignment PIN_A18 -to TxD
-set_location_assignment PIN_A17 -to YM_QA
-set_location_assignment PIN_G13 -to YM_QB
-set_location_assignment PIN_E15 -to YM_QC
-set_location_assignment PIN_T1 -to WP_CF_CARD
-set_location_assignment PIN_C19 -to TRACK00
-set_location_assignment PIN_M19 -to SD_WP
-set_location_assignment PIN_B17 -to SD_DATA2
-set_location_assignment PIN_A16 -to SD_DATA1
-set_location_assignment PIN_B16 -to SD_DATA0
-set_location_assignment PIN_M20 -to SD_CARD_DEDECT
-set_location_assignment PIN_H15 -to RxD
-set_location_assignment PIN_B19 -to RI
-set_location_assignment PIN_L7 -to PIC_AMKB_RX
-set_location_assignment PIN_D19 -to nWP
-set_location_assignment PIN_H2 -to nSCSI_MSG
-set_location_assignment PIN_J3 -to nSCSI_I_O
-set_location_assignment PIN_U1 -to nSCSI_DRQ
-set_location_assignment PIN_H1 -to nSCSI_C_D
-set_location_assignment PIN_A20 -to nRD_DATA
-set_location_assignment PIN_C17 -to nDCHG
-set_location_assignment PIN_J4 -to nACSI_INT
-set_location_assignment PIN_K7 -to nACSI_DRQ
-set_location_assignment PIN_G7 -to LP_BUSY
-set_location_assignment PIN_Y1 -to IDE_RDY
-set_location_assignment PIN_G22 -to IDE_INT
-set_location_assignment PIN_F16 -to HD_DD
-set_location_assignment PIN_A19 -to DCD
-set_location_assignment PIN_H14 -to CTS
-set_location_assignment PIN_Y2 -to AMKB_RX
-set_location_assignment PIN_E16 -to nINDEX
-set_location_assignment PIN_W19 -to BA[0]
-set_location_assignment PIN_AA19 -to BA[1]
-set_location_assignment PIN_K21 -to HSYNC_PAD
-set_location_assignment PIN_K19 -to VSYNC_PAD
-set_location_assignment PIN_G17 -to nBLANK_PAD
-set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
-set_location_assignment PIN_F17 -to nSYNC
-set_location_assignment PIN_G15 -to nSTEP_DIR
-set_location_assignment PIN_F14 -to nSTEP
-set_location_assignment PIN_G16 -to nMOT_ON
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name TPD_REQUIREMENT "1 ns"
-set_global_assignment -name TSU_REQUIREMENT "1 ns"
-set_global_assignment -name TCO_REQUIREMENT "1 ns"
-set_global_assignment -name TH_REQUIREMENT "1 ns"
-set_global_assignment -name FMAX_REQUIREMENT "33 MHz"
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY firebee1
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SAFE_STATE_MACHINE OFF
-set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP3C40F484C6
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name FITTER_EFFORT "AUTO FIT"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
-set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
-set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_TTF_FILE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name GENERATE_HEX_FILE OFF
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name END_TIME "2 us"
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
-set_global_assignment -name SETUP_HOLD_DETECTION OFF
-set_global_assignment -name GLITCH_DETECTION OFF
-set_global_assignment -name CHECK_OUTPUTS OFF
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
-
-# start EDA_TOOL_SETTINGS(eda_blast_fpga)
-# ---------------------------------------
-
-	# Analysis & Synthesis Assignments
-	# ================================
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
-
-# end EDA_TOOL_SETTINGS(eda_blast_fpga)
-# -------------------------------------
-
-# start CLOCK(fast)
-# -----------------
-
-	# Classic Timing Assignments
-	# ==========================
-set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
-
-# end CLOCK(fast)
-# ---------------
-
-# start ASSIGNMENT_GROUP(fast)
-# ----------------------------
-
-	# Assignment Group Assignments
-	# ============================
-
-# end ASSIGNMENT_GROUP(fast)
-# --------------------------
-
-# ----------------------
-# start ENTITY(firebee1)
-
-	# Classic Timing Assignments
-	# ==========================
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
-set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
-set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
-
-	# Fitter Assignments
-	# ==================
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
-
-	# Simulator Assignments
-	# =====================
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
-
-	# start LOGICLOCK_REGION(Root Region)
-	# -----------------------------------
-
-		# LogicLock Region Assignments
-		# ============================
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-
-	# end LOGICLOCK_REGION(Root Region)
-	# ---------------------------------
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(firebee1)
-# --------------------
-set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
-set_location_assignment PIN_E5 -to LPDIR
-set_location_assignment PIN_B11 -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
-set_location_assignment PIN_AB12 -to CLK33MDIR
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_location_assignment PIN_E12 -to MIDI_IN_PIN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
-set_instance_assignment -name PCI_IO ON -to nPCI_INTA
-set_instance_assignment -name PCI_IO ON -to nPCI_INTB
-set_instance_assignment -name PCI_IO ON -to nPCI_INTC
-set_instance_assignment -name PCI_IO ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
-set_location_assignment PIN_V2 -to nDREQ0
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name SLEW_RATE 0 -to LP_D
-set_instance_assignment -name SLEW_RATE 0 -to LP_STR
-set_instance_assignment -name SLEW_RATE 0 -to LPDIR
-set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_ror128.cmp
-set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_ror128.tdf
-set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
-set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
-set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
-set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
-set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
-set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
-set_global_assignment -name VHDL_FILE lpm_latch0.vhd
-set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
-set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
-set_global_assignment -name QIP_FILE altpll2.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
-set_global_assignment -name QIP_FILE altpll3.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
-set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
-set_global_assignment -name SOURCE_FILE altpll0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
-set_global_assignment -name SOURCE_FILE altpll2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
-set_global_assignment -name VHDL_FILE altpll2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
-set_global_assignment -name SOURCE_FILE altpll3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
-set_global_assignment -name VHDL_FILE altpll3.vhd
-set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
-set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
-set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
-set_global_assignment -name BDF_FILE Video/Video.bdf
-set_global_assignment -name VHDL_FILE altpll1.vhd
-set_global_assignment -name SOURCE_FILE altpll1.cmp
-set_global_assignment -name BDF_FILE firebee1.bdf
-set_global_assignment -name QIP_FILE altpll0.qip
-set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name VHDL_FILE "FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd"
-set_global_assignment -name VHDL_FILE "DSP/DSP.vhd"
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE Video/altdpram0.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
-set_global_assignment -name QIP_FILE Video/altdpram1.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
-set_global_assignment -name QIP_FILE Video/altdpram2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
-set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
-set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name AHDL_FILE "Interrupt_Handler/interrupt_handler.tdf"
-set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
-set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
-set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
-set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
-set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
-set_global_assignment -name QIP_FILE Video/altddio_out0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
-set_global_assignment -name QIP_FILE Video/altddio_out1.qip
-set_global_assignment -name QIP_FILE Video/altddio_out2.qip
-set_global_assignment -name QIP_FILE altddio_out3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
-set_global_assignment -name QIP_FILE altpll_reconfig1.qip
-set_global_assignment -name QIP_FILE altpll4.qip
-set_global_assignment -name QIP_FILE lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
-set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE lpm_counter1.qip
-set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
-set_global_assignment -name QIP_FILE lpm_mux1.qip
-set_global_assignment -name QIP_FILE Video/lpm_blitter.qip
-set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift384.tdf
-set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
-set_global_assignment -name QIP_FILE FPGA_DATE.qip
-set_global_assignment -name QIP_FILE Video/Doppelzeilen_Fifo.qip
-set_global_assignment -name QIP_FILE Video/shiftreg_dpz.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_ror128.qip
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
-set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
-set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 12:45:00  November 06, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		firebee1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:precmd.tcl"
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz"
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY firebee1
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+
+# start EDA_TOOL_SETTINGS(eda_blast_fpga)
+# ---------------------------------------
+
+	# Analysis & Synthesis Assignments
+	# ================================
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+
+# end EDA_TOOL_SETTINGS(eda_blast_fpga)
+# -------------------------------------
+
+# start CLOCK(fast)
+# -----------------
+
+	# Classic Timing Assignments
+	# ==========================
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+
+# end CLOCK(fast)
+# ---------------
+
+# start ASSIGNMENT_GROUP(fast)
+# ----------------------------
+
+	# Assignment Group Assignments
+	# ============================
+
+# end ASSIGNMENT_GROUP(fast)
+# --------------------------
+
+# ----------------------
+# start ENTITY(firebee1)
+
+	# Classic Timing Assignments
+	# ==========================
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+
+	# Fitter Assignments
+	# ==================
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+
+	# Simulator Assignments
+	# =====================
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+
+	# start LOGICLOCK_REGION(Root Region)
+	# -----------------------------------
+
+		# LogicLock Region Assignments
+		# ============================
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+	# end LOGICLOCK_REGION(Root Region)
+	# ---------------------------------
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(firebee1)
+# --------------------
+set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_location_assignment PIN_V2 -to nDREQ0
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name SLEW_RATE 0 -to LP_D
+set_instance_assignment -name SLEW_RATE 0 -to LP_STR
+set_instance_assignment -name SLEW_RATE 0 -to LPDIR
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
+set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
+set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
+set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION OFF
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to MAIN_CLK
+set_location_assignment PLL_1 -to "altpll3:inst13|altpll:altpll_component|altpll_9j03:auto_generated|pll1"
+set_location_assignment PLL_3 -to "altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1"
+set_location_assignment PLL_2 -to "altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1"
+
+set_location_assignment PLL_4 -to "altpll1:inst|altpll:altpll_component|altpll_hsp2:auto_generated|pll1"
+
+set_global_assignment -name SDC_FILE firebee1.sdc
+set_global_assignment -name VHDL_FILE compile_date.vhd
+set_global_assignment -name VHDL_FILE datetime.vhd
+set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_ror128.cmp
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_ror128.tdf
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
+set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
+set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
+set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name BDF_FILE Video/Video.bdf
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name BDF_FILE firebee1.bdf
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name QIP_FILE altpll_reconfig1.qip
+set_global_assignment -name QIP_FILE altpll4.qip
+set_global_assignment -name QIP_FILE lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
+set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE lpm_counter1.qip
+set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
+set_global_assignment -name QIP_FILE lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_blitter.qip
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift384.tdf
+set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
+set_global_assignment -name QIP_FILE FPGA_DATE.qip
+set_global_assignment -name QIP_FILE Video/Doppelzeilen_Fifo.qip
+set_global_assignment -name QIP_FILE Video/shiftreg_dpz.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_ror128.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.sdc b/FPGA_by_Fredi/firebee1.sdc
new file mode 100644
index 0000000..dc4fd4b
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.sdc
@@ -0,0 +1,155 @@
+## Generated SDC file "D:/Download/firebee1.out.sdc"
+
+## Copyright (C) 1991-2010 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition"
+
+## DATE    "Tue Jun 02 13:09:12 2020"
+
+##
+## DEVICE  "EP3C40F484C6"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+
+create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
+
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[0]} -phase 240  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[1]} -phase 0    -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[2]} -phase 180  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[2]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[3]} -phase 105  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[3]]
+#create_generated_clock  -multiply_by 2                    -name {CLK_DDR[4]} -phase 270  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[4]]
+
+#create_generated_clock  -multiply_by 16   -divide_by 11   -name {CLK_48M}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 16   -divide_by 33   -name {CLK_FDC}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 32   -divide_by 43   -name {CLK_24M}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[2]]
+
+#create_generated_clock  -multiply_by 25   -divide_by 33   -name {CLK_25M}              -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 2    -divide_by 33   -name {CLK_2M}               -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 1    -divide_by 66   -name {CLK_500k}             -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[2]]
+#create_generated_clock  -multiply_by 25   -divide_by 336  -name {CLK_2M4}              -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[3]]
+
+#create_generated_clock  -multiply_by 2                    -name {CLK_PIXEL}            -source [get_pins inst|altpll_component|auto_generated|pll1|clk[0]] [get_pins inst22|altpll_component|auto_generated|pll1|clk[0]]
+
+# see if Quartus finds even more clocks
+
+derive_pll_clocks -use_net_name
+derive_clocks -period 30.303
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -clock {MAIN_CLK} -max 4 [remove_from_collection [all_inputs] [get_ports {MAIN_CLK}]]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_keepers *0hh1*d_wrptr*] -to [get_keepers *0hh1*dffe13a*]
+set_false_path -from [get_keepers *0hh1*rdptr_g\[*] -to [get_keepers *0hh1*dffe18*]
+set_false_path -from [get_keepers *3fh1*d_wrptr*] -to [get_keepers *3fh1*dffe13a*]
+set_false_path -from [get_keepers *3fh1*rdptr_g\[*] -to [get_keepers *3fh1*15\|dffe16a\[*]
+
+set_false_path -from MAIN_CLK -to altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]
+
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
+#set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
+#set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_te9:dffpipe20|dffe21a*}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+# TPD
+set_max_delay -from [all_inputs] -to [all_outputs] 1 
+
+# TSU
+set_max_delay -from [all_inputs] -to [all_registers] 1
+
+# TCO
+set_max_delay -from [all_registers] -to [all_outputs] 1 
+
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers BA*] 5
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers VA*] 5
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers nVRA*] 5
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/FPGA_by_Fredi/make_datetime.tcl b/FPGA_by_Fredi/make_datetime.tcl
new file mode 100644
index 0000000..e9a5c6c
--- /dev/null
+++ b/FPGA_by_Fredi/make_datetime.tcl
@@ -0,0 +1,36 @@
+puts make_datetime.tcl
+
+# Make datetime.vhd package from Tcl script
+
+# Current date, time, and seconds since epoch
+# Array index                                            0  1  2  3  4  5  6
+set datetime_arr [clock format [clock seconds] -format {%Y %m %d %H %M %S %s}]
+
+# Write VHDL package
+set filename datetime.vhd
+set file [open $filename w]
+puts $file "library ieee;"
+puts $file "use ieee.std_logic_1164.all;"
+puts $file ""
+puts $file "package datetime is"
+puts $file "    -- Date information"
+puts $file "    constant YEAR_INT       : integer                        := [lindex $datetime_arr 0];"
+puts $file "    constant YEAR_HEX       : std_ulogic_vector(15 downto 0) := X\"[lindex $datetime_arr 0]\";"
+puts $file "    constant MONTH_INT      : integer                        := [lindex $datetime_arr 1];"
+puts $file "    constant MONTH_HEX      : std_ulogic_vector(7 downto 0)  := X\"[lindex $datetime_arr 1]\";"
+puts $file "    constant DAY_INT        : integer                        := [lindex $datetime_arr 2];"
+puts $file "    constant DAY_HEX        : std_ulogic_vector(7 downto 0)  := X\"[lindex $datetime_arr 2]\";"
+puts $file "    constant DATE_HEX_DMY   : std_ulogic_vector(31 downto 0) := DAY_HEX & MONTH_HEX & YEAR_HEX;"
+puts $file "    constant DATE_HEX_YMD   : std_ulogic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;"
+puts $file "    -- Time information"
+puts $file "    constant HOUR_INT       : integer                       := [lindex $datetime_arr 3];"
+puts $file "    constant HOUR_HEX       : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 3]\";"
+puts $file "    constant MINUTE_INT     : integer                       := [lindex $datetime_arr 4];"
+puts $file "    constant MINUTE_HEX     : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 4]\";"
+puts $file "    constant SECOND_INT     : integer                       := [lindex $datetime_arr 5];"
+puts $file "    constant SECOND_HEX     : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 5]\";"
+puts $file "    constant TIME_HEX       : std_ulogic_vector(31 downto 0):= X\"00\" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;"
+puts $file "    -- Miscellaneous information"
+puts $file "    constant EPOCH_INT      : integer := [lindex $datetime_arr 6];  -- Seconds since 1970-01-01_00:00:00"
+puts $file "end package;"
+close $file
diff --git a/FPGA_by_Fredi/precmd.tcl b/FPGA_by_Fredi/precmd.tcl
new file mode 100644
index 0000000..dae5694
--- /dev/null
+++ b/FPGA_by_Fredi/precmd.tcl
@@ -0,0 +1,13 @@
+#
+# execute each of a list of tcl scripts
+#
+# meant to be used with the PRE_FLOW_SCRIPT_FILE quartus assignment
+# that allows to evaluate a tcl script before analysis starts
+
+set precmd_list { "make_datetime.tcl" }
+
+set script [info script]
+foreach item $precmd_list {
+    post_message "$script: execute $item"
+    exec quartus_sh -t $item
+}