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fix ACP web address

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This commit is contained in:
Markus Fröschle
2015-11-18 06:41:49 +00:00
parent fc8034d93b
commit 5c933580a2
19 changed files with 883 additions and 883 deletions
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114
FPGA_Quartus_13.1/altpll1.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 272 184) (rect 0 0 272 176)
(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10))) (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" )) (text "inst" (rect 8 161 26 172)(font "Arial" ))
(port (port
(pt 0 64) (pt 0 64)
(input) (input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1)) (line (pt 0 64)(pt 40 64))
) )
(port (port
(pt 272 64) (pt 272 64)
(output) (output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8))) (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
) )
(port (port
(pt 272 80) (pt 272 80)
(output) (output)
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8))) (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
) )
(port (port
(pt 272 96) (pt 272 96)
(output) (output)
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8))) (text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
) )
(port (port
(pt 272 112) (pt 272 112)
(output) (output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8))) (text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
) )
(drawing (drawing
(text "Cyclone III" (rect 211 169 258 181)(font "Arial" )) (text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" )) (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" )) (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" )) (text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 83 96 105 108)(font "Arial" )) (text "Ratio" (rect 82 91 187 192)(font "Arial" ))
(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" )) (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
(text "DC (%)" (rect 156 96 187 108)(font "Arial" )) (text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" )) (text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "16/11" (rect 83 111 106 123)(font "Arial" )) (text "16/11" (rect 82 104 186 218)(font "Arial" ))
(text "0.00" (rect 127 111 145 123)(font "Arial" )) (text "0.00" (rect 125 104 269 218)(font "Arial" ))
(text "50.00" (rect 160 111 183 123)(font "Arial" )) (text "50.00" (rect 158 104 340 218)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" )) (text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "16/33" (rect 83 126 106 138)(font "Arial" )) (text "16/33" (rect 82 117 187 244)(font "Arial" ))
(text "0.00" (rect 127 126 145 138)(font "Arial" )) (text "0.00" (rect 125 117 269 244)(font "Arial" ))
(text "50.00" (rect 160 126 183 138)(font "Arial" )) (text "50.00" (rect 158 117 340 244)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "1024/1375" (rect 73 141 116 153)(font "Arial" )) (text "1024/1375" (rect 71 130 185 270)(font "Arial" ))
(text "0.00" (rect 127 141 145 153)(font "Arial" )) (text "0.00" (rect 125 130 269 270)(font "Arial" ))
(text "50.00" (rect 160 141 183 153)(font "Arial" )) (text "50.00" (rect 158 130 340 270)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1)) (line (pt 0 0)(pt 273 0))
(line (pt 273 0)(pt 273 185)(line_width 1)) (line (pt 273 0)(pt 273 177))
(line (pt 0 185)(pt 273 185)(line_width 1)) (line (pt 0 177)(pt 273 177))
(line (pt 0 0)(pt 0 185)(line_width 1)) (line (pt 0 0)(pt 0 177))
(line (pt 48 94)(pt 189 94)(line_width 1)) (line (pt 48 89)(pt 186 89))
(line (pt 48 108)(pt 189 108)(line_width 1)) (line (pt 48 101)(pt 186 101))
(line (pt 48 123)(pt 189 123)(line_width 1)) (line (pt 48 114)(pt 186 114))
(line (pt 48 138)(pt 189 138)(line_width 1)) (line (pt 48 127)(pt 186 127))
(line (pt 48 153)(pt 189 153)(line_width 1)) (line (pt 48 140)(pt 186 140))
(line (pt 48 94)(pt 48 153)(line_width 1)) (line (pt 48 89)(pt 48 140))
(line (pt 70 94)(pt 70 153)(line_width 3)) (line (pt 68 89)(pt 68 140)(line_width 3))
(line (pt 118 94)(pt 118 153)(line_width 3)) (line (pt 116 89)(pt 116 140)(line_width 3))
(line (pt 153 94)(pt 153 153)(line_width 3)) (line (pt 151 89)(pt 151 140)(line_width 3))
(line (pt 188 94)(pt 188 153)(line_width 1)) (line (pt 185 89)(pt 185 140))
(line (pt 40 48)(pt 224 48)(line_width 1)) (line (pt 40 48)(pt 223 48))
(line (pt 224 48)(pt 224 168)(line_width 1)) (line (pt 223 48)(pt 223 159))
(line (pt 40 168)(pt 224 168)(line_width 1)) (line (pt 40 159)(pt 223 159))
(line (pt 40 48)(pt 40 168)(line_width 1)) (line (pt 40 48)(pt 40 159))
(line (pt 271 64)(pt 223 64))
(line (pt 271 80)(pt 223 80))
(line (pt 271 96)(pt 223 96))
(line (pt 271 112)(pt 223 112))
) )
) )

2
FPGA_Quartus_13.1/altpll1.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]

64
FPGA_Quartus_13.1/altpll1.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -131,35 +131,35 @@ ARCHITECTURE SYN OF altpll1 IS
width_clock : NATURAL width_clock : NATURAL
); );
PORT ( PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ; locked : OUT STD_LOGIC
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
BEGIN BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0"; sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv); sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire3 <= sub_wire0(2); sub_wire4 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1); sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(0); sub_wire1 <= sub_wire0(1);
c0 <= sub_wire1; c1 <= sub_wire1;
c1 <= sub_wire2; locked <= sub_wire2;
c2 <= sub_wire3; c0 <= sub_wire3;
locked <= sub_wire4; c2 <= sub_wire4;
sub_wire5 <= inclk0; sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll altpll_component : altpll
GENERIC MAP ( GENERIC MAP (
bandwidth_type => "AUTO", bandwidth_type => "AUTO",
clk0_divide_by => 11, clk0_divide_by => 11,
clk0_duty_cycle => 50, clk0_duty_cycle => 50,
clk0_multiply_by => 16, clk0_multiply_by => 16,
clk0_phase_shift => "0", clk0_phase_shift => "0",
clk1_divide_by => 33, clk1_divide_by => 33,
clk1_duty_cycle => 50, clk1_duty_cycle => 50,
clk1_multiply_by => 16, clk1_multiply_by => 16,
clk1_phase_shift => "0", clk1_phase_shift => "0",
clk2_divide_by => 1375, clk2_divide_by => 1375,
clk2_duty_cycle => 50, clk2_duty_cycle => 50,
@@ -218,7 +218,7 @@ BEGIN
PORT MAP ( PORT MAP (
inclk => sub_wire6, inclk => sub_wire6,
clk => sub_wire0, clk => sub_wire0,
locked => sub_wire4 locked => sub_wire2
); );
@@ -244,14 +244,14 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -270,21 +270,21 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
@@ -298,7 +298,7 @@ END SYN;
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -338,13 +338,13 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
@@ -406,17 +406,17 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE

152
FPGA_Quartus_13.1/altpll2.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 304 248) (rect 0 0 256 200)
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2
FPGA_Quartus_13.1/altpll2.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll2.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll2.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]

32
FPGA_Quartus_13.1/altpll2.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS
width_clock : NATURAL width_clock : NATURAL
); );
PORT ( PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
@@ -149,14 +149,14 @@ BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0"; sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv); sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(4); sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3); sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(2); sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(1); sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(0); sub_wire1 <= sub_wire0(1);
c0 <= sub_wire1; c1 <= sub_wire1;
c1 <= sub_wire2; c3 <= sub_wire2;
c2 <= sub_wire3; c0 <= sub_wire3;
c3 <= sub_wire4; c2 <= sub_wire4;
c4 <= sub_wire5; c4 <= sub_wire5;
sub_wire6 <= inclk0; sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
@@ -293,7 +293,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -459,18 +459,18 @@ END SYN;
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 -- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE

250
FPGA_Quartus_13.1/altpll4.bsf
View File

@@ -1,125 +1,125 @@
/* /*
WARNING: Do NOT edit the input and output ports in this file in a text WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including, Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
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(line (pt 377 0)(pt 377 233)(line_width 1)) (line (pt 80 134)(pt 196 134))
(line (pt 0 233)(pt 377 233)(line_width 1)) (line (pt 80 147)(pt 196 147))
(line (pt 0 0)(pt 0 233)(line_width 1)) (line (pt 80 122)(pt 80 147))
(line (pt 96 164)(pt 246 164)(line_width 1)) (line (pt 100 122)(pt 100 147)(line_width 3))
(line (pt 96 181)(pt 246 181)(line_width 1)) (line (pt 126 122)(pt 126 147)(line_width 3))
(line (pt 96 199)(pt 246 199)(line_width 1)) (line (pt 161 122)(pt 161 147)(line_width 3))
(line (pt 96 164)(pt 96 199)(line_width 1)) (line (pt 195 122)(pt 195 147))
(line (pt 122 164)(pt 122 199)(line_width 3)) (line (pt 72 48)(pt 239 48))
(line (pt 156 164)(pt 156 199)(line_width 3)) (line (pt 239 48)(pt 239 168))
(line (pt 201 164)(pt 201 199)(line_width 3)) (line (pt 72 168)(pt 239 168))
(line (pt 245 164)(pt 245 199)(line_width 1)) (line (pt 72 48)(pt 72 168))
(line (pt 88 56)(pt 288 56)(line_width 1)) (line (pt 311 64)(pt 239 64))
(line (pt 288 56)(pt 288 216)(line_width 1)) (line (pt 311 80)(pt 239 80))
(line (pt 88 216)(pt 288 216)(line_width 1)) (line (pt 311 96)(pt 239 96))
(line (pt 88 56)(pt 88 216)(line_width 1)) (line (pt 311 112)(pt 239 112))
) )
) )

60
FPGA_Quartus_13.1/altpll4.cmp
View File

@@ -1,30 +1,30 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
component altpll4 component altpll4
PORT PORT
( (
areset : IN STD_LOGIC := '0'; areset : IN STD_LOGIC := '0';
configupdate : IN STD_LOGIC := '0'; configupdate : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1'; scanclk : IN STD_LOGIC := '1';
scanclkena : IN STD_LOGIC := '0'; scanclkena : IN STD_LOGIC := '0';
scandata : IN STD_LOGIC := '0'; scandata : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ; c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ; locked : OUT STD_LOGIC ;
scandataout : OUT STD_LOGIC ; scandataout : OUT STD_LOGIC ;
scandone : OUT STD_LOGIC scandone : OUT STD_LOGIC
); );
end component; end component;

62
FPGA_Quartus_13.1/altpll4.inc
View File

@@ -1,31 +1,31 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
FUNCTION altpll4 FUNCTION altpll4
( (
areset, areset,
configupdate, configupdate,
inclk0, inclk0,
scanclk, scanclk,
scanclkena, scanclkena,
scandata scandata
) )
RETURNS ( RETURNS (
c0, c0,
locked, locked,
scandataout, scandataout,
scandone scandone
); );

348
FPGA_Quartus_13.1/altpll4.mif
View File

@@ -1,174 +1,174 @@
-- Copyright (C) 1991-2010 Altera Corporation -- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions -- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic -- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing -- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any -- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject -- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License -- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License -- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including, -- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of -- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by -- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the -- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. -- applicable agreement for further details.
-- MIF file representing initial state of PLL Scan Chain -- MIF file representing initial state of PLL Scan Chain
-- Device Family: Cyclone III -- Device Family: Cyclone III
-- Device Part: - -- Device Part: -
-- Device Speed Grade: 8 -- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits) -- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: C:\FireBee\FPGA\altpll4.mif -- File Name: /home/mfro/Dokumente/Development/workspace/FPGA_quartus_ori/altpll4.mif
-- Generated: Mon Dec 06 01:47:24 2010 -- Generated: Fri Oct 30 21:50:08 2015
WIDTH=1; WIDTH=1;
DEPTH=144; DEPTH=144;
ADDRESS_RADIX=UNS; ADDRESS_RADIX=UNS;
DATA_RADIX=UNS; DATA_RADIX=UNS;
CONTENT BEGIN CONTENT BEGIN
0 : 0; -- Reserved Bits = 0 (1 bit(s)) 0 : 0; -- Reserved Bits = 0 (1 bit(s))
1 : 0; -- Reserved Bits = 0 (1 bit(s)) 1 : 0; -- Reserved Bits = 0 (1 bit(s))
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
3 : 0; 3 : 0;
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
5 : 1; 5 : 1;
6 : 0; 6 : 0;
7 : 1; 7 : 1;
8 : 1; 8 : 1;
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
10 : 0; -- Reserved Bits = 0 (5 bit(s)) 10 : 0; -- Reserved Bits = 0 (5 bit(s))
11 : 0; 11 : 0;
12 : 0; 12 : 0;
13 : 0; 13 : 0;
14 : 0; 14 : 0;
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
16 : 0; 16 : 0;
17 : 1; 17 : 1;
18 : 1; -- N counter: Bypass = 1 (1 bit(s)) 18 : 1; -- N counter: Bypass = 1 (1 bit(s))
19 : 0; -- N counter: High Count = 0 (8 bit(s)) 19 : 0; -- N counter: High Count = 0 (8 bit(s))
20 : 0; 20 : 0;
21 : 0; 21 : 0;
22 : 0; 22 : 0;
23 : 0; 23 : 0;
24 : 0; 24 : 0;
25 : 0; 25 : 0;
26 : 0; 26 : 0;
27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) 27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
28 : 0; -- N counter: Low Count = 0 (8 bit(s)) 28 : 0; -- N counter: Low Count = 0 (8 bit(s))
29 : 0; 29 : 0;
30 : 0; 30 : 0;
31 : 0; 31 : 0;
32 : 0; 32 : 0;
33 : 0; 33 : 0;
34 : 0; 34 : 0;
35 : 0; 35 : 0;
36 : 0; -- M counter: Bypass = 0 (1 bit(s)) 36 : 0; -- M counter: Bypass = 0 (1 bit(s))
37 : 0; -- M counter: High Count = 6 (8 bit(s)) 37 : 0; -- M counter: High Count = 6 (8 bit(s))
38 : 0; 38 : 0;
39 : 0; 39 : 0;
40 : 0; 40 : 0;
41 : 0; 41 : 0;
42 : 1; 42 : 1;
43 : 1; 43 : 1;
44 : 0; 44 : 0;
45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) 45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
46 : 0; -- M counter: Low Count = 6 (8 bit(s)) 46 : 0; -- M counter: Low Count = 6 (8 bit(s))
47 : 0; 47 : 0;
48 : 0; 48 : 0;
49 : 0; 49 : 0;
50 : 0; 50 : 0;
51 : 1; 51 : 1;
52 : 1; 52 : 1;
53 : 0; 53 : 0;
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
55 : 0; -- clk0 counter: High Count = 3 (8 bit(s)) 55 : 0; -- clk0 counter: High Count = 3 (8 bit(s))
56 : 0; 56 : 0;
57 : 0; 57 : 0;
58 : 0; 58 : 0;
59 : 0; 59 : 0;
60 : 0; 60 : 0;
61 : 1; 61 : 1;
62 : 1; 62 : 1;
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s)) 64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s))
65 : 0; 65 : 0;
66 : 0; 66 : 0;
67 : 0; 67 : 0;
68 : 0; 68 : 0;
69 : 0; 69 : 0;
70 : 1; 70 : 1;
71 : 1; 71 : 1;
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
74 : 0; 74 : 0;
75 : 0; 75 : 0;
76 : 0; 76 : 0;
77 : 0; 77 : 0;
78 : 0; 78 : 0;
79 : 0; 79 : 0;
80 : 0; 80 : 0;
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
83 : 0; 83 : 0;
84 : 0; 84 : 0;
85 : 0; 85 : 0;
86 : 0; 86 : 0;
87 : 0; 87 : 0;
88 : 0; 88 : 0;
89 : 0; 89 : 0;
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
92 : 0; 92 : 0;
93 : 0; 93 : 0;
94 : 0; 94 : 0;
95 : 0; 95 : 0;
96 : 0; 96 : 0;
97 : 0; 97 : 0;
98 : 0; 98 : 0;
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
101 : 0; 101 : 0;
102 : 0; 102 : 0;
103 : 0; 103 : 0;
104 : 0; 104 : 0;
105 : 0; 105 : 0;
106 : 0; 106 : 0;
107 : 0; 107 : 0;
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
110 : 0; 110 : 0;
111 : 0; 111 : 0;
112 : 0; 112 : 0;
113 : 0; 113 : 0;
114 : 0; 114 : 0;
115 : 0; 115 : 0;
116 : 0; 116 : 0;
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
119 : 0; 119 : 0;
120 : 0; 120 : 0;
121 : 0; 121 : 0;
122 : 0; 122 : 0;
123 : 0; 123 : 0;
124 : 0; 124 : 0;
125 : 0; 125 : 0;
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
128 : 0; 128 : 0;
129 : 0; 129 : 0;
130 : 0; 130 : 0;
131 : 0; 131 : 0;
132 : 0; 132 : 0;
133 : 0; 133 : 0;
134 : 0; 134 : 0;
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
137 : 0; 137 : 0;
138 : 0; 138 : 0;
139 : 0; 139 : 0;
140 : 0; 140 : 0;
141 : 0; 141 : 0;
142 : 0; 142 : 0;
143 : 0; 143 : 0;
END; END;

34
FPGA_Quartus_13.1/altpll4.ppf
View File

@@ -1,17 +1,17 @@
<?xml version="1.0" encoding="UTF-8" ?> <?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan> <!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports"> <pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports">
<global> <global>
<pin name="areset" direction="input" scope="external" /> <pin name="areset" direction="input" scope="external" />
<pin name="configupdate" direction="input" scope="external" /> <pin name="configupdate" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" /> <pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="scanclk" direction="input" scope="external" source="clock" /> <pin name="scanclk" direction="input" scope="external" source="clock" />
<pin name="scanclkena" direction="input" scope="external" /> <pin name="scanclkena" direction="input" scope="external" />
<pin name="scandata" direction="input" scope="external" /> <pin name="scandata" direction="input" scope="external" />
<pin name="c0" direction="output" scope="external" source="clock" /> <pin name="c0" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" /> <pin name="locked" direction="output" scope="external" />
<pin name="scandataout" direction="output" scope="external" /> <pin name="scandataout" direction="output" scope="external" />
<pin name="scandone" direction="output" scope="external" /> <pin name="scandone" direction="output" scope="external" />
</global> </global>
</pinplan> </pinplan>

14
FPGA_Quartus_13.1/altpll4.qip
View File

@@ -1,7 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]

596
FPGA_Quartus_13.1/altpll4.tdf
View File

@@ -1,298 +1,298 @@
-- megafunction wizard: %ALTPLL% -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD -- GENERATION: STANDARD
-- VERSION: WM1.0 -- VERSION: WM1.0
-- MODULE: altpll -- MODULE: altpll
-- ============================================================ -- ============================================================
-- File Name: altpll4.tdf -- File Name: altpll4.tdf
-- Megafunction Name(s): -- Megafunction Name(s):
-- altpll -- altpll
-- --
-- Simulation Library Files(s): -- Simulation Library Files(s):
-- altera_mf -- altera_mf
-- ============================================================ -- ============================================================
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
INCLUDE "altpll.inc"; INCLUDE "altpll.inc";
SUBDESIGN altpll4 SUBDESIGN altpll4
( (
areset : INPUT = GND; areset : INPUT = GND;
configupdate : INPUT = GND; configupdate : INPUT = GND;
inclk0 : INPUT = GND; inclk0 : INPUT = GND;
scanclk : INPUT = VCC; scanclk : INPUT = VCC;
scanclkena : INPUT = GND; scanclkena : INPUT = GND;
scandata : INPUT = GND; scandata : INPUT = GND;
c0 : OUTPUT; c0 : OUTPUT;
locked : OUTPUT; locked : OUTPUT;
scandataout : OUTPUT; scandataout : OUTPUT;
scandone : OUTPUT; scandone : OUTPUT;
) )
VARIABLE VARIABLE
altpll_component : altpll WITH ( altpll_component : altpll WITH (
BANDWIDTH_TYPE = "AUTO", BANDWIDTH_TYPE = "AUTO",
CLK0_DIVIDE_BY = 1, CLK0_DIVIDE_BY = 1,
CLK0_DUTY_CYCLE = 50, CLK0_DUTY_CYCLE = 50,
CLK0_MULTIPLY_BY = 2, CLK0_MULTIPLY_BY = 2,
CLK0_PHASE_SHIFT = "0", CLK0_PHASE_SHIFT = "0",
COMPENSATE_CLOCK = "CLK0", COMPENSATE_CLOCK = "CLK0",
INCLK0_INPUT_FREQUENCY = 20833, INCLK0_INPUT_FREQUENCY = 20833,
INTENDED_DEVICE_FAMILY = "Cyclone III", INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_TYPE = "altpll", LPM_TYPE = "altpll",
OPERATION_MODE = "NORMAL", OPERATION_MODE = "NORMAL",
PLL_TYPE = "AUTO", PLL_TYPE = "AUTO",
PORT_ACTIVECLOCK = "PORT_UNUSED", PORT_ACTIVECLOCK = "PORT_UNUSED",
PORT_ARESET = "PORT_USED", PORT_ARESET = "PORT_USED",
PORT_CLKBAD0 = "PORT_UNUSED", PORT_CLKBAD0 = "PORT_UNUSED",
PORT_CLKBAD1 = "PORT_UNUSED", PORT_CLKBAD1 = "PORT_UNUSED",
PORT_CLKLOSS = "PORT_UNUSED", PORT_CLKLOSS = "PORT_UNUSED",
PORT_CLKSWITCH = "PORT_UNUSED", PORT_CLKSWITCH = "PORT_UNUSED",
PORT_CONFIGUPDATE = "PORT_USED", PORT_CONFIGUPDATE = "PORT_USED",
PORT_FBIN = "PORT_UNUSED", PORT_FBIN = "PORT_UNUSED",
PORT_INCLK0 = "PORT_USED", PORT_INCLK0 = "PORT_USED",
PORT_INCLK1 = "PORT_UNUSED", PORT_INCLK1 = "PORT_UNUSED",
PORT_LOCKED = "PORT_USED", PORT_LOCKED = "PORT_USED",
PORT_PFDENA = "PORT_UNUSED", PORT_PFDENA = "PORT_UNUSED",
PORT_PHASECOUNTERSELECT = "PORT_UNUSED", PORT_PHASECOUNTERSELECT = "PORT_UNUSED",
PORT_PHASEDONE = "PORT_UNUSED", PORT_PHASEDONE = "PORT_UNUSED",
PORT_PHASESTEP = "PORT_UNUSED", PORT_PHASESTEP = "PORT_UNUSED",
PORT_PHASEUPDOWN = "PORT_UNUSED", PORT_PHASEUPDOWN = "PORT_UNUSED",
PORT_PLLENA = "PORT_UNUSED", PORT_PLLENA = "PORT_UNUSED",
PORT_SCANACLR = "PORT_UNUSED", PORT_SCANACLR = "PORT_UNUSED",
PORT_SCANCLK = "PORT_USED", PORT_SCANCLK = "PORT_USED",
PORT_SCANCLKENA = "PORT_USED", PORT_SCANCLKENA = "PORT_USED",
PORT_SCANDATA = "PORT_USED", PORT_SCANDATA = "PORT_USED",
PORT_SCANDATAOUT = "PORT_USED", PORT_SCANDATAOUT = "PORT_USED",
PORT_SCANDONE = "PORT_USED", PORT_SCANDONE = "PORT_USED",
PORT_SCANREAD = "PORT_UNUSED", PORT_SCANREAD = "PORT_UNUSED",
PORT_SCANWRITE = "PORT_UNUSED", PORT_SCANWRITE = "PORT_UNUSED",
PORT_clk0 = "PORT_USED", PORT_clk0 = "PORT_USED",
PORT_clk1 = "PORT_UNUSED", PORT_clk1 = "PORT_UNUSED",
PORT_clk2 = "PORT_UNUSED", PORT_clk2 = "PORT_UNUSED",
PORT_clk3 = "PORT_UNUSED", PORT_clk3 = "PORT_UNUSED",
PORT_clk4 = "PORT_UNUSED", PORT_clk4 = "PORT_UNUSED",
PORT_clk5 = "PORT_UNUSED", PORT_clk5 = "PORT_UNUSED",
PORT_clkena0 = "PORT_UNUSED", PORT_clkena0 = "PORT_UNUSED",
PORT_clkena1 = "PORT_UNUSED", PORT_clkena1 = "PORT_UNUSED",
PORT_clkena2 = "PORT_UNUSED", PORT_clkena2 = "PORT_UNUSED",
PORT_clkena3 = "PORT_UNUSED", PORT_clkena3 = "PORT_UNUSED",
PORT_clkena4 = "PORT_UNUSED", PORT_clkena4 = "PORT_UNUSED",
PORT_clkena5 = "PORT_UNUSED", PORT_clkena5 = "PORT_UNUSED",
PORT_extclk0 = "PORT_UNUSED", PORT_extclk0 = "PORT_UNUSED",
PORT_extclk1 = "PORT_UNUSED", PORT_extclk1 = "PORT_UNUSED",
PORT_extclk2 = "PORT_UNUSED", PORT_extclk2 = "PORT_UNUSED",
PORT_extclk3 = "PORT_UNUSED", PORT_extclk3 = "PORT_UNUSED",
SELF_RESET_ON_LOSS_LOCK = "OFF", SELF_RESET_ON_LOSS_LOCK = "OFF",
WIDTH_CLOCK = 5, WIDTH_CLOCK = 5,
scan_chain_mif_file = "altpll4.mif" scan_chain_mif_file = "altpll4.mif"
); );
BEGIN BEGIN
c0 = altpll_component.clk[0..0]; c0 = altpll_component.clk[0..0];
scandone = altpll_component.scandone; scandataout = altpll_component.scandataout;
scandataout = altpll_component.scandataout; scandone = altpll_component.scandone;
locked = altpll_component.locked; locked = altpll_component.locked;
altpll_component.scanclkena = scanclkena; altpll_component.areset = areset;
altpll_component.inclk[0..0] = inclk0; altpll_component.configupdate = configupdate;
altpll_component.inclk[1..1] = GND; altpll_component.inclk[0..0] = inclk0;
altpll_component.scandata = scandata; altpll_component.inclk[1..1] = GND;
altpll_component.areset = areset; altpll_component.scanclk = scanclk;
altpll_component.scanclk = scanclk; altpll_component.scanclkena = scanclkena;
altpll_component.configupdate = configupdate; altpll_component.scandata = scandata;
END; END;
-- ============================================================ -- ============================================================
-- CNX file retrieval info -- CNX file retrieval info
-- ============================================================ -- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" -- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" -- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" -- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" -- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 -- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 -- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 -- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 -- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 -- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

26
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -41,8 +41,8 @@
# ======================== # ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
# Pin & Location Assignments # Pin & Location Assignments
# ========================== # ==========================
@@ -367,14 +367,14 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
@@ -559,7 +559,7 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
# end ENTITY(firebee1) # end ENTITY(firebee1)
# -------------------- # --------------------
set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_E5 -to LPDIR
set_location_assignment PIN_B11 -to nRSTO_MCF set_location_assignment PIN_B11 -to nRSTO_MCF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
@@ -568,8 +568,8 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
set_location_assignment PIN_AB12 -to CLK33MDIR set_location_assignment PIN_AB12 -to CLK33MDIR
set_location_assignment PIN_E12 -to MIDI_IN_PIN set_location_assignment PIN_E12 -to MIDI_IN_PIN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
@@ -603,9 +603,9 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
set_global_assignment -name POWER_USE_TA_VALUE 35 set_global_assignment -name POWER_USE_TA_VALUE 35
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR

2
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -3,7 +3,7 @@
# Synopsis design constraints for the Firebee project # # Synopsis design constraints for the Firebee project #
# # # #
# This file is part of the Firebee ACP project. # # This file is part of the Firebee ACP project. #
# http://www.experiment-s.de # # http://www.firebee.org #
# # # #
# Description: # # Description: #
# timing constraints for the Firebee VHDL config # # timing constraints for the Firebee VHDL config #