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added another false path to fix timing

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Markus Fröschle
2015-10-18 01:02:05 +00:00
parent 8b7fe5f731
commit 56adcdd218
1 changed files with 1 additions and 0 deletions
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FPGA_Quartus_13.1/firebee1.sdc
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@@ -150,6 +150,7 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl
# MAIN_CLK to DDR clk and v.v.
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]