forked from Firebee/FPGA_Config
create datestamp on the fly during compilation
This commit is contained in:
29
FPGA_by_Fredi/compile_date.bsf
Normal file
29
FPGA_by_Fredi/compile_date.bsf
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2014 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 64 64)
|
||||
(text "compile_date" (rect 5 0 56 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 32 20 44)(font "Arial" ))
|
||||
(drawing
|
||||
(rectangle (rect 16 16 32 32)(line_width 1))
|
||||
)
|
||||
)
|
||||
Reference in New Issue
Block a user