ragnar/FPGA_Config
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finish conversion to vhdl

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This commit is contained in:
Markus Fröschle
2016-01-13 12:53:03 +00:00
parent 79a14e2a70
commit 5183d08d60
3 changed files with 2759 additions and 741 deletions
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12
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
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@@ -604,11 +604,11 @@ BEGIN
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
% RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
%
HDIS_START[] = HDB[] & ACP_VIDEO_ON
# RAND_LINKS[] + 1 & !ACP_VIDEO_ON; --
@@ -618,16 +618,16 @@ BEGIN
RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON
# HDIS_END[] + 1 & !ACP_VIDEO_ON; --
HS_START[] = HSS[] & ACP_VIDEO_ON
% HS_START[] = HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = HHT[] & ACP_VIDEO_ON
%
% H_TOTAL[] = HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
# (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
%
RAND_OBEN[] = VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;

2017
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd Executable file
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File diff suppressed because it is too large Load Diff

11
FPGA_Quartus_13.1/firebee1.qsf
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@@ -660,7 +660,7 @@ set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
@@ -668,6 +668,11 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
@@ -720,7 +725,6 @@ set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
@@ -850,7 +854,4 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top