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translate interrupt_controller to vhd

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This commit is contained in:
Markus Fröschle
2016-01-11 16:11:04 +00:00
parent 98a362dc90
commit 476825a3ba
6 changed files with 7740 additions and 1612 deletions
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6381
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd Executable file
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1
FPGA_Quartus_13.1/Video/video.vhd
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@@ -82,6 +82,7 @@ COMPONENT mux41_0
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;

1471
FPGA_Quartus_13.1/firebee1.qsf
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12
FPGA_Quartus_13.1/firebee1.sdc
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@@ -118,17 +118,21 @@ derive_clock_uncertainty
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}]
#**************************************************************
# Set Clock Groups

1481
FPGA_Quartus_13.1/firebee1.vhd
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6
FPGA_Quartus_13.1/lpm_bustri_WORD.vhd
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@@ -43,7 +43,7 @@ ENTITY lpm_bustri_WORD IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
enabledt : IN STD_LOGIC ;
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_bustri_WORD;
@@ -61,8 +61,8 @@ ARCHITECTURE SYN OF lpm_bustri_word IS
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;