forked from Firebee/FPGA_Config
improve formatting
This commit is contained in:
Markus Fröschle
@@ -9,173 +9,173 @@ library work;
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entity firebee1 is
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port
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(
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MAIN_CLK : in std_logic;
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nRSTO_MCF : in std_logic;
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CLK33MDIR : in std_logic;
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MAIN_CLK : in std_logic;
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nRSTO_MCF : in std_logic;
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CLK33MDIR : in std_logic;
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-- the ColdFire FlexBus signals
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FB_ALE : in std_logic;
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FB_AD : inout std_logic_vector(31 downto 0);
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nFB_OE : in std_logic;
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nFB_WR : in std_logic;
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nFB_TA : out std_logic;
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nFB_CS1 : in std_logic;
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nFB_CS2 : in std_logic;
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nFB_CS3 : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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nFB_BURST : in std_logic;
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FB_ALE : in std_logic;
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FB_AD : inout std_logic_vector(31 downto 0);
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nFB_OE : in std_logic;
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nFB_WR : in std_logic;
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nFB_TA : out std_logic;
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nFB_CS1 : in std_logic;
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nFB_CS2 : in std_logic;
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nFB_CS3 : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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nFB_BURST : in std_logic;
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-- serial port pins
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RxD : in std_logic;
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CTS : in std_logic;
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RI : in std_logic;
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DCD : in std_logic;
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TxD : out std_logic;
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RTS : out std_logic;
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DTR : out std_logic;
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RxD : in std_logic;
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CTS : in std_logic;
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RI : in std_logic;
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DCD : in std_logic;
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TxD : out std_logic;
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RTS : out std_logic;
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DTR : out std_logic;
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-- parallel port
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LP_D : inout std_logic_vector(7 downto 0);
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LP_STR : out std_logic;
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LPDIR : out std_logic;
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LP_BUSY : in std_logic;
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LP_D : inout std_logic_vector(7 downto 0);
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LP_STR : out std_logic;
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LPDIR : out std_logic;
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LP_BUSY : in std_logic;
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AMKB_RX : in std_logic;
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PIC_AMKB_RX : in std_logic;
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AMKB_RX : in std_logic;
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PIC_AMKB_RX : in std_logic;
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IDE_RDY : in std_logic;
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IDE_INT : in std_logic;
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WP_CF_CARD : in std_logic;
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TRACK00 : in std_logic;
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nWP : in std_logic;
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nDCHG : in std_logic;
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SD_DATA0 : in std_logic;
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SD_DATA1 : in std_logic;
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SD_DATA2 : in std_logic;
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sd_card_detect : in std_logic;
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nSCSI_DRQ : in std_logic;
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SD_WP : in std_logic;
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nRD_DATA : in std_logic;
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IDE_RDY : in std_logic;
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IDE_INT : in std_logic;
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WP_CF_CARD : in std_logic;
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TRACK00 : in std_logic;
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nWP : in std_logic;
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nDCHG : in std_logic;
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SD_DATA0 : in std_logic;
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SD_DATA1 : in std_logic;
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SD_DATA2 : in std_logic;
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sd_card_detect : in std_logic;
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nSCSI_DRQ : in std_logic;
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SD_WP : in std_logic;
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nRD_DATA : in std_logic;
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nSCSI_C_D : in std_logic;
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nSCSI_I_O : in std_logic;
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nSCSI_MSG : in std_logic;
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nDACK0 : in std_logic;
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nSCSI_C_D : in std_logic;
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nSCSI_I_O : in std_logic;
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nSCSI_MSG : in std_logic;
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nDACK0 : in std_logic;
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PIC_INT : in std_logic;
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TOUT0 : in std_logic;
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nMASTER : in std_logic;
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DVI_INT : in std_logic;
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nDACK1 : in std_logic;
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PIC_INT : in std_logic;
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TOUT0 : in std_logic;
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nMASTER : in std_logic;
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DVI_INT : in std_logic;
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nDACK1 : in std_logic;
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nPCI_INTD : in std_logic;
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nPCI_INTC : in std_logic;
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nPCI_INTB : in std_logic;
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nPCI_INTA : in std_logic;
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nPCI_INTD : in std_logic;
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nPCI_INTC : in std_logic;
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nPCI_INTB : in std_logic;
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nPCI_INTA : in std_logic;
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E0_INT : in std_logic;
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E0_INT : in std_logic;
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nINDEX : in std_logic;
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HD_DD : in std_logic;
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nINDEX : in std_logic;
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HD_DD : in std_logic;
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SCSI_PAR : inout std_logic;
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nSCSI_RST : inout std_logic;
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nSCSI_SEL : inout std_logic;
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nSCSI_BUSY : inout std_logic;
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SCSI_D : inout std_logic_vector(7 downto 0);
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nSCSI_ACK : out std_logic;
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nSCSI_ATN : out std_logic;
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SCSI_DIR : out std_logic;
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SCSI_PAR : inout std_logic;
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nSCSI_RST : inout std_logic;
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nSCSI_SEL : inout std_logic;
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nSCSI_BUSY : inout std_logic;
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SCSI_D : inout std_logic_vector(7 downto 0);
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nSCSI_ACK : out std_logic;
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nSCSI_ATN : out std_logic;
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SCSI_DIR : out std_logic;
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SD_CD_DATA3 : inout std_logic;
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SD_CMD_D1 : inout std_logic;
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MIDI_IN_PIN : inout std_logic;
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SD_CD_DATA3 : inout std_logic;
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SD_CMD_D1 : inout std_logic;
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MIDI_IN_PIN : inout std_logic;
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IO : inout std_logic_vector(17 downto 0);
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IO : inout std_logic_vector(17 downto 0);
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SRD : inout std_logic_vector(15 downto 0);
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VD : inout std_logic_vector(31 downto 0);
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VDQS : inout std_logic_vector(3 downto 0);
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SRD : inout std_logic_vector(15 downto 0);
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VD : inout std_logic_vector(31 downto 0);
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VDQS : inout std_logic_vector(3 downto 0);
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nACSI_DRQ : in std_logic;
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nACSI_INT : in std_logic;
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nACSI_ACK : out std_logic;
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nACSI_RESET : out std_logic;
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nACSI_CS : out std_logic;
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ACSI_DIR : out std_logic;
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ACSI_A1 : out std_logic;
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ACSI_D : inout std_logic_vector(7 downto 0);
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nACSI_DRQ : in std_logic;
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nACSI_INT : in std_logic;
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nACSI_ACK : out std_logic;
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nACSI_RESET : out std_logic;
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nACSI_CS : out std_logic;
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ACSI_DIR : out std_logic;
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ACSI_A1 : out std_logic;
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ACSI_D : inout std_logic_vector(7 downto 0);
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MIDI_TLR : out std_logic;
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AMKB_TX : out std_logic;
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MIDI_TLR : out std_logic;
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AMKB_TX : out std_logic;
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IDE_RES : out std_logic;
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nIDE_CS0 : out std_logic;
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nIDE_CS1 : out std_logic;
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nIDE_WR : out std_logic;
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nIDE_RD : out std_logic;
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nCF_CS0 : out std_logic;
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nCF_CS1 : out std_logic;
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nROM3 : out std_logic;
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nROM4 : out std_logic;
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nRP_UDS : out std_logic;
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nRP_LDS : out std_logic;
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nSDSEL : out std_logic;
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nWR_GATE : out std_logic;
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nWR : out std_logic;
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IDE_RES : out std_logic;
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nIDE_CS0 : out std_logic;
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nIDE_CS1 : out std_logic;
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nIDE_WR : out std_logic;
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nIDE_RD : out std_logic;
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nCF_CS0 : out std_logic;
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nCF_CS1 : out std_logic;
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nROM3 : out std_logic;
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nROM4 : out std_logic;
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nRP_UDS : out std_logic;
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nRP_LDS : out std_logic;
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nSDSEL : out std_logic;
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nWR_GATE : out std_logic;
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nWR : out std_logic;
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YM_QA : out std_logic;
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YM_QB : out std_logic;
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YM_QC : out std_logic;
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YM_QA : out std_logic;
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YM_QB : out std_logic;
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YM_QC : out std_logic;
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SD_CLK : out std_logic;
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DSA_D : out std_logic;
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nPD_VGA : out std_logic;
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TIN0 : out std_logic;
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nSRCS : out std_logic;
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nSRBLE : out std_logic;
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nSRBHE : out std_logic;
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nSRWE : out std_logic;
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nDREQ1 : out std_logic;
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SD_CLK : out std_logic;
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DSA_D : out std_logic;
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nPD_VGA : out std_logic;
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TIN0 : out std_logic;
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nSRCS : out std_logic;
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nSRBLE : out std_logic;
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nSRBHE : out std_logic;
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nSRWE : out std_logic;
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nDREQ1 : out std_logic;
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LED_FPGA_OK : out std_logic;
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LED_FPGA_OK : out std_logic;
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nSROE : out std_logic;
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nSYNC : out std_logic;
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nMOT_ON : out std_logic;
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nSTEP_DIR : out std_logic;
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nSTEP : out std_logic;
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nSROE : out std_logic;
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nSYNC : out std_logic;
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nMOT_ON : out std_logic;
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nSTEP_DIR : out std_logic;
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nSTEP : out std_logic;
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MIDI_OLR : out std_logic;
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CLK25M : out std_logic;
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CLKUSB : out std_logic;
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CLK24M576 : out std_logic;
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MIDI_OLR : out std_logic;
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CLK25M : out std_logic;
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CLKUSB : out std_logic;
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CLK24M576 : out std_logic;
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nIRQ : out std_logic_vector(7 downto 2);
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nIRQ : out std_logic_vector(7 downto 2);
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-- DDR memory signals
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BA : out std_logic_vector(1 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VDM : out std_logic_vector(3 downto 0);
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VCKE : out std_logic;
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nDDR_CLK : out std_logic;
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DDR_CLK : out std_logic;
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nVWE : out std_logic;
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nVCAS : out std_logic;
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nVRAS : out std_logic;
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nVCS : out std_logic;
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BA : out std_logic_vector(1 downto 0);
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VA : out std_logic_vector(12 downto 0);
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VDM : out std_logic_vector(3 downto 0);
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VCKE : out std_logic;
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nDDR_CLK : out std_logic;
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DDR_CLK : out std_logic;
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nVWE : out std_logic;
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nVCAS : out std_logic;
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nVRAS : out std_logic;
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nVCS : out std_logic;
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-- video signals
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VR : out std_logic_vector(7 downto 0);
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VG : out std_logic_vector(7 downto 0);
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VB : out std_logic_vector(7 downto 0);
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VSYNC_PAD : out std_logic;
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HSYNC_PAD : out std_logic;
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nBLANK_PAD : out std_logic;
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PIXEL_CLK_PAD : out std_logic
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VR : out std_logic_vector(7 downto 0);
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VG : out std_logic_vector(7 downto 0);
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VB : out std_logic_vector(7 downto 0);
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VSYNC_PAD : out std_logic;
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HSYNC_PAD : out std_logic;
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nBLANK_PAD : out std_logic;
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PIXEL_CLK_PAD : out std_logic
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);
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end firebee1;
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@@ -239,23 +239,23 @@ architecture rtl of firebee1 is
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component altpll_reconfig1
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port
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(
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clock : in std_logic ;
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clock : in std_logic;
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counter_param : in std_logic_vector (2 downto 0);
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counter_type : in std_logic_vector (3 downto 0);
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data_in : in std_logic_vector (8 downto 0);
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pll_areset_in : in std_logic := '0';
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pll_scandataout : in std_logic ;
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pll_scandone : in std_logic ;
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read_param : in std_logic ;
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reconfig : in std_logic ;
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reset : in std_logic ;
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write_param : in std_logic ;
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busy : out std_logic ;
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pll_areset_in : in std_logic := '0';
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pll_scandataout : in std_logic;
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pll_scandone : in std_logic;
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read_param : in std_logic;
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reconfig : in std_logic;
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reset : in std_logic;
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write_param : in std_logic;
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busy : out std_logic;
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data_out : out std_logic_vector (8 downto 0);
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pll_areset : out std_logic ;
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pll_configupdate : out std_logic ;
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pll_scanclk : out std_logic ;
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pll_scanclkena : out std_logic ;
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pll_areset : out std_logic;
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pll_configupdate : out std_logic;
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pll_scanclk : out std_logic;
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pll_scanclkena : out std_logic;
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pll_scandata : out std_logic
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);
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end component altpll_reconfig1;
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@@ -282,300 +282,300 @@ begin
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i_atari_clk_pll : work.altpll3
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port map
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(
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inclk0 => MAIN_CLK,
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c0 => clk25m_i,
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c1 => clk2m,
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c2 => clk500k,
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c3 => clk2m4576,
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locked => pll3_locked
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inclk0 => MAIN_CLK,
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c0 => clk25m_i,
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c1 => clk2m,
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c2 => clk500k,
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c3 => clk2m4576,
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locked => pll3_locked
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);
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i_ddr_clk_pll : work.altpll2
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port map
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(
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inclk0 => MAIN_CLK,
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c0 => ddrclk(0),
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c1 => ddrclk(1),
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c2 => ddrclk(2),
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c3 => ddrclk(3),
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c4 => ddr_sync_66m
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inclk0 => MAIN_CLK,
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c0 => ddrclk(0),
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c1 => ddrclk(1),
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c2 => ddrclk(2),
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c3 => ddrclk(3),
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c4 => ddr_sync_66m
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);
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i_dsp : work.dsp
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port map
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(
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clk33m => main_clk,
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MAIN_CLK => MAIN_CLK,
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nFB_OE => nFB_OE,
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nFB_WR => nFB_WR,
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nFB_CS1 => nFB_CS1,
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nFB_CS2 => nFB_CS2,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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nFB_BURST => nFB_BURST,
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nrsto => rsto_n,
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nFB_CS3 => nFB_CS3,
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fb_ad_in => fb_ad_in,
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fb_ad_out => fb_ad_out,
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fb_adr => fb_adr,
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IO => IO,
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SRD => SRD,
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nSRCS => srcs_n_i,
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nSRBLE => nSRBLE,
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nSRBHE => nSRBHE,
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nSRWE => nSRWE,
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nSROE => nSROE,
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dsp_int => dsp_int,
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dsp_ta => dsp_ta
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clk33m => main_clk,
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MAIN_CLK => MAIN_CLK,
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nFB_OE => nFB_OE,
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nFB_WR => nFB_WR,
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nFB_CS1 => nFB_CS1,
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nFB_CS2 => nFB_CS2,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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nFB_BURST => nFB_BURST,
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nrsto => rsto_n,
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nFB_CS3 => nFB_CS3,
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fb_ad_in => fb_ad_in,
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fb_ad_out => fb_ad_out,
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fb_adr => fb_adr,
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IO => IO,
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SRD => SRD,
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nSRCS => srcs_n_i,
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nSRBLE => nSRBLE,
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nSRBHE => nSRBHE,
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nSRWE => nSRWE,
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nSROE => nSROE,
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dsp_int => dsp_int,
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dsp_ta => dsp_ta
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);
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i_falconio_sdcard_ide_cf : entity work.falconio_sdcard_ide_cf
|
||||
port map
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(
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clk33m => main_clk,
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MAIN_CLK => MAIN_CLK,
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clk2m => clk2m,
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clk500k => clk500k,
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nFB_CS1 => nFB_CS1,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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nFB_BURST => nFB_BURST,
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||||
LP_BUSY => LP_BUSY,
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nACSI_DRQ => nACSI_DRQ,
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nACSI_INT => nACSI_INT,
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nSCSI_DRQ => nSCSI_DRQ,
|
||||
nSCSI_MSG => nSCSI_MSG,
|
||||
midi_in => midi_in,
|
||||
RxD => RxD,
|
||||
CTS => CTS,
|
||||
RI => RI,
|
||||
DCD => DCD,
|
||||
AMKB_RX => AMKB_RX,
|
||||
PIC_AMKB_RX => PIC_AMKB_RX,
|
||||
IDE_RDY => IDE_RDY,
|
||||
IDE_INT => IDE_INT,
|
||||
WP_CS_CARD => '0',
|
||||
nINDEX => nINDEX,
|
||||
TRACK00 => TRACK00,
|
||||
nRD_DATA => nRD_DATA,
|
||||
nDCHG => nDCHG,
|
||||
SD_DATA0 => SD_DATA0,
|
||||
SD_DATA1 => SD_DATA1,
|
||||
SD_DATA2 => SD_DATA2,
|
||||
sd_card_dedect => sd_card_detect,
|
||||
SD_WP => SD_WP,
|
||||
nDACK0 => nDACK0,
|
||||
nFB_WR => nFB_WR,
|
||||
WP_CF_CARD => WP_CF_CARD,
|
||||
nWP => nWP,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
nrsto => rsto_n,
|
||||
nSCSI_C_D => nSCSI_C_D,
|
||||
nSCSI_I_O => nSCSI_I_O,
|
||||
clk2m4576 => clk2m4576,
|
||||
nFB_OE => nFB_OE,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
dsp_int => dsp_int,
|
||||
nblank => blank_n,
|
||||
fdc_clk => fdc_clk,
|
||||
FB_ALE => FB_ALE,
|
||||
HD_DD => HD_DD,
|
||||
SCSI_PAR => SCSI_PAR,
|
||||
nSCSI_SEL => nSCSI_SEL,
|
||||
nSCSI_BUSY => nSCSI_BUSY,
|
||||
nSCSI_RST => nSCSI_RST,
|
||||
SD_CD_DATA3 => SD_CD_DATA3,
|
||||
sd_cdm_d1 => sd_cdm_d1,
|
||||
acp_conf => acp_conf(31 downto 24),
|
||||
ACSI_D => ACSI_D,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
LP_D => LP_D,
|
||||
SCSI_D => SCSI_D,
|
||||
nIDE_CS1 => nIDE_CS1,
|
||||
nIDE_CS0 => nIDE_CS0,
|
||||
LP_STR => LP_STR,
|
||||
lp_dir => lp_dir,
|
||||
nACSI_ACK => nACSI_ACK,
|
||||
nACSI_RESET => nACSI_RESET,
|
||||
nACSI_CS => nACSI_CS,
|
||||
ACSI_DIR => ACSI_DIR,
|
||||
ACSI_A1 => ACSI_A1,
|
||||
nSCSI_ACK => nSCSI_ACK,
|
||||
nSCSI_ATN => nSCSI_ATN,
|
||||
SCSI_DIR => SCSI_DIR,
|
||||
SD_CLK => SD_CLK,
|
||||
YM_QA => YM_QA,
|
||||
YM_QC => YM_QC,
|
||||
YM_QB => YM_QB,
|
||||
nSDSEL => nSDSEL,
|
||||
step => step,
|
||||
mot_on => mot_on,
|
||||
nRP_LDS => nRP_LDS,
|
||||
nRP_UDS => nRP_UDS,
|
||||
nROM4 => nROM4,
|
||||
nROM3 => nROM3,
|
||||
nCF_CS1 => nCF_CS1,
|
||||
nCF_CS0 => nCF_CS0,
|
||||
nIDE_RD => ide_rd_n_i,
|
||||
nIDE_WR => ide_wr_n_i,
|
||||
AMKB_TX => AMKB_TX,
|
||||
IDE_RES => IDE_RES,
|
||||
DTR => DTR,
|
||||
RTS => RTS,
|
||||
TxD => TxD,
|
||||
MIDI_OLR => MIDI_OLR,
|
||||
DSA_D => DSA_D,
|
||||
nmfp_int => mfp_int_n,
|
||||
falcon_io_ta => falcon_io_ta,
|
||||
step_dir => step_dir,
|
||||
wr_data => wr_data,
|
||||
wr_gate => wr_gate,
|
||||
dma_drq => dma_drq,
|
||||
MIDI_TLR => MIDI_TLR
|
||||
clk33m => main_clk,
|
||||
MAIN_CLK => MAIN_CLK,
|
||||
clk2m => clk2m,
|
||||
clk500k => clk500k,
|
||||
nFB_CS1 => nFB_CS1,
|
||||
FB_SIZE0 => FB_SIZE0,
|
||||
FB_SIZE1 => FB_SIZE1,
|
||||
nFB_BURST => nFB_BURST,
|
||||
LP_BUSY => LP_BUSY,
|
||||
nACSI_DRQ => nACSI_DRQ,
|
||||
nACSI_INT => nACSI_INT,
|
||||
nSCSI_DRQ => nSCSI_DRQ,
|
||||
nSCSI_MSG => nSCSI_MSG,
|
||||
midi_in => midi_in,
|
||||
RxD => RxD,
|
||||
CTS => CTS,
|
||||
RI => RI,
|
||||
DCD => DCD,
|
||||
AMKB_RX => AMKB_RX,
|
||||
PIC_AMKB_RX => PIC_AMKB_RX,
|
||||
IDE_RDY => IDE_RDY,
|
||||
IDE_INT => IDE_INT,
|
||||
WP_CS_CARD => '0',
|
||||
nINDEX => nINDEX,
|
||||
TRACK00 => TRACK00,
|
||||
nRD_DATA => nRD_DATA,
|
||||
nDCHG => nDCHG,
|
||||
SD_DATA0 => SD_DATA0,
|
||||
SD_DATA1 => SD_DATA1,
|
||||
SD_DATA2 => SD_DATA2,
|
||||
sd_card_dedect => sd_card_detect,
|
||||
SD_WP => SD_WP,
|
||||
nDACK0 => nDACK0,
|
||||
nFB_WR => nFB_WR,
|
||||
WP_CF_CARD => WP_CF_CARD,
|
||||
nWP => nWP,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
nrsto => rsto_n,
|
||||
nSCSI_C_D => nSCSI_C_D,
|
||||
nSCSI_I_O => nSCSI_I_O,
|
||||
clk2m4576 => clk2m4576,
|
||||
nFB_OE => nFB_OE,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
dsp_int => dsp_int,
|
||||
nblank => blank_n,
|
||||
fdc_clk => fdc_clk,
|
||||
FB_ALE => FB_ALE,
|
||||
HD_DD => HD_DD,
|
||||
SCSI_PAR => SCSI_PAR,
|
||||
nSCSI_SEL => nSCSI_SEL,
|
||||
nSCSI_BUSY => nSCSI_BUSY,
|
||||
nSCSI_RST => nSCSI_RST,
|
||||
SD_CD_DATA3 => SD_CD_DATA3,
|
||||
sd_cdm_d1 => sd_cdm_d1,
|
||||
acp_conf => acp_conf(31 downto 24),
|
||||
ACSI_D => ACSI_D,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
LP_D => LP_D,
|
||||
SCSI_D => SCSI_D,
|
||||
nIDE_CS1 => nIDE_CS1,
|
||||
nIDE_CS0 => nIDE_CS0,
|
||||
LP_STR => LP_STR,
|
||||
lp_dir => lp_dir,
|
||||
nACSI_ACK => nACSI_ACK,
|
||||
nACSI_RESET => nACSI_RESET,
|
||||
nACSI_CS => nACSI_CS,
|
||||
ACSI_DIR => ACSI_DIR,
|
||||
ACSI_A1 => ACSI_A1,
|
||||
nSCSI_ACK => nSCSI_ACK,
|
||||
nSCSI_ATN => nSCSI_ATN,
|
||||
SCSI_DIR => SCSI_DIR,
|
||||
SD_CLK => SD_CLK,
|
||||
YM_QA => YM_QA,
|
||||
YM_QC => YM_QC,
|
||||
YM_QB => YM_QB,
|
||||
nSDSEL => nSDSEL,
|
||||
step => step,
|
||||
mot_on => mot_on,
|
||||
nRP_LDS => nRP_LDS,
|
||||
nRP_UDS => nRP_UDS,
|
||||
nROM4 => nROM4,
|
||||
nROM3 => nROM3,
|
||||
nCF_CS1 => nCF_CS1,
|
||||
nCF_CS0 => nCF_CS0,
|
||||
nIDE_RD => ide_rd_n_i,
|
||||
nIDE_WR => ide_wr_n_i,
|
||||
AMKB_TX => AMKB_TX,
|
||||
IDE_RES => IDE_RES,
|
||||
DTR => DTR,
|
||||
RTS => RTS,
|
||||
TxD => TxD,
|
||||
MIDI_OLR => MIDI_OLR,
|
||||
DSA_D => DSA_D,
|
||||
nmfp_int => mfp_int_n,
|
||||
falcon_io_ta => falcon_io_ta,
|
||||
step_dir => step_dir,
|
||||
wr_data => wr_data,
|
||||
wr_gate => wr_gate,
|
||||
dma_drq => dma_drq,
|
||||
MIDI_TLR => MIDI_TLR
|
||||
);
|
||||
|
||||
|
||||
i_interrupt_handler : entity work.interrupt_handler
|
||||
port map
|
||||
(
|
||||
MAIN_CLK => MAIN_CLK,
|
||||
nFB_WR => nFB_WR,
|
||||
nFB_CS1 => nFB_CS1,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
FB_SIZE0 => FB_SIZE0,
|
||||
FB_SIZE1 => FB_SIZE1,
|
||||
PIC_INT => PIC_INT,
|
||||
E0_INT => E0_INT,
|
||||
DVI_INT => DVI_INT,
|
||||
nPCI_INTA => nPCI_INTA,
|
||||
nPCI_INTB => nPCI_INTB,
|
||||
nPCI_INTC => nPCI_INTC,
|
||||
nPCI_INTD => nPCI_INTD,
|
||||
nmfp_int => mfp_int_n,
|
||||
nFB_OE => nFB_OE,
|
||||
dsp_int => dsp_int,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
dma_drq => dma_drq,
|
||||
nrsto => rsto_n,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
int_handler_ta => int_handler_ta,
|
||||
TIN0 => TIN0,
|
||||
acp_conf => acp_conf,
|
||||
nIRQ => nIRQ
|
||||
MAIN_CLK => MAIN_CLK,
|
||||
nFB_WR => nFB_WR,
|
||||
nFB_CS1 => nFB_CS1,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
FB_SIZE0 => FB_SIZE0,
|
||||
FB_SIZE1 => FB_SIZE1,
|
||||
PIC_INT => PIC_INT,
|
||||
E0_INT => E0_INT,
|
||||
DVI_INT => DVI_INT,
|
||||
nPCI_INTA => nPCI_INTA,
|
||||
nPCI_INTB => nPCI_INTB,
|
||||
nPCI_INTC => nPCI_INTC,
|
||||
nPCI_INTD => nPCI_INTD,
|
||||
nmfp_int => mfp_int_n,
|
||||
nFB_OE => nFB_OE,
|
||||
dsp_int => dsp_int,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
dma_drq => dma_drq,
|
||||
nrsto => rsto_n,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
int_handler_ta => int_handler_ta,
|
||||
TIN0 => TIN0,
|
||||
acp_conf => acp_conf,
|
||||
nIRQ => nIRQ
|
||||
);
|
||||
|
||||
i_mfp_acia_clk_pll : entity work.altpll1
|
||||
port map
|
||||
(
|
||||
inclk0 => MAIN_CLK,
|
||||
c0 => clk48m,
|
||||
c1 => fdc_clk,
|
||||
c2 => CLK24M576,
|
||||
locked => pll1_locked
|
||||
inclk0 => MAIN_CLK,
|
||||
c0 => clk48m,
|
||||
c1 => fdc_clk,
|
||||
c2 => CLK24M576,
|
||||
locked => pll1_locked
|
||||
);
|
||||
|
||||
|
||||
i_pll_reconfig : altpll_reconfig1
|
||||
port map
|
||||
(
|
||||
reconfig => video_reconfig,
|
||||
read_param => vr_rd,
|
||||
write_param => vr_wr,
|
||||
pll_areset_in => '0',
|
||||
reconfig => video_reconfig,
|
||||
read_param => vr_rd,
|
||||
write_param => vr_wr,
|
||||
pll_areset_in => '0',
|
||||
pll_scandataout => scandataout,
|
||||
pll_scandone => scandone,
|
||||
clock => MAIN_CLK,
|
||||
reset => reset,
|
||||
counter_param => fb_adr(8 downto 6),
|
||||
counter_type => fb_adr(5 downto 2),
|
||||
data_in => FB_AD(24 downto 16),
|
||||
busy => vr_busy,
|
||||
pll_scandata => scandata,
|
||||
pll_scanclk => scanclk,
|
||||
pll_scanclkena => scan_clkena,
|
||||
pll_scandone => scandone,
|
||||
clock => MAIN_CLK,
|
||||
reset => reset,
|
||||
counter_param => fb_adr(8 downto 6),
|
||||
counter_type => fb_adr(5 downto 2),
|
||||
data_in => FB_AD(24 downto 16),
|
||||
busy => vr_busy,
|
||||
pll_scandata => scandata,
|
||||
pll_scanclk => scanclk,
|
||||
pll_scanclkena => scan_clkena,
|
||||
pll_configupdate => config_update,
|
||||
pll_areset => pll_reset,
|
||||
data_out => vr_d
|
||||
pll_areset => pll_reset,
|
||||
data_out => vr_d
|
||||
);
|
||||
|
||||
i_video : entity work.video
|
||||
port map
|
||||
(
|
||||
MAIN_CLK => MAIN_CLK,
|
||||
nFB_CS1 => nFB_CS1,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
nFB_CS3 => nFB_CS3,
|
||||
nFB_WR => nFB_WR,
|
||||
FB_SIZE0 => FB_SIZE0,
|
||||
FB_SIZE1 => FB_SIZE1,
|
||||
nrsto => rsto_n,
|
||||
nFB_OE => nFB_OE,
|
||||
FB_ALE => FB_ALE,
|
||||
ddr_sync_66m => ddr_sync_66m,
|
||||
MAIN_CLK => MAIN_CLK,
|
||||
nFB_CS1 => nFB_CS1,
|
||||
nFB_CS2 => nFB_CS2,
|
||||
nFB_CS3 => nFB_CS3,
|
||||
nFB_WR => nFB_WR,
|
||||
FB_SIZE0 => FB_SIZE0,
|
||||
FB_SIZE1 => FB_SIZE1,
|
||||
nrsto => rsto_n,
|
||||
nFB_OE => nFB_OE,
|
||||
FB_ALE => FB_ALE,
|
||||
ddr_sync_66m => ddr_sync_66m,
|
||||
-- clk33m => clk33m,
|
||||
clk33m => main_clk,
|
||||
CLK25M => clk25m_i,
|
||||
clk_video => clk_video,
|
||||
vr_busy => vr_busy,
|
||||
ddrclk => ddrclk,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
VD => VD,
|
||||
VDQS => VDQS,
|
||||
vr_d => vr_d,
|
||||
vr_rd => vr_rd,
|
||||
nblank => blank_n,
|
||||
nVWE => nVWE,
|
||||
nVCAS => nVCAS,
|
||||
nVRAS => nVRAS,
|
||||
nVCS => nVCS,
|
||||
nPD_VGA => nPD_VGA,
|
||||
VCKE => VCKE,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
nSYNC => nSYNC,
|
||||
VIDEO_TA => video_ta,
|
||||
pixel_clk => pixel_clk,
|
||||
video_reconfig => video_reconfig,
|
||||
vr_wr => vr_wr,
|
||||
BA => BA,
|
||||
VA => VA,
|
||||
VB => VB,
|
||||
VDM => VDM,
|
||||
VG => VG,
|
||||
VR => VR
|
||||
clk33m => main_clk,
|
||||
CLK25M => clk25m_i,
|
||||
clk_video => clk_video,
|
||||
vr_busy => vr_busy,
|
||||
ddrclk => ddrclk,
|
||||
fb_ad_in => fb_ad_in,
|
||||
fb_ad_out => fb_ad_out,
|
||||
fb_adr => fb_adr,
|
||||
VD => VD,
|
||||
VDQS => VDQS,
|
||||
vr_d => vr_d,
|
||||
vr_rd => vr_rd,
|
||||
nblank => blank_n,
|
||||
nVWE => nVWE,
|
||||
nVCAS => nVCAS,
|
||||
nVRAS => nVRAS,
|
||||
nVCS => nVCS,
|
||||
nPD_VGA => nPD_VGA,
|
||||
VCKE => VCKE,
|
||||
vsync => vsync,
|
||||
hsync => hsync,
|
||||
nSYNC => nSYNC,
|
||||
VIDEO_TA => video_ta,
|
||||
pixel_clk => pixel_clk,
|
||||
video_reconfig => video_reconfig,
|
||||
vr_wr => vr_wr,
|
||||
BA => BA,
|
||||
VA => VA,
|
||||
VB => VB,
|
||||
VDM => VDM,
|
||||
VG => VG,
|
||||
VR => VR
|
||||
);
|
||||
|
||||
i_video_clk_pll : altpll4
|
||||
port map
|
||||
(
|
||||
inclk0 => clk48m,
|
||||
areset => pll_reset,
|
||||
scanclk => scanclk,
|
||||
scandata => scandata,
|
||||
scanclkena => scan_clkena,
|
||||
configupdate => config_update,
|
||||
c0 => clk_video,
|
||||
scandataout => scandataout,
|
||||
scandone => scandone
|
||||
inclk0 => clk48m,
|
||||
areset => pll_reset,
|
||||
scanclk => scanclk,
|
||||
scandata => scandata,
|
||||
scanclkena => scan_clkena,
|
||||
configupdate => config_update,
|
||||
c0 => clk_video,
|
||||
scandataout => scandataout,
|
||||
scandone => scandone
|
||||
);
|
||||
|
||||
|
||||
i_fb_adr_latch : entity work.lpm_ff0
|
||||
port map
|
||||
(
|
||||
clock => ddr_sync_66m,
|
||||
enable => FB_ALE,
|
||||
data => FB_AD,
|
||||
q => fb_adr
|
||||
clock => ddr_sync_66m,
|
||||
enable => FB_ALE,
|
||||
data => FB_AD,
|
||||
q => fb_adr
|
||||
);
|
||||
|
||||
nMOT_ON <= not(mot_on);
|
||||
@@ -586,8 +586,8 @@ begin
|
||||
inst18 : entity work.lpm_counter0
|
||||
port map
|
||||
(
|
||||
clock => clk500k,
|
||||
q => timebase
|
||||
clock => clk500k,
|
||||
q => timebase
|
||||
);
|
||||
|
||||
|
||||
@@ -605,10 +605,10 @@ begin
|
||||
inst29 : alt_iobuf
|
||||
port map
|
||||
(
|
||||
i => clk2m,
|
||||
oe => clk2m,
|
||||
io => MIDI_IN_PIN,
|
||||
o => midi_in
|
||||
i => clk2m,
|
||||
oe => clk2m,
|
||||
io => MIDI_IN_PIN,
|
||||
o => midi_in
|
||||
);
|
||||
|
||||
led_fpga_ok <= timebase(17);
|
||||
@@ -618,39 +618,39 @@ begin
|
||||
inst5 : entity work.altddio_out3
|
||||
port map
|
||||
(
|
||||
datain_h => vsync,
|
||||
datain_l => vsync,
|
||||
outclock => pixel_clk,
|
||||
dataout => VSYNC_PAD
|
||||
datain_h => vsync,
|
||||
datain_l => vsync,
|
||||
outclock => pixel_clk,
|
||||
dataout => VSYNC_PAD
|
||||
);
|
||||
|
||||
|
||||
inst6 : entity work.altddio_out3
|
||||
port map
|
||||
(
|
||||
datain_h => hsync,
|
||||
datain_l => hsync,
|
||||
outclock => pixel_clk,
|
||||
dataout => HSYNC_PAD
|
||||
datain_h => hsync,
|
||||
datain_l => hsync,
|
||||
outclock => pixel_clk,
|
||||
dataout => HSYNC_PAD
|
||||
);
|
||||
|
||||
|
||||
inst8 : entity work.altddio_out3
|
||||
port map
|
||||
(
|
||||
datain_h => blank_n,
|
||||
datain_l => blank_n,
|
||||
outclock => pixel_clk,
|
||||
dataout => nBLANK_PAD
|
||||
datain_h => blank_n,
|
||||
datain_l => blank_n,
|
||||
outclock => pixel_clk,
|
||||
dataout => nBLANK_PAD
|
||||
);
|
||||
|
||||
inst9 : entity work.altddio_out3
|
||||
port map
|
||||
(
|
||||
datain_h => '0',
|
||||
datain_l => '1',
|
||||
outclock => pixel_clk,
|
||||
dataout => PIXEL_CLK_PAD
|
||||
datain_h => '0',
|
||||
datain_l => '1',
|
||||
outclock => pixel_clk,
|
||||
dataout => PIXEL_CLK_PAD
|
||||
);
|
||||
|
||||
SD_CMD_D1 <= sd_cdm_d1;
|
||||
|
||||
Reference in New Issue
Block a user