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improve formatting

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This commit is contained in:
Markus Fröschle
2018-08-19 19:02:11 +02:00
parent d774f3bd95
commit 4164ee3a7b
1 changed files with 412 additions and 412 deletions
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24
FPGA_Quartus_13.1/firebee1.vhd
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@@ -239,23 +239,23 @@ architecture rtl of firebee1 is
component altpll_reconfig1
port
(
clock : in std_logic ;
clock : in std_logic;
counter_param : in std_logic_vector (2 downto 0);
counter_type : in std_logic_vector (3 downto 0);
data_in : in std_logic_vector (8 downto 0);
pll_areset_in : in std_logic := '0';
pll_scandataout : in std_logic ;
pll_scandone : in std_logic ;
read_param : in std_logic ;
reconfig : in std_logic ;
reset : in std_logic ;
write_param : in std_logic ;
busy : out std_logic ;
pll_scandataout : in std_logic;
pll_scandone : in std_logic;
read_param : in std_logic;
reconfig : in std_logic;
reset : in std_logic;
write_param : in std_logic;
busy : out std_logic;
data_out : out std_logic_vector (8 downto 0);
pll_areset : out std_logic ;
pll_configupdate : out std_logic ;
pll_scanclk : out std_logic ;
pll_scanclkena : out std_logic ;
pll_areset : out std_logic;
pll_configupdate : out std_logic;
pll_scanclk : out std_logic;
pll_scanclkena : out std_logic;
pll_scandata : out std_logic
);
end component altpll_reconfig1;