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aschi54
2010-12-27 13:20:36 +00:00
committed by David Gálvez
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FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

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FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"FEDCBA9876543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

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FPGA_by_Fredi/Video/DDR_CTR.tdf Normal file
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TITLE "DDR_CTR";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK
CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 200;
CONSTANT FIFO_HWM = 500;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT;
BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT;
FIFO_MW[8..0] : INPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT;
SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
DS_CB6, DS_CB8, -- CLOSE FIFO BANK
DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA_P[12..0] :DFF;
BA_P[1..0] :DFF;
VA_S[12..0] :DFF;
BA_S[1..0] :DFF;
MCS[1..0] :DFF;
CPU_DDR_SYNC :DFF;
DDR_SEL :NODE;
DDR_CS :DFFE;
DDR_CONFIG :NODE;
SR_DDR_WR :DFF;
SR_DDRWR_D_SEL :DFF;
SR_VDMP[7..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA[1..0] :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
CPU_AC :DFF;
BUS_CYC :DFF;
BUS_CYC_END :NODE;
BLITTER_REQ :DFF;
BLITTER_AC :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA[1..0] :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_REQ :DFF;
FIFO_AC :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA[1..0] :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_ACTIVE :NODE;
CLR_FIFO_SYNC :DFF;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
SR_FIFO_WRE :DFF;
FIFO_BANK_OK :DFF;
FIFO_BANK_NOT_OK :NODE;
DDR_REFRESH_ON :NODE;
DDR_REFRESH_CNT[10..0] :DFF;
DDR_REFRESH_REQ :DFF;
DDR_REFRESH_SIG[3..0] :DFFE;
REFRESH_TIME :DFF;
VIDEO_BASE_L_D[7..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[2..0] :DFFE;
VIDEO_ADR_CNT[22..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[22..0] :NODE;
VIDEO_ACT_ADR[26..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0 -- ADR==0
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
FB_LE0 = !nFB_WR;
IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
IF DDR_CS THEN
FB_LE0 = !nFB_WR;
VIDEO_DDR_TA = VCC;
IF LINE THEN
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_REGDDR = FR_S1;
ELSE
BUS_CYC_END = VCC;
FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_REGDDR = FR_WAIT;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
IF DDR_CS THEN
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S2;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S2 =>
IF DDR_CS THEN
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
FB_REGDDR = FR_S2;
ELSE
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S3;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S3 =>
IF DDR_CS THEN
FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
VIDEO_DDR_TA = VCC;
BUS_CYC_END = VCC;
FB_REGDDR = FR_WAIT;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
MCS1 = MCS0;
CPU_DDR_SYNC.CLK = DDRCLK0;
CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
---------------------------------------------------
VA_S[].CLK = DDRCLK0;
BA_S[].CLK = DDRCLK0;
VA[] = VA_S[];
BA[] = BA_S[];
VA_P[].CLK = DDRCLK0;
BA_P[].CLK = DDRCLK0;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF DDR_REFRESH_REQ THEN
DDR_SM = DS_R2;
ELSE
IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
IF DDR_CONFIG THEN -- JA
DDR_SM = DS_C2;
ELSE
IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
VA_S[] = CPU_ROW_ADR[];
BA_S[] = CPU_BA[];
CPU_AC = VCC;
BUS_CYC = VCC;
DDR_SM = DS_T2B;
ELSE
IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
VA_P[] = FIFO_ROW_ADR[];
BA_P[] = FIFO_BA[];
FIFO_AC = VCC; -- VORBESETZEN
ELSE
VA_P[] = BLITTER_ROW_ADR[];
BA_P[] = BLITTER_BA[];
BLITTER_AC = VCC; -- VORBESETZEN
END IF;
DDR_SM = DS_T2A;
END IF;
END IF;
ELSE
DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
END IF;
END IF;
WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
IF DDR_SEL & (nFB_WR # !LINE) THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
ELSE
VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
VA[] = VA_P[];
BA[] = BA_P[];
VA_S[10] = !(FIFO_AC & FIFO_REQ);
FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
FIFO_AC = FIFO_AC & FIFO_REQ;
BLITTER_AC = BLITTER_AC & BLITTER_REQ;
END IF;
DDR_SM = DS_T3;
WHEN DS_T2B =>
VRAS = VCC;
FIFO_BANK_NOT_OK = VCC;
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
DDR_SM = DS_T3;
WHEN DS_T3 =>
CPU_AC = CPU_AC;
FIFO_AC = FIFO_AC;
BLITTER_AC = BLITTER_AC;
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
DDR_SM = DS_T4W;
ELSE
IF CPU_AC THEN -- CPU?
VA_S[9..0] = CPU_COL_ADR[];
BA_S[] = CPU_BA[];
DDR_SM = DS_T4R;
ELSE
IF FIFO_AC THEN -- FIFO?
VA_S[9..0] = FIFO_COL_ADR[];
BA_S[] = FIFO_BA[];
DDR_SM = DS_T4F;
ELSE
IF BLITTER_AC THEN
VA_S[9..0] = BLITTER_COL_ADR[];
BA_S[] = BLITTER_BA[];
DDR_SM = DS_T4R;
ELSE
DDR_SM = DS_N8;
END IF;
END IF;
END IF;
END IF;
-- READ
WHEN DS_T4R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
WHEN DS_T5R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- WRITE
WHEN DS_T4W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
DDR_SM = DS_T5W;
WHEN DS_T5W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
# BLITTER_AC & BLITTER_COL_ADR[];
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
DDR_SM = DS_T9W;
WHEN DS_T9W =>
IF FIFO_REQ & FIFO_BANK_OK THEN
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- FIFO READ
WHEN DS_T4F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T5F;
WHEN DS_T5F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
END IF;
WHEN DS_T6F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
WHEN DS_T7F =>
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T8F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
END IF;
END IF;
WHEN DS_T8F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
DDR_SM = DS_T5F; -- JA->
ELSE
DDR_SM = DS_T9F;
END IF;
WHEN DS_T9F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_P[9..0] = FIFO_COL_ADR[]+4;
VA_P[10] = GND; -- NON AUTO PRECHARGE
BA_P[] = FIFO_BA[];
DDR_SM = DS_T10F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
END IF;
WHEN DS_T10F =>
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
DDR_SM = DS_T3;
ELSE
VCAS = VCC;
VA[] = VA_P[];
BA[] = BA_P[];
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
END IF;
-- CONFIG CYCLUS
WHEN DS_C2 =>
DDR_SM = DS_C3;
WHEN DS_C3 =>
BUS_CYC = CPU_REQ;
DDR_SM = DS_C4;
WHEN DS_C4 =>
IF CPU_REQ THEN
DDR_SM = DS_C5;
ELSE
DDR_SM = DS_T1;
END IF;
WHEN DS_C5 =>
DDR_SM = DS_C6;
WHEN DS_C6 =>
VA_S[] = FB_AD[12..0];
BA_S[] = FB_AD[14..13];
DDR_SM = DS_C7;
WHEN DS_C7 =>
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
DDR_SM = DS_N8;
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
WHEN DS_R2 =>
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
VWE = VCC;
VA[10] = VCC;
FIFO_BANK_NOT_OK = VCC;
DDR_SM = DS_R4;
ELSE
VCAS = VCC;
VRAS = VCC;
DDR_SM = DS_R3;
END IF;
WHEN DS_R3 =>
DDR_SM = DS_R4;
WHEN DS_R4 =>
DDR_SM = DS_R5;
WHEN DS_R5 =>
DDR_SM = DS_R6;
WHEN DS_R6 =>
DDR_SM = DS_N5;
-- LEERSCHLAUFE
WHEN DS_N5 =>
DDR_SM = DS_N6;
WHEN DS_N6 =>
DDR_SM = DS_N7;
WHEN DS_N7 =>
DDR_SM = DS_N8;
WHEN DS_N8 =>
DDR_SM = DS_T1;
END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------
-- FIFO ---------------------------------
--------------------------------------------------------
FIFO_REQ.CLK = DDRCLK0;
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
FIFO_BA1 = VIDEO_ADR_CNT9;
FIFO_BA0 = VIDEO_ADR_CNT8;
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-- AKTUELLE VIDEO ADRESSE
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
-----------------------------------------------------------------------------------------
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[26..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[]
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
END;

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FPGA_by_Fredi/Video/DDR_CTR.tdf.bak Normal file
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TITLE "DDR_CTR";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK
CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 200;
CONSTANT FIFO_HWM = 500;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT;
BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT;
FIFO_MW[8..0] : INPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
CLEAR_FIFO_CNT : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT;
SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
DS_CB6, DS_CB8, -- CLOSE FIFO BANK
DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA_P[12..0] :DFF;
BA_P[1..0] :DFF;
VA_S[12..0] :DFF;
BA_S[1..0] :DFF;
MCS[1..0] :DFF;
CPU_DDR_SYNC :DFF;
DDR_SEL :NODE;
DDR_CS :DFFE;
DDR_CONFIG :NODE;
SR_DDR_WR :DFF;
SR_DDRWR_D_SEL :DFF;
SR_VDMP[7..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA[1..0] :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
CPU_AC :DFF;
BUS_CYC :DFF;
BUS_CYC_END :NODE;
BLITTER_REQ :DFF;
BLITTER_AC :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA[1..0] :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_REQ :DFF;
FIFO_AC :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA[1..0] :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_ACTIVE :NODE;
CLR_FIFO_SYNC :DFF;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
SR_FIFO_WRE :DFF;
FIFO_BANK_OK :DFF;
FIFO_BANK_NOT_OK :NODE;
DDR_REFRESH_ON :NODE;
DDR_REFRESH_CNT[10..0] :DFF;
DDR_REFRESH_REQ :DFF;
DDR_REFRESH_SIG[3..0] :DFFE;
REFRESH_TIME :DFF;
VIDEO_BASE_L_D[7..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[2..0] :DFFE;
VIDEO_ADR_CNT[22..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[22..0] :NODE;
VIDEO_ACT_ADR[26..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0 -- ADR==0
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
FB_LE0 = !nFB_WR;
IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
IF DDR_CS THEN
FB_LE0 = !nFB_WR;
VIDEO_DDR_TA = VCC;
IF LINE THEN
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_REGDDR = FR_S1;
ELSE
BUS_CYC_END = VCC;
FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_REGDDR = FR_WAIT;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
IF DDR_CS THEN
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S2;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S2 =>
IF DDR_CS THEN
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
FB_REGDDR = FR_S2;
ELSE
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S3;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S3 =>
IF DDR_CS THEN
FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
VIDEO_DDR_TA = VCC;
BUS_CYC_END = VCC;
FB_REGDDR = FR_WAIT;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
MCS1 = MCS0;
CPU_DDR_SYNC.CLK = DDRCLK0;
CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
---------------------------------------------------
VA_S[].CLK = DDRCLK0;
BA_S[].CLK = DDRCLK0;
VA[] = VA_S[];
BA[] = BA_S[];
VA_P[].CLK = DDRCLK0;
BA_P[].CLK = DDRCLK0;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF DDR_REFRESH_REQ THEN
DDR_SM = DS_R2;
ELSE
IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
IF DDR_CONFIG THEN -- JA
DDR_SM = DS_C2;
ELSE
IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
VA_S[] = CPU_ROW_ADR[];
BA_S[] = CPU_BA[];
CPU_AC = VCC;
BUS_CYC = VCC;
DDR_SM = DS_T2B;
ELSE
IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
VA_P[] = FIFO_ROW_ADR[];
BA_P[] = FIFO_BA[];
FIFO_AC = VCC; -- VORBESETZEN
ELSE
VA_P[] = BLITTER_ROW_ADR[];
BA_P[] = BLITTER_BA[];
BLITTER_AC = VCC; -- VORBESETZEN
END IF;
DDR_SM = DS_T2A;
END IF;
END IF;
ELSE
DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
END IF;
END IF;
WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
IF DDR_SEL & (nFB_WR # !LINE) THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
ELSE
VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
VA[] = VA_P[];
BA[] = BA_P[];
VA_S[10] = !(FIFO_AC & FIFO_REQ);
FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
FIFO_AC = FIFO_AC & FIFO_REQ;
BLITTER_AC = BLITTER_AC & BLITTER_REQ;
END IF;
DDR_SM = DS_T3;
WHEN DS_T2B =>
VRAS = VCC;
FIFO_BANK_NOT_OK = VCC;
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
DDR_SM = DS_T3;
WHEN DS_T3 =>
CPU_AC = CPU_AC;
FIFO_AC = FIFO_AC;
BLITTER_AC = BLITTER_AC;
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
DDR_SM = DS_T4W;
ELSE
IF CPU_AC THEN -- CPU?
VA_S[9..0] = CPU_COL_ADR[];
BA_S[] = CPU_BA[];
DDR_SM = DS_T4R;
ELSE
IF FIFO_AC THEN -- FIFO?
VA_S[9..0] = FIFO_COL_ADR[];
BA_S[] = FIFO_BA[];
DDR_SM = DS_T4F;
ELSE
IF BLITTER_AC THEN
VA_S[9..0] = BLITTER_COL_ADR[];
BA_S[] = BLITTER_BA[];
DDR_SM = DS_T4R;
ELSE
DDR_SM = DS_N8;
END IF;
END IF;
END IF;
END IF;
-- READ
WHEN DS_T4R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
WHEN DS_T5R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- WRITE
WHEN DS_T4W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
DDR_SM = DS_T5W;
WHEN DS_T5W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
# BLITTER_AC & BLITTER_COL_ADR[];
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
DDR_SM = DS_T9W;
WHEN DS_T9W =>
IF FIFO_REQ & FIFO_BANK_OK THEN
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- FIFO READ
WHEN DS_T4F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T5F;
WHEN DS_T5F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
END IF;
WHEN DS_T6F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
WHEN DS_T7F =>
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T8F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
END IF;
END IF;
WHEN DS_T8F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
DDR_SM = DS_T5F; -- JA->
ELSE
DDR_SM = DS_T9F;
END IF;
WHEN DS_T9F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_P[9..0] = FIFO_COL_ADR[]+4;
VA_P[10] = GND; -- NON AUTO PRECHARGE
BA_P[] = FIFO_BA[];
DDR_SM = DS_T10F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
END IF;
WHEN DS_T10F =>
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
DDR_SM = DS_T3;
ELSE
VCAS = VCC;
VA[] = VA_P[];
BA[] = BA_P[];
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
END IF;
-- CONFIG CYCLUS
WHEN DS_C2 =>
DDR_SM = DS_C3;
WHEN DS_C3 =>
BUS_CYC = CPU_REQ;
DDR_SM = DS_C4;
WHEN DS_C4 =>
IF CPU_REQ THEN
DDR_SM = DS_C5;
ELSE
DDR_SM = DS_T1;
END IF;
WHEN DS_C5 =>
DDR_SM = DS_C6;
WHEN DS_C6 =>
VA_S[] = FB_AD[12..0];
BA_S[] = FB_AD[14..13];
DDR_SM = DS_C7;
WHEN DS_C7 =>
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
DDR_SM = DS_N8;
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
WHEN DS_R2 =>
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
VWE = VCC;
VA[10] = VCC;
FIFO_BANK_NOT_OK = VCC;
DDR_SM = DS_R4;
ELSE
VCAS = VCC;
VRAS = VCC;
DDR_SM = DS_R3;
END IF;
WHEN DS_R3 =>
DDR_SM = DS_R4;
WHEN DS_R4 =>
DDR_SM = DS_R5;
WHEN DS_R5 =>
DDR_SM = DS_R6;
WHEN DS_R6 =>
DDR_SM = DS_N5;
-- LEERSCHLAUFE
WHEN DS_N5 =>
DDR_SM = DS_N6;
WHEN DS_N6 =>
DDR_SM = DS_N7;
WHEN DS_N7 =>
DDR_SM = DS_N8;
WHEN DS_N8 =>
DDR_SM = DS_T1;
END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------
-- FIFO ---------------------------------
--------------------------------------------------------
FIFO_REQ.CLK = DDRCLK0;
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
FIFO_BA1 = VIDEO_ADR_CNT9;
FIFO_BA0 = VIDEO_ADR_CNT8;
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-- AKTUELLE VIDEO ADRESSE
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
-----------------------------------------------------------------------------------------
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[26..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[]
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
END;

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FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak Normal file
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TITLE "DDR_CTR_BLITTER";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR_BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FIFO_FULL : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
VSYNC : INPUT;
BLITTER_ON : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
VDVZ[127..0] : INPUT;
DDRCLK[3..0] : INPUT;
BA0 : OUTPUT;
BA1 : OUTPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FIFO_WRE : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
START_CYC_RDWR : OUTPUT;
DDR_WR : OUTPUT;
CLEAR_FIFO_CNT : OUTPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_LE[3..0] : OUTPUT;
BLITTER_RDE : OUTPUT;
DDRWR_D_SEL[1..0] : OUTPUT;
VDMP[7..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA[12..0] :NODE;
BA0 :NODE;
BA1 :NODE;
DDR_WR :DFF;
DDR_SEL :NODE;
DDR_CONFIG :NODE;
DDRWR_D_SEL[1..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA0 :NODE;
CPU_BA1 :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
BLITTER_SIG :NODE;
BLITTER_REQ :DFF;
BLITTER_RUN :DFF;
BLITTER_WR :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA0 :NODE;
BLITTER_BA1 :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_SIG :NODE;
FIFO_REQ :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA0 :NODE;
FIFO_BA1 :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_WRE :DFF;
FIFO_ACTIVE :NODE;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
DDR_REFRESH_ON :NODE;
VIDEO_BASE_L_D[3..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[7..0] :DFFE;
VIDEO_ADR_CNT[27..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[27..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
IF DDR_SEL THEN
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_LE0 = !nFB_WR;
IF LINE THEN
FB_REGDDR = FR_S1;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
FB_REGDDR = FR_S2;
WHEN FR_S2 =>
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
FB_REGDDR = FR_S3;
WHEN FR_S3 =>
FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
FB_REGDDR = FR_WAIT;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
FIFO_ACTIVE = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
DDR_REFRESH_ON = VIDEO_RAM_CTR4;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA1 = FB_ADR13;
CPU_BA0 = FB_ADR12;
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
DDR_WR.CLK = DDRCLK0;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..29]==B"011";
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS
# FR_S0 & !nFB_WR -- WRITE SP<53>TER AUCH CONFIG
# FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE
CPU_REQ = CPU_SIG;
CPU_REQ.CLK = DDR_SYNC_66M;
DDR_D_SEL[].CLK = DDRCLK3;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF MAIN_CLK THEN
DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4)
DDR_SM = DS_T2;
ELSE
DDR_SM = DS_LS; -- SYNCHRONISIEREN
END IF;
WHEN DS_T2 =>
IF !DDR_CONFIG THEN
VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
VA[] = CPU_SIG & CPU_ROW_ADR[]
# BLITTER_SIG & BLITTER_ROW_ADR[]
# FIFO_SIG & FIFO_ROW_ADR[];
BA0 = CPU_SIG & CPU_BA0
# BLITTER_SIG & BLITTER_BA0
# FIFO_SIG & FIFO_BA0;
BA1 = CPU_SIG & CPU_BA1
# BLITTER_SIG & BLITTER_BA1
# FIFO_SIG & FIFO_BA1;
VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS
BLITTER_REQ = BLITTER_SIG;
FIFO_REQ = FIFO_SIG;
END IF;
IF MAIN_CLK THEN
DDR_SM = DS_T3;
ELSE
DDR_SM = DS_LS;
END IF;
WHEN DS_T3 =>
IF DDR_CONFIG & CPU_REQ THEN
VRAS = FB_AD18;
VCAS = FB_AD17;
VWE = FB_AD16;
BA1 = FB_AD14;
BA0 = FB_AD13;
VA[] = FB_AD[12..0];
END IF;
IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
DDR_SM = DS_LS;
ELSE
BLITTER_REQ = BLITTER_SIG;
FIFO_REQ = FIFO_SIG;
DDR_SM = DS_T4;
END IF;
WHEN DS_T4 =>
FIFO_REQ = FIFO_SIG;
VCAS = VCC;
VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
VA[9..0] = CPU_REQ & CPU_COL_ADR[]
# BLITTER_REQ & BLITTER_COL_ADR[]
# FIFO_REQ & FIFO_COL_ADR[];
VA10 = VCC; -- AUTO PRECHARGE
BA0 = CPU_REQ & CPU_BA0
# BLITTER_REQ & BLITTER_BA0
# FIFO_REQ & FIFO_BA0;
BA1 = CPU_REQ & CPU_BA1
# BLITTER_REQ & BLITTER_BA1
# FIFO_REQ & FIFO_BA1;
DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
FIFO_REQ = FIFO_SIG;
IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
DDR_SM = DS_T5; -- JA->
ELSE
DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
END IF;
WHEN DS_T5 =>
FIFO_REQ = FIFO_SIG;
DDR_SM = DS_T6;
WHEN DS_T6 =>
IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ
VRAS = VCC;
VA[] = CPU_ROW_ADR[];
BA1 = CPU_BA1;
BA0 = CPU_BA0;
DDR_SM = DS_T3;
ELSE
FIFO_REQ = FIFO_SIG;
VCAS = VCC;
VA[9..0] = FIFO_COL_ADR[];
VA10 = VCC; -- AUTO PRECHARGE
BA0 = FIFO_BA0;
BA1 = FIFO_BA1;
FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133
IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
DDR_SM = DS_T5; -- JA->
ELSE
DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
END IF;
END IF;
WHEN DS_LS =>
IF !MAIN_CLK THEN -- LEERSTATE UND SYNC
DDR_SM = DS_T1;
ELSE
DDR_SM = DS_LS;
END IF;
END CASE;
------------------------------------------------------------------------------
-- FIFO ---------------------------------
FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
FIFO_REQ.CLK = DDR_SYNC_66M;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
FIFO_BA1 = VIDEO_ADR_CNT11;
FIFO_BA0 = VIDEO_ADR_CNT10;
FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
-- Z<>HLER R<>CKSETZEN WENN VSYNC ----------------
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = VSYNC # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET
# !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS
VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
FIFO_WRE.CLK = DDRCLK0;
---------------------------------------------------------------
-- BLITTER BUS IST 128 BIT BREIT ------
BLITTER_SIG = GND & !CPU_SIG;
BLITTER_REQ.CLK = DDR_SYNC_66M;
BLITTER_RUN.CLK = DDRCLK0;
BLITTER_RUN = GND;
BLITTER_WR.CLK = DDRCLK0;
BLITTER_WR = GND;
DDRWR_D_SEL1 = BLITTER_WR;
BLITTER_ROW_ADR[] = H"0";
BLITTER_BA1 = GND;
BLITTER_BA0 = GND;
BLITTER_COL_ADR[] = H"0";
BLITTER_DOUT[] = H"0";
BLITTER_LE[] = H"0";
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[31..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & VIDEO_BASE_X_D[]
# VIDEO_CNT_H & VIDEO_ADR_CNT[27..20]
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000")
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000")
# VIDEO_CNT_M & VIDEO_ADR_CNT[11..4]
# VIDEO_CNT_H & VIDEO_ADR_CNT[19..12]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[];
END;

267
FPGA_by_Fredi/Video/UNUSED Normal file
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-- Clearbox generated Memory Initialization File (.mif)
WIDTH=6;
DEPTH=256;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
000 : 0F;
001 : 0E;
002 : 0D;
003 : 0C;
004 : 0B;
005 : 0A;
006 : 09;
007 : 08;
008 : 07;
009 : 06;
00a : 05;
00b : 04;
00c : 03;
00d : 02;
00e : 01;
00f : 00;
010 : 0F;
011 : 0E;
012 : 0D;
013 : 0C;
014 : 0B;
015 : 0A;
016 : 09;
017 : 08;
018 : 07;
019 : 06;
01a : 05;
01b : 04;
01c : 03;
01d : 02;
01e : 01;
01f : 00;
020 : 0F;
021 : 0E;
022 : 0D;
023 : 0C;
024 : 0B;
025 : 0A;
026 : 09;
027 : 08;
028 : 07;
029 : 06;
02a : 05;
02b : 04;
02c : 03;
02d : 02;
02e : 01;
02f : 00;
030 : 0F;
031 : 0E;
032 : 0D;
033 : 0C;
034 : 0B;
035 : 0A;
036 : 09;
037 : 08;
038 : 07;
039 : 06;
03a : 05;
03b : 04;
03c : 03;
03d : 02;
03e : 01;
03f : 00;
040 : 0F;
041 : 0E;
042 : 0D;
043 : 0C;
044 : 0B;
045 : 0A;
046 : 09;
047 : 08;
048 : 07;
049 : 06;
04a : 05;
04b : 04;
04c : 03;
04d : 02;
04e : 01;
04f : 00;
050 : 0F;
051 : 0E;
052 : 0D;
053 : 0C;
054 : 0B;
055 : 0A;
056 : 09;
057 : 08;
058 : 07;
059 : 06;
05a : 05;
05b : 04;
05c : 03;
05d : 02;
05e : 01;
05f : 00;
060 : 0F;
061 : 0E;
062 : 0D;
063 : 0C;
064 : 0B;
065 : 0A;
066 : 09;
067 : 08;
068 : 07;
069 : 06;
06a : 05;
06b : 04;
06c : 03;
06d : 02;
06e : 01;
06f : 00;
070 : 0F;
071 : 0E;
072 : 0D;
073 : 0C;
074 : 0B;
075 : 0A;
076 : 09;
077 : 08;
078 : 07;
079 : 06;
07a : 05;
07b : 04;
07c : 03;
07d : 02;
07e : 01;
07f : 00;
080 : 0F;
081 : 0E;
082 : 0D;
083 : 0C;
084 : 0B;
085 : 0A;
086 : 09;
087 : 08;
088 : 07;
089 : 06;
08a : 05;
08b : 04;
08c : 03;
08d : 02;
08e : 01;
08f : 00;
090 : 0F;
091 : 0E;
092 : 0D;
093 : 0C;
094 : 0B;
095 : 0A;
096 : 09;
097 : 08;
098 : 07;
099 : 06;
09a : 05;
09b : 04;
09c : 03;
09d : 02;
09e : 01;
09f : 00;
0a0 : 0F;
0a1 : 0E;
0a2 : 0D;
0a3 : 0C;
0a4 : 0B;
0a5 : 0A;
0a6 : 09;
0a7 : 08;
0a8 : 07;
0a9 : 06;
0aa : 05;
0ab : 04;
0ac : 03;
0ad : 02;
0ae : 01;
0af : 00;
0b0 : 0F;
0b1 : 0E;
0b2 : 0D;
0b3 : 0C;
0b4 : 0B;
0b5 : 0A;
0b6 : 09;
0b7 : 08;
0b8 : 07;
0b9 : 06;
0ba : 05;
0bb : 04;
0bc : 03;
0bd : 02;
0be : 01;
0bf : 00;
0c0 : 0F;
0c1 : 0E;
0c2 : 0D;
0c3 : 0C;
0c4 : 0B;
0c5 : 0A;
0c6 : 09;
0c7 : 08;
0c8 : 07;
0c9 : 06;
0ca : 05;
0cb : 04;
0cc : 03;
0cd : 02;
0ce : 01;
0cf : 00;
0d0 : 0F;
0d1 : 0E;
0d2 : 0D;
0d3 : 0C;
0d4 : 0B;
0d5 : 0A;
0d6 : 09;
0d7 : 08;
0d8 : 07;
0d9 : 06;
0da : 05;
0db : 04;
0dc : 03;
0dd : 02;
0de : 01;
0df : 00;
0e0 : 0F;
0e1 : 0E;
0e2 : 0D;
0e3 : 0C;
0e4 : 0B;
0e5 : 0A;
0e6 : 09;
0e7 : 08;
0e8 : 07;
0e9 : 06;
0ea : 05;
0eb : 04;
0ec : 03;
0ed : 02;
0ee : 01;
0ef : 00;
0f0 : 0F;
0f1 : 0E;
0f2 : 0D;
0f3 : 0C;
0f4 : 0B;
0f5 : 0A;
0f6 : 09;
0f7 : 08;
0f8 : 07;
0f9 : 06;
0fa : 05;
0fb : 04;
0fc : 03;
0fd : 02;
0fe : 01;
0ff : 00;
END;

675
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf Normal file
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TITLE "VIDEO MODUSE UND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nFB_BURST : INPUT;
FB_ADR[31..0] : INPUT;
CLK33M : INPUT;
CLK25M : INPUT;
BLITTER_RUN : INPUT;
CLK_VIDEO : INPUT;
VR_D[8..0] : INPUT;
VR_BUSY : INPUT;
COLOR8 : OUTPUT;
ACP_CLUT_RD : OUTPUT;
COLOR1 : OUTPUT;
FALCON_CLUT_RDH : OUTPUT;
FALCON_CLUT_RDL : OUTPUT;
FALCON_CLUT_WR[3..0] : OUTPUT;
ST_CLUT_RD : OUTPUT;
ST_CLUT_WR[1..0] : OUTPUT;
CLUT_MUX_ADR[3..0] : OUTPUT;
HSYNC : OUTPUT;
VSYNC : OUTPUT;
nBLANK : OUTPUT;
nSYNC : OUTPUT;
nPD_VGA : OUTPUT;
FIFO_RDE : OUTPUT;
COLOR2 : OUTPUT;
COLOR4 : OUTPUT;
PIXEL_CLK : OUTPUT;
CLUT_OFF[3..0] : OUTPUT;
BLITTER_ON : OUTPUT;
VIDEO_RAM_CTR[15..0] : OUTPUT;
VIDEO_MOD_TA : OUTPUT;
CCR[23..0] : OUTPUT;
CCSEL[2..0] : OUTPUT;
ACP_CLUT_WR[3..0] : OUTPUT;
INTER_ZEI : OUTPUT;
DOP_FIFO_CLR : OUTPUT;
VIDEO_RECONFIG : OUTPUT;
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
CLK17M :DFF;
CLK13M :DFF;
ACP_CLUT_CS :NODE;
ACP_CLUT :NODE;
VIDEO_PLL_CONFIG_CS :NODE;
VR_WR :DFF;
VR_DOUT[8..0] :DFFE;
VR_FRQ[7..0] :DFFE;
VIDEO_PLL_RECONFIG_CS :NODE;
VIDEO_RECONFIG :DFF;
FALCON_CLUT_CS :NODE;
FALCON_CLUT :NODE;
ST_CLUT_CS :NODE;
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
CLUT_MUX_ADR[3..0] :DFF;
CLUT_MUX_AV[1..0][3..0] :DFF;
ACP_VCTR_CS :NODE;
ACP_VCTR[31..0] :DFFE;
CCR_CS :NODE;
CCR[23..0] :DFFE;
ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE;
VDL_LOF[15..0] :DFFE;
VDL_LOF_CS :NODE;
VDL_LWD[15..0] :DFFE;
VDL_LWD_CS :NODE;
-- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF;
HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
FIFO_RDE :DFF;
CLR_FIFO :DFFE;
START_ZEILE :DFFE;
SYNC_PIX :DFF;
SYNC_PIX1 :DFF;
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
FALCON_SHIFT_MODE[] = FB_AD[26..16];
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
VR_DOUT[].CLK = MAIN_CLK;
VR_DOUT[].ENA = !VR_BUSY;
VR_DOUT[] = VR_D[];
VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
# B"100" & ACP_CLUT
# B"101" & COLOR16
# B"110" & COLOR24
# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
VDL_VMD[].CLK = MAIN_CLK;
VDL_VMD[] = FB_AD[19..16];
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
VERZ[][3] = VERZ[][2];
VERZ[][4] = VERZ[][3];
VERZ[][5] = VERZ[][4];
VERZ[][6] = VERZ[][5];
VERZ[][7] = VERZ[][6];
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9];
nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
RAND[1] = RAND[0];
RAND[2] = RAND[1];
RAND[3] = RAND[2];
RAND[4] = RAND[3];
RAND[5] = RAND[4];
RAND[6] = RAND[5];
RAND_ON = RAND[6];
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
FIFO_RDE.CLK = PIXEL_CLK;
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
END;

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FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak Normal file
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TITLE "VIDEO MODUSE UND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nFB_BURST : INPUT;
FB_ADR[31..0] : INPUT;
CLK33M : INPUT;
CLK25M : INPUT;
BLITTER_RUN : INPUT;
CLK_VIDEO : INPUT;
VR_D[8..0] : INPUT;
VR_BUSY : INPUT;
COLOR8 : OUTPUT;
ACP_CLUT_RD : OUTPUT;
COLOR1 : OUTPUT;
FALCON_CLUT_RDH : OUTPUT;
FALCON_CLUT_RDL : OUTPUT;
FALCON_CLUT_WR[3..0] : OUTPUT;
ST_CLUT_RD : OUTPUT;
ST_CLUT_WR[1..0] : OUTPUT;
CLUT_MUX_ADR[3..0] : OUTPUT;
HSYNC : OUTPUT;
VSYNC : OUTPUT;
nBLANK : OUTPUT;
nSYNC : OUTPUT;
nPD_VGA : OUTPUT;
FIFO_RDE : OUTPUT;
COLOR2 : OUTPUT;
COLOR4 : OUTPUT;
PIXEL_CLK : OUTPUT;
CLUT_OFF[3..0] : OUTPUT;
BLITTER_ON : OUTPUT;
VIDEO_RAM_CTR[15..0] : OUTPUT;
VIDEO_MOD_TA : OUTPUT;
CCR[23..0] : OUTPUT;
CCSEL[2..0] : OUTPUT;
ACP_CLUT_WR[3..0] : OUTPUT;
INTER_ZEI : OUTPUT;
DOP_FIFO_CLR : OUTPUT;
VIDEO_RECONFIG : OUTPUT;
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
CLK17M :DFF;
CLK13M :DFF;
ACP_CLUT_CS :NODE;
ACP_CLUT :NODE;
VIDEO_PLL_CONFIG_CS :NODE;
VR_WR :DFF;
VR_DOUT[8..0] :DFFE;
VR_FRQ[7..0] :DFFE;
VIDEO_PLL_RECONFIG_CS :NODE;
VIDEO_RECONFIG :DFF;
FALCON_CLUT_CS :NODE;
FALCON_CLUT :NODE;
ST_CLUT_CS :NODE;
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
CLUT_MUX_ADR[3..0] :DFF;
CLUT_MUX_AV[1..0][3..0] :DFF;
ACP_VCTR_CS :NODE;
ACP_VCTR[31..0] :DFFE;
CCR_CS :NODE;
CCR[23..0] :DFFE;
ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE;
VDL_LOF[15..0] :DFFE;
VDL_LOF_CS :NODE;
VDL_LWD[15..0] :DFFE;
VDL_LWD_CS :NODE;
-- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF;
HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
FIFO_RDE :DFF;
CLR_FIFO :DFFE;
START_ZEILE :DFFE;
SYNC_PIX :DFF;
SYNC_PIX1 :DFF;
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
FALCON_SHIFT_MODE[] = FB_AD[26..16];
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
VR_DOUT[].CLK = MAIN_CLK;
VR_DOUT[].ENA = !VR_BUSY;
VR_DOUT[] = VR_D[];
VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
# B"100" & ACP_CLUT
# B"101" & COLOR16
# B"110" & COLOR24
# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
VDL_VMD[].CLK = MAIN_CLK;
VDL_VMD[] = FB_AD[19..16];
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
VERZ[][3] = VERZ[][2];
VERZ[][4] = VERZ[][3];
VERZ[][5] = VERZ[][4];
VERZ[][6] = VERZ[][5];
VERZ[][7] = VERZ[][6];
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9];
nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
RAND[1] = RAND[0];
RAND[2] = RAND[1];
RAND[3] = RAND[2];
RAND[4] = RAND[3];
RAND[5] = RAND[4];
RAND[6] = RAND[5];
RAND_ON = RAND[6];
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==1 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
FIFO_RDE.CLK = PIXEL_CLK;
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
END;

10651
FPGA_by_Fredi/Video/Video.bdf Normal file
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File diff suppressed because it is too large Load Diff

99
FPGA_by_Fredi/Video/altddio_bidir0.bsf Normal file
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@@ -0,0 +1,99 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 240 136)
(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 120 25 132)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 88 88)(line_width 1))
)
(port
(pt 240 24)
(output)
(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
(line (pt 240 24)(pt 144 24)(line_width 3))
)
(port
(pt 240 40)
(output)
(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
(line (pt 240 40)(pt 144 40)(line_width 3))
)
(port
(pt 240 72)
(output)
(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
(line (pt 240 72)(pt 144 72)(line_width 3))
)
(port
(pt 240 56)
(bidir)
(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
(line (pt 240 56)(pt 144 56)(line_width 3))
)
(drawing
(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 90 129 102)(font "Arial" ))
(text "low" (rect 92 100 105 112)(font "Arial" ))
(line (pt 88 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 112)(line_width 1))
(line (pt 144 112)(pt 88 112)(line_width 1))
(line (pt 88 112)(pt 88 16)(line_width 1))
)
)

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_bidir0
PORT
(
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_bidir0
(
datain_h[31..0],
datain_l[31..0],
inclock,
oe,
outclock
)
RETURNS (
combout[31..0],
dataout_h[31..0],
dataout_l[31..0],
padio[31..0]
);

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
<global>
<pin name="datain_h[31..0]" direction="input" scope="external" />
<pin name="datain_l[31..0]" direction="input" scope="external" />
<pin name="inclock" direction="input" scope="external" source="clock" />
<pin name="oe" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="combout[31..0]" direction="output" scope="external" />
<pin name="dataout_h[31..0]" direction="output" scope="external" />
<pin name="dataout_l[31..0]" direction="output" scope="external" />
<pin name="padio[31..0]" direction="bidir" scope="external" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]

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-- megafunction wizard: %ALTDDIO_BIDIR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_bidir
-- ============================================================
-- File Name: altddio_bidir0.vhd
-- Megafunction Name(s):
-- altddio_bidir
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_bidir0 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altddio_bidir0;
ARCHITECTURE SYN OF altddio_bidir0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altddio_bidir
GENERIC (
extend_oe_disable : STRING;
implement_input_in_lcell : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
outclock : IN STD_LOGIC ;
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
oe : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout_h <= sub_wire0(31 DOWNTO 0);
combout <= sub_wire1(31 DOWNTO 0);
dataout_l <= sub_wire2(31 DOWNTO 0);
altddio_bidir_component : altddio_bidir
GENERIC MAP (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "ON",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 32
)
PORT MAP (
outclock => outclock,
inclock => inclock,
oe => oe,
datain_h => datain_h,
datain_l => datain_l,
dataout_h => sub_wire0,
combout => sub_wire1,
dataout_l => sub_wire2,
padio => padio
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "1"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

64
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "high" (rect 92 84 109 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

24
FPGA_by_Fredi/Video/altddio_out0.cmp Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out0
PORT
(
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;

25
FPGA_by_Fredi/Video/altddio_out0.inc Normal file
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@@ -0,0 +1,25 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out0
(
datain_h[3..0],
datain_l[3..0],
outclock
)
RETURNS (
dataout[3..0]
);

11
FPGA_by_Fredi/Video/altddio_out0.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[3..0]" direction="input" scope="external" />
<pin name="datain_l[3..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[3..0]" direction="output" scope="external" />
</global>
</pinplan>

7
FPGA_by_Fredi/Video/altddio_out0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out0.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out0 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END altddio_out0;
ARCHITECTURE SYN OF altddio_out0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(3 DOWNTO 0);
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "ON",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "ON",
width => 4
)
PORT MAP (
outclock => outclock,
datain_h => datain_h,
datain_l => datain_l,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out1
PORT
(
datain_h : IN STD_LOGIC ;
datain_l : IN STD_LOGIC ;
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC
);
end component;

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out1
(
datain_h,
datain_l,
outclock
)
RETURNS (
dataout
);

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h" direction="input" scope="external" />
<pin name="datain_l" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout" direction="output" scope="external" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out1.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out1 IS
PORT
(
datain_h : IN STD_LOGIC ;
datain_l : IN STD_LOGIC ;
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC
);
END altddio_out1;
ARCHITECTURE SYN OF altddio_out1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
dataout <= sub_wire1;
sub_wire2 <= datain_h;
sub_wire3(0) <= sub_wire2;
sub_wire4 <= datain_l;
sub_wire5(0) <= sub_wire4;
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
)
PORT MAP (
outclock => outclock,
datain_h => sub_wire3,
datain_l => sub_wire5,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

24
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out2
PORT
(
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
end component;

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out2
(
datain_h[23..0],
datain_l[23..0],
outclock
)
RETURNS (
dataout[23..0]
);

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[23..0]" direction="input" scope="external" />
<pin name="datain_l[23..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[23..0]" direction="output" scope="external" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out2.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out2 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END altddio_out2;
ARCHITECTURE SYN OF altddio_out2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(23 DOWNTO 0);
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 24
)
PORT MAP (
outclock => outclock,
datain_h => datain_h,
datain_l => datain_l,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
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(line (pt 256 96)(pt 192 96)(line_width 3))
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(drawing
(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
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30
FPGA_by_Fredi/Video/altdpram0.cmp Normal file
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@@ -0,0 +1,30 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram0
PORT
(
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;

31
FPGA_by_Fredi/Video/altdpram0.inc Normal file
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@@ -0,0 +1,31 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram0
(
address_a[3..0],
address_b[3..0],
clock_a,
clock_b,
data_a[2..0],
data_b[2..0],
wren_a,
wren_b
)
RETURNS (
q_a[2..0],
q_b[2..0]
);

6
FPGA_by_Fredi/Video/altdpram0.qip Normal file
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@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"]

273
FPGA_by_Fredi/Video/altdpram0.vhd Normal file
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@@ -0,0 +1,273 @@
-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram0 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END altdpram0;
ARCHITECTURE SYN OF altdpram0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(2 DOWNTO 0);
q_b <= sub_wire1(2 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 16,
numwords_b => 16,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 4,
widthad_b => 4,
width_a => 3,
width_b => 3,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0]
-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0]
-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0]
-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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FPGA_by_Fredi/Video/altdpram0_waveforms.html Normal file
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<html>
<head>
<title>Sample Waveforms for altdpram0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/altdpram1.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[5..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[5..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 144)(line_width 1))
(line (pt 168 144)(pt 128 144)(line_width 1))
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)
)

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FPGA_by_Fredi/Video/altdpram1.cmp Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram1
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;

31
FPGA_by_Fredi/Video/altdpram1.inc Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram1
(
address_a[7..0],
address_b[7..0],
clock_a,
clock_b,
data_a[5..0],
data_b[5..0],
wren_a,
wren_b
)
RETURNS (
q_a[5..0],
q_b[5..0]
);

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FPGA_by_Fredi/Video/altdpram1.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"]

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FPGA_by_Fredi/Video/altdpram1.vhd Normal file
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-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram1 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END altdpram1;
ARCHITECTURE SYN OF altdpram1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(5 DOWNTO 0);
q_b <= sub_wire1(5 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 8,
widthad_b => 8,
width_a => 6,
width_b => 6,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0]
-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0]
-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0]
-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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<html>
<head>
<title>Sample Waveforms for altdpram1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 144)(line_width 1))
(line (pt 168 144)(pt 128 144)(line_width 1))
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)
)

30
FPGA_by_Fredi/Video/altdpram2.cmp Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram2
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

31
FPGA_by_Fredi/Video/altdpram2.inc Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram2
(
address_a[7..0],
address_b[7..0],
clock_a,
clock_b,
data_a[7..0],
data_b[7..0],
wren_a,
wren_b
)
RETURNS (
q_a[7..0],
q_b[7..0]
);

6
FPGA_by_Fredi/Video/altdpram2.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"]

273
FPGA_by_Fredi/Video/altdpram2.vhd Normal file
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-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram2 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END altdpram2;
ARCHITECTURE SYN OF altdpram2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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<html>
<head>
<title>Sample Waveforms for altdpram2.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "32" (rect 61 25 71 37)(font "Arial" ))
(text "32" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

23
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri0
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

24
FPGA_by_Fredi/Video/lpm_bustri0.inc Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_bustri0
(
data[31..0],
enabledt
)
RETURNS (
tridata[31..0]
);

6
FPGA_by_Fredi/Video/lpm_bustri0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri0.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri0 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_bustri0;
ARCHITECTURE SYN OF lpm_bustri0 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 32
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
FPGA_by_Fredi/Video/lpm_bustri1.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "3" (rect 63 25 68 37)(font "Arial" ))
(text "3" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/lpm_bustri1.cmp Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri1
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;

5
FPGA_by_Fredi/Video/lpm_bustri1.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"]

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FPGA_by_Fredi/Video/lpm_bustri1.vhd Normal file
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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri1.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri1 IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END lpm_bustri1;
ARCHITECTURE SYN OF lpm_bustri1 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 3
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0]
-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
FPGA_by_Fredi/Video/lpm_bustri2.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "18" (rect 61 25 71 37)(font "Arial" ))
(text "18" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/lpm_bustri2.cmp Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri2
PORT
(
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component;

5
FPGA_by_Fredi/Video/lpm_bustri2.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"]

107
FPGA_by_Fredi/Video/lpm_bustri2.vhd Normal file
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@@ -0,0 +1,107 @@
-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri2.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri2 IS
PORT
(
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END lpm_bustri2;
ARCHITECTURE SYN OF lpm_bustri2 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 18
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "18"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0]
-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0
-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
FPGA_by_Fredi/Video/lpm_bustri3.bsf Normal file
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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "6" (rect 63 25 68 37)(font "Arial" ))
(text "6" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/lpm_bustri3.cmp Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri3
PORT
(
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;

5
FPGA_by_Fredi/Video/lpm_bustri3.qip Normal file
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@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"]

107
FPGA_by_Fredi/Video/lpm_bustri3.vhd Normal file
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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri3.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri3 IS
PORT
(
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_bustri3;
ARCHITECTURE SYN OF lpm_bustri3 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 6
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0]
-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0
-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
FPGA_by_Fredi/Video/lpm_bustri4.bsf Normal file
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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "5" (rect 63 25 68 37)(font "Arial" ))
(text "5" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/lpm_bustri4.cmp Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri4
PORT
(
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component;

5
FPGA_by_Fredi/Video/lpm_bustri4.qip Normal file
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@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"]

107
FPGA_by_Fredi/Video/lpm_bustri4.vhd Normal file
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@@ -0,0 +1,107 @@
-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri4.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri4 IS
PORT
(
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_bustri4;
ARCHITECTURE SYN OF lpm_bustri4 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 5
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0]
-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
FPGA_by_Fredi/Video/lpm_bustri5.bsf Normal file
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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "8" (rect 63 25 68 37)(font "Arial" ))
(text "8" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/lpm_bustri5.cmp Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri5
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

24
FPGA_by_Fredi/Video/lpm_bustri5.inc Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_bustri5
(
data[7..0],
enabledt
)
RETURNS (
tridata[7..0]
);

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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri5.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri5 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_bustri5;
ARCHITECTURE SYN OF lpm_bustri5 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 8
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "24" (rect 61 25 71 37)(font "Arial" ))
(text "24" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

23
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri6
PORT
(
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
end component;

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FPGA_by_Fredi/Video/lpm_bustri6.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri6.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END lpm_bustri6;
ARCHITECTURE SYN OF lpm_bustri6 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 24
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0]
-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0
-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "4" (rect 63 25 68 37)(font "Arial" ))
(text "4" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri7
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;

5
FPGA_by_Fredi/Video/lpm_bustri7.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri7.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_bustri7;
ARCHITECTURE SYN OF lpm_bustri7 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 4
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0]
-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

54
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 128 96)
(text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 48)
(input)
(text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 128 56)
(output)
(text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8)))
(line (pt 128 56)(pt 112 56)(line_width 1))
)
(drawing
(text "unsigned compare" (rect 36 17 112 29)(font "Arial" ))
(line (pt 16 16)(pt 112 16)(line_width 1))
(line (pt 112 16)(pt 112 80)(line_width 1))
(line (pt 112 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_compare1
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
end component;

24
FPGA_by_Fredi/Video/lpm_compare1.inc Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_compare1
(
dataa[10..0],
datab[10..0]
)
RETURNS (
AgB
);

6
FPGA_by_Fredi/Video/lpm_compare1.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"]

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-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AgB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 11
)
PORT MAP (
dataa => dataa,
datab => datab,
AgB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0]
-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0]
-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm

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FPGA_by_Fredi/Video/lpm_compare1_waveforms.html Normal file
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<html>
<head>
<title>Sample Waveforms for lpm_compare1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

42
FPGA_by_Fredi/Video/lpm_constant0.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "5" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

21
FPGA_by_Fredi/Video/lpm_constant0.cmp Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_constant0
PORT
(
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component;

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