forked from Firebee/FPGA_Config
First full HDL version
This commit is contained in:
torlus
David Gálvez
662
FPGA_by_Gregory_Estrade/ahdl2v/DDR_CTR.tdf
Normal file
662
FPGA_by_Gregory_Estrade/ahdl2v/DDR_CTR.tdf
Normal file
@@ -0,0 +1,662 @@
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TITLE "DDR_CTR";
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-- CREATED BY FREDI ASCHWANDEN
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INCLUDE "lpm_bustri_BYT.inc";
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-- FIFO WATER MARK
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CONSTANT FIFO_LWM = 0;
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CONSTANT FIFO_MWM = 200;
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CONSTANT FIFO_HWM = 500;
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-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
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SUBDESIGN DDR_CTR
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(
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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FB_ADR[31..0] : INPUT;
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nFB_CS1 : INPUT;
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nFB_CS2 : INPUT;
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nFB_CS3 : INPUT;
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nFB_OE : INPUT;
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FB_SIZE0 : INPUT;
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FB_SIZE1 : INPUT;
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nRSTO : INPUT;
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MAIN_CLK : INPUT;
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FB_ALE : INPUT;
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nFB_WR : INPUT;
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DDR_SYNC_66M : INPUT;
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CLR_FIFO : INPUT;
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VIDEO_RAM_CTR[15..0] : INPUT;
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BLITTER_ADR[31..0] : INPUT;
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BLITTER_SIG : INPUT;
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BLITTER_WR : INPUT;
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DDRCLK0 : INPUT;
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CLK33M : INPUT;
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FIFO_MW[8..0] : INPUT;
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VA[12..0] : OUTPUT;
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nVWE : OUTPUT;
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nVRAS : OUTPUT;
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nVCS : OUTPUT;
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VCKE : OUTPUT;
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nVCAS : OUTPUT;
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FB_LE[3..0] : OUTPUT;
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FB_VDOE[3..0] : OUTPUT;
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SR_FIFO_WRE : OUTPUT;
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SR_DDR_FB : OUTPUT;
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SR_DDR_WR : OUTPUT;
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SR_DDRWR_D_SEL : OUTPUT;
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SR_VDMP[7..0] : OUTPUT;
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VIDEO_DDR_TA : OUTPUT;
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SR_BLITTER_DACK : OUTPUT;
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BA[1..0] : OUTPUT;
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DDRWR_D_SEL1 : OUTPUT;
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VDM_SEL[3..0] : OUTPUT;
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FB_AD[31..0] : BIDIR;
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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)
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VARIABLE
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FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
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DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
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DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
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DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
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DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
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DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
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DS_CB6, DS_CB8, -- CLOSE FIFO BANK
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DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
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LINE :NODE;
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FB_B[3..0] :NODE;
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VCAS :NODE;
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VRAS :NODE;
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VWE :NODE;
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VA_P[12..0] :DFF;
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BA_P[1..0] :DFF;
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VA_S[12..0] :DFF;
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BA_S[1..0] :DFF;
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MCS[1..0] :DFF;
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CPU_DDR_SYNC :DFF;
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DDR_SEL :NODE;
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DDR_CS :DFFE;
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DDR_CONFIG :NODE;
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SR_DDR_WR :DFF;
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SR_DDRWR_D_SEL :DFF;
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SR_VDMP[7..0] :DFF;
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CPU_ROW_ADR[12..0] :NODE;
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CPU_BA[1..0] :NODE;
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CPU_COL_ADR[9..0] :NODE;
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CPU_SIG :NODE;
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CPU_REQ :DFF;
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CPU_AC :DFF;
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BUS_CYC :DFF;
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BUS_CYC_END :NODE;
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BLITTER_REQ :DFF;
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BLITTER_AC :DFF;
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BLITTER_ROW_ADR[12..0] :NODE;
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BLITTER_BA[1..0] :NODE;
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BLITTER_COL_ADR[9..0] :NODE;
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FIFO_REQ :DFF;
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FIFO_AC :DFF;
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FIFO_ROW_ADR[12..0] :NODE;
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FIFO_BA[1..0] :NODE;
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FIFO_COL_ADR[9..0] :NODE;
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FIFO_ACTIVE :NODE;
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CLR_FIFO_SYNC :DFF;
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CLEAR_FIFO_CNT :DFF;
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STOP :DFF;
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SR_FIFO_WRE :DFF;
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FIFO_BANK_OK :DFF;
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FIFO_BANK_NOT_OK :NODE;
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DDR_REFRESH_ON :NODE;
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DDR_REFRESH_CNT[10..0] :DFF;
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DDR_REFRESH_REQ :DFF;
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DDR_REFRESH_SIG[3..0] :DFFE;
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REFRESH_TIME :DFF;
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VIDEO_BASE_L_D[7..0] :DFFE;
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VIDEO_BASE_L :NODE;
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VIDEO_BASE_M_D[7..0] :DFFE;
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VIDEO_BASE_M :NODE;
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VIDEO_BASE_H_D[7..0] :DFFE;
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VIDEO_BASE_H :NODE;
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VIDEO_BASE_X_D[2..0] :DFFE;
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VIDEO_BASE_X_D_FULL[7..0] :NODE;
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VIDEO_ADR_CNT[22..0] :DFFE;
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VIDEO_CNT_L :NODE;
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VIDEO_CNT_M :NODE;
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VIDEO_CNT_H :NODE;
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VIDEO_BASE_ADR[22..0] :NODE;
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VIDEO_ACT_ADR[26..0] :NODE;
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BEGIN
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LINE = FB_SIZE0 & FB_SIZE1;
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-- BYT SELECT
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FB_B0 = FB_ADR[1..0]==0 -- ADR==0
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B1 = FB_ADR[1..0]==1 -- ADR==1
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# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B2 = FB_ADR[1..0]==2 -- ADR==2
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B3 = FB_ADR[1..0]==3 -- ADR==3
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# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
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FB_REGDDR.CLK = MAIN_CLK;
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CASE FB_REGDDR IS
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WHEN FR_WAIT =>
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FB_LE0 = !nFB_WR;
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IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
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FB_REGDDR = FR_S0;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S0 =>
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IF DDR_CS THEN
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FB_LE0 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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IF LINE THEN
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FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
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FB_REGDDR = FR_S1;
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ELSE
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BUS_CYC_END = VCC;
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FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
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FB_REGDDR = FR_WAIT;
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END IF;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S1 =>
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IF DDR_CS THEN
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FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
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FB_LE1 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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FB_REGDDR = FR_S2;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S2 =>
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IF DDR_CS THEN
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FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
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FB_LE2 = !nFB_WR;
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IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
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FB_REGDDR = FR_S2;
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ELSE
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VIDEO_DDR_TA = VCC;
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FB_REGDDR = FR_S3;
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END IF;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S3 =>
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IF DDR_CS THEN
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FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
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FB_LE3 = !nFB_WR;
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VIDEO_DDR_TA = VCC;
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BUS_CYC_END = VCC;
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FB_REGDDR = FR_WAIT;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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END CASE;
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-- DDR STEUERUNG -----------------------------------------------------
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-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
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VCKE = VIDEO_RAM_CTR0;
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nVCS = !VIDEO_RAM_CTR1;
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DDR_REFRESH_ON = VIDEO_RAM_CTR2;
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DDR_CONFIG = VIDEO_RAM_CTR3;
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FIFO_ACTIVE = VIDEO_RAM_CTR8;
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--------------------------------
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CPU_ROW_ADR[] = FB_ADR[26..14];
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CPU_BA[] = FB_ADR[13..12];
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CPU_COL_ADR[] = FB_ADR[11..2];
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nVRAS = !VRAS;
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nVCAS = !VCAS;
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nVWE = !VWE;
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SR_DDR_WR.CLK = DDRCLK0;
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SR_DDRWR_D_SEL.CLK = DDRCLK0;
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SR_VDMP[7..0].CLK = DDRCLK0;
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SR_FIFO_WRE.CLK = DDRCLK0;
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CPU_AC.CLK = DDRCLK0;
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FIFO_AC.CLK = DDRCLK0;
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BLITTER_AC.CLK = DDRCLK0;
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DDRWR_D_SEL1 = BLITTER_AC;
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-- SELECT LOGIC
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DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
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DDR_CS.CLK = MAIN_CLK;
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DDR_CS.ENA = FB_ALE;
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DDR_CS = DDR_SEL;
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-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
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CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
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# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
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# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
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CPU_REQ.CLK = DDR_SYNC_66M;
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CPU_REQ = CPU_SIG
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# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
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BUS_CYC.CLK = DDRCLK0;
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BUS_CYC = BUS_CYC & !BUS_CYC_END;
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-- STATE MACHINE SYNCHRONISIEREN -----------------
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MCS[].CLK = DDRCLK0;
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MCS0 = MAIN_CLK;
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MCS1 = MCS0;
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CPU_DDR_SYNC.CLK = DDRCLK0;
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CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
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---------------------------------------------------
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VA_S[].CLK = DDRCLK0;
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BA_S[].CLK = DDRCLK0;
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VA[] = VA_S[];
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BA[] = BA_S[];
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VA_P[].CLK = DDRCLK0;
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BA_P[].CLK = DDRCLK0;
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-- DDR STATE MACHINE -----------------------------------------------
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DDR_SM.CLK = DDRCLK0;
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CASE DDR_SM IS
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WHEN DS_T1 =>
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IF DDR_REFRESH_REQ THEN
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DDR_SM = DS_R2;
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ELSE
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IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
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IF DDR_CONFIG THEN -- JA
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DDR_SM = DS_C2;
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ELSE
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IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
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VA_S[] = CPU_ROW_ADR[];
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BA_S[] = CPU_BA[];
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CPU_AC = VCC;
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BUS_CYC = VCC;
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DDR_SM = DS_T2B;
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ELSE
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IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
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VA_P[] = FIFO_ROW_ADR[];
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BA_P[] = FIFO_BA[];
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FIFO_AC = VCC; -- VORBESETZEN
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ELSE
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VA_P[] = BLITTER_ROW_ADR[];
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BA_P[] = BLITTER_BA[];
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BLITTER_AC = VCC; -- VORBESETZEN
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END IF;
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DDR_SM = DS_T2A;
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END IF;
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END IF;
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ELSE
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DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
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END IF;
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END IF;
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WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
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IF DDR_SEL & (nFB_WR # !LINE) THEN
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VRAS = VCC;
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VA[] = FB_AD[26..14];
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BA[] = FB_AD[13..12];
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VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
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CPU_AC = VCC;
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BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
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ELSE
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VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
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VA[] = VA_P[];
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BA[] = BA_P[];
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VA_S[10] = !(FIFO_AC & FIFO_REQ);
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FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
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FIFO_AC = FIFO_AC & FIFO_REQ;
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BLITTER_AC = BLITTER_AC & BLITTER_REQ;
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END IF;
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DDR_SM = DS_T3;
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WHEN DS_T2B =>
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VRAS = VCC;
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FIFO_BANK_NOT_OK = VCC;
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CPU_AC = VCC;
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BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
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DDR_SM = DS_T3;
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WHEN DS_T3 =>
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CPU_AC = CPU_AC;
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FIFO_AC = FIFO_AC;
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BLITTER_AC = BLITTER_AC;
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
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IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
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DDR_SM = DS_T4W;
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ELSE
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IF CPU_AC THEN -- CPU?
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VA_S[9..0] = CPU_COL_ADR[];
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BA_S[] = CPU_BA[];
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DDR_SM = DS_T4R;
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ELSE
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IF FIFO_AC THEN -- FIFO?
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VA_S[9..0] = FIFO_COL_ADR[];
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BA_S[] = FIFO_BA[];
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DDR_SM = DS_T4F;
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ELSE
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IF BLITTER_AC THEN
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VA_S[9..0] = BLITTER_COL_ADR[];
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BA_S[] = BLITTER_BA[];
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DDR_SM = DS_T4R;
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ELSE
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DDR_SM = DS_N8;
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END IF;
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||||
END IF;
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END IF;
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END IF;
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-- READ
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WHEN DS_T4R =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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VCAS = VCC;
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SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
|
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SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
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DDR_SM = DS_T5R;
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WHEN DS_T5R =>
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CPU_AC = CPU_AC;
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BLITTER_AC = BLITTER_AC;
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IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
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VA_S[9..0] = FIFO_COL_ADR[];
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VA_S[10] = GND; -- MANUEL PRECHARGE
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BA_S[] = FIFO_BA[];
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DDR_SM = DS_T6F;
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ELSE
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VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
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DDR_SM = DS_CB6;
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END IF;
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-- WRITE
|
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WHEN DS_T4W =>
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||||
CPU_AC = CPU_AC;
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||||
BLITTER_AC = BLITTER_AC;
|
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SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
|
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
|
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DDR_SM = DS_T5W;
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||||
|
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WHEN DS_T5W =>
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CPU_AC = CPU_AC;
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||||
BLITTER_AC = BLITTER_AC;
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VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
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# BLITTER_AC & BLITTER_COL_ADR[];
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VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
|
||||
BA_S[] = CPU_AC & CPU_BA[]
|
||||
# BLITTER_AC & BLITTER_BA[];
|
||||
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
|
||||
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
|
||||
DDR_SM = DS_T6W;
|
||||
|
||||
WHEN DS_T6W =>
|
||||
CPU_AC = CPU_AC;
|
||||
BLITTER_AC = BLITTER_AC;
|
||||
VCAS = VCC;
|
||||
VWE = VCC;
|
||||
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
|
||||
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
|
||||
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
|
||||
DDR_SM = DS_T7W;
|
||||
|
||||
WHEN DS_T7W =>
|
||||
CPU_AC = CPU_AC;
|
||||
BLITTER_AC = BLITTER_AC;
|
||||
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
|
||||
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
|
||||
DDR_SM = DS_T8W;
|
||||
|
||||
WHEN DS_T8W =>
|
||||
DDR_SM = DS_T9W;
|
||||
|
||||
WHEN DS_T9W =>
|
||||
IF FIFO_REQ & FIFO_BANK_OK THEN
|
||||
VA_S[9..0] = FIFO_COL_ADR[];
|
||||
VA_S[10] = GND; -- NON AUTO PRECHARGE
|
||||
BA_S[] = FIFO_BA[];
|
||||
DDR_SM = DS_T6F;
|
||||
ELSE
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||||
DDR_SM = DS_CB6;
|
||||
END IF;
|
||||
-- FIFO READ
|
||||
WHEN DS_T4F =>
|
||||
VCAS = VCC;
|
||||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||||
DDR_SM = DS_T5F;
|
||||
|
||||
WHEN DS_T5F =>
|
||||
IF FIFO_REQ THEN
|
||||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||||
ELSE
|
||||
VA_S[9..0] = FIFO_COL_ADR[]+4;
|
||||
VA_S[10] = GND; -- NON AUTO PRECHARGE
|
||||
BA_S[] = FIFO_BA[];
|
||||
DDR_SM = DS_T6F;
|
||||
END IF;
|
||||
ELSE
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||||
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
|
||||
END IF;
|
||||
|
||||
WHEN DS_T6F =>
|
||||
VCAS = VCC;
|
||||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||||
DDR_SM = DS_T7F;
|
||||
|
||||
WHEN DS_T7F =>
|
||||
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
|
||||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||||
ELSE
|
||||
IF FIFO_REQ THEN
|
||||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
|
||||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||||
ELSE
|
||||
VA_S[9..0] = FIFO_COL_ADR[]+4;
|
||||
VA_S[10] = GND; -- NON AUTO PRECHARGE
|
||||
BA_S[] = FIFO_BA[];
|
||||
DDR_SM = DS_T8F;
|
||||
END IF;
|
||||
ELSE
|
||||
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
|
||||
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
WHEN DS_T8F =>
|
||||
VCAS = VCC;
|
||||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||||
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
|
||||
DDR_SM = DS_T5F; -- JA->
|
||||
ELSE
|
||||
DDR_SM = DS_T9F;
|
||||
END IF;
|
||||
|
||||
WHEN DS_T9F =>
|
||||
IF FIFO_REQ THEN
|
||||
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
|
||||
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
|
||||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||||
ELSE
|
||||
VA_P[9..0] = FIFO_COL_ADR[]+4;
|
||||
VA_P[10] = GND; -- NON AUTO PRECHARGE
|
||||
BA_P[] = FIFO_BA[];
|
||||
DDR_SM = DS_T10F;
|
||||
END IF;
|
||||
ELSE
|
||||
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
|
||||
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
|
||||
END IF;
|
||||
|
||||
WHEN DS_T10F =>
|
||||
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
|
||||
VRAS = VCC;
|
||||
VA[] = FB_AD[26..14];
|
||||
BA[] = FB_AD[13..12];
|
||||
CPU_AC = VCC;
|
||||
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
|
||||
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
|
||||
DDR_SM = DS_T3;
|
||||
ELSE
|
||||
VCAS = VCC;
|
||||
VA[] = VA_P[];
|
||||
BA[] = BA_P[];
|
||||
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
|
||||
DDR_SM = DS_T7F;
|
||||
END IF;
|
||||
|
||||
-- CONFIG CYCLUS
|
||||
WHEN DS_C2 =>
|
||||
DDR_SM = DS_C3;
|
||||
WHEN DS_C3 =>
|
||||
BUS_CYC = CPU_REQ;
|
||||
DDR_SM = DS_C4;
|
||||
WHEN DS_C4 =>
|
||||
IF CPU_REQ THEN
|
||||
DDR_SM = DS_C5;
|
||||
ELSE
|
||||
DDR_SM = DS_T1;
|
||||
END IF;
|
||||
WHEN DS_C5 =>
|
||||
DDR_SM = DS_C6;
|
||||
WHEN DS_C6 =>
|
||||
VA_S[] = FB_AD[12..0];
|
||||
BA_S[] = FB_AD[14..13];
|
||||
DDR_SM = DS_C7;
|
||||
WHEN DS_C7 =>
|
||||
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||||
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||||
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
|
||||
DDR_SM = DS_N8;
|
||||
-- CLOSE FIFO BANK
|
||||
WHEN DS_CB6 =>
|
||||
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
|
||||
VRAS = VCC; -- B<>NKE SCHLIESSEN
|
||||
VWE = VCC;
|
||||
DDR_SM = DS_N7;
|
||||
WHEN DS_CB8 =>
|
||||
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
|
||||
VRAS = VCC; -- B<>NKE SCHLIESSEN
|
||||
VWE = VCC;
|
||||
DDR_SM = DS_T1;
|
||||
-- REFRESH 70NS = 10 ZYCLEN
|
||||
WHEN DS_R2 =>
|
||||
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
|
||||
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
|
||||
VWE = VCC;
|
||||
VA[10] = VCC;
|
||||
FIFO_BANK_NOT_OK = VCC;
|
||||
DDR_SM = DS_R4;
|
||||
ELSE
|
||||
VCAS = VCC;
|
||||
VRAS = VCC;
|
||||
DDR_SM = DS_R3;
|
||||
END IF;
|
||||
WHEN DS_R3 =>
|
||||
DDR_SM = DS_R4;
|
||||
WHEN DS_R4 =>
|
||||
DDR_SM = DS_R5;
|
||||
WHEN DS_R5 =>
|
||||
DDR_SM = DS_R6;
|
||||
WHEN DS_R6 =>
|
||||
DDR_SM = DS_N5;
|
||||
-- LEERSCHLAUFE
|
||||
WHEN DS_N5 =>
|
||||
DDR_SM = DS_N6;
|
||||
WHEN DS_N6 =>
|
||||
DDR_SM = DS_N7;
|
||||
WHEN DS_N7 =>
|
||||
DDR_SM = DS_N8;
|
||||
WHEN DS_N8 =>
|
||||
DDR_SM = DS_T1;
|
||||
END CASE;
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- BLITTER ----------------------
|
||||
-----------------------------------------
|
||||
BLITTER_REQ.CLK = DDRCLK0;
|
||||
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
|
||||
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
|
||||
BLITTER_BA1 = BLITTER_ADR13;
|
||||
BLITTER_BA0 = BLITTER_ADR12;
|
||||
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
|
||||
------------------------------------------------------------------------------
|
||||
-- FIFO ---------------------------------
|
||||
--------------------------------------------------------
|
||||
FIFO_REQ.CLK = DDRCLK0;
|
||||
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
|
||||
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
|
||||
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
|
||||
FIFO_BA1 = VIDEO_ADR_CNT9;
|
||||
FIFO_BA0 = VIDEO_ADR_CNT8;
|
||||
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
|
||||
FIFO_BANK_OK.CLK = DDRCLK0;
|
||||
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
|
||||
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
|
||||
CLR_FIFO_SYNC.CLK =DDRCLK0;
|
||||
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
|
||||
CLEAR_FIFO_CNT.CLK = DDRCLK0;
|
||||
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
|
||||
STOP.CLK = DDRCLK0;
|
||||
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
|
||||
-- Z<>HLEN -----------------------------------------------
|
||||
VIDEO_ADR_CNT[].CLK = DDRCLK0;
|
||||
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
|
||||
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
|
||||
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
|
||||
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
|
||||
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
|
||||
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
|
||||
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
|
||||
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
|
||||
-- AKTUELLE VIDEO ADRESSE
|
||||
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
|
||||
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
|
||||
-----------------------------------------------------------------------------------------
|
||||
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
|
||||
-----------------------------------------------------------------------------------------
|
||||
DDR_REFRESH_CNT[].CLK = CLK33M;
|
||||
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
|
||||
REFRESH_TIME.CLK = DDRCLK0;
|
||||
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
|
||||
DDR_REFRESH_SIG[].CLK = DDRCLK0;
|
||||
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
|
||||
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
|
||||
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
|
||||
DDR_REFRESH_REQ.CLK = DDRCLK0;
|
||||
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
|
||||
-----------------------------------------------------------
|
||||
-- VIDEO REGISTER -----------------------
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
|
||||
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
|
||||
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
|
||||
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
|
||||
|
||||
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
|
||||
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
|
||||
VIDEO_BASE_M_D[] = FB_AD[23..16];
|
||||
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
|
||||
|
||||
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
|
||||
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
|
||||
VIDEO_BASE_H_D[] = FB_AD[23..16];
|
||||
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
|
||||
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
|
||||
VIDEO_BASE_X_D[] = FB_AD[26..24];
|
||||
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
|
||||
|
||||
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
|
||||
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
|
||||
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
|
||||
|
||||
VIDEO_BASE_X_D_FULL[] = (0,VIDEO_BASE_X_D[]); -- GE
|
||||
|
||||
FB_AD[31..24] = lpm_bustri_BYT(
|
||||
VIDEO_BASE_H & VIDEO_BASE_X_D_FULL[]
|
||||
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
|
||||
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
|
||||
|
||||
FB_AD[23..16] = lpm_bustri_BYT(
|
||||
VIDEO_BASE_L & VIDEO_BASE_L_D[]
|
||||
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
|
||||
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
|
||||
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
|
||||
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
|
||||
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
|
||||
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
|
||||
END;
|
||||
|
||||
1095
FPGA_by_Gregory_Estrade/ahdl2v/DDR_CTR.v
Normal file
1095
FPGA_by_Gregory_Estrade/ahdl2v/DDR_CTR.v
Normal file
File diff suppressed because it is too large
Load Diff
684
FPGA_by_Gregory_Estrade/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf
Normal file
684
FPGA_by_Gregory_Estrade/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf
Normal file
@@ -0,0 +1,684 @@
|
||||
TITLE "VIDEO MODUSE UND CLUT CONTROL";
|
||||
|
||||
-- CREATED BY FREDI ASCHWANDEN
|
||||
|
||||
-- GE http://quartushelp.altera.com/current/mergedProjects/hdl/ahdl/ahdl_elements_arithmetic_operators.htm
|
||||
|
||||
INCLUDE "lpm_bustri_WORD.inc";
|
||||
INCLUDE "lpm_bustri_BYT.inc";
|
||||
|
||||
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
|
||||
|
||||
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
|
||||
(
|
||||
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
nRSTO : INPUT;
|
||||
MAIN_CLK : INPUT;
|
||||
nFB_CS1 : INPUT;
|
||||
nFB_CS2 : INPUT;
|
||||
nFB_CS3 : INPUT;
|
||||
nFB_WR : INPUT;
|
||||
nFB_OE : INPUT;
|
||||
FB_SIZE0 : INPUT;
|
||||
FB_SIZE1 : INPUT;
|
||||
nFB_BURST : INPUT;
|
||||
FB_ADR[31..0] : INPUT;
|
||||
CLK33M : INPUT;
|
||||
CLK25M : INPUT;
|
||||
BLITTER_RUN : INPUT;
|
||||
CLK_VIDEO : INPUT;
|
||||
VR_D[8..0] : INPUT;
|
||||
VR_BUSY : INPUT;
|
||||
COLOR8 : OUTPUT;
|
||||
ACP_CLUT_RD : OUTPUT;
|
||||
COLOR1 : OUTPUT;
|
||||
FALCON_CLUT_RDH : OUTPUT;
|
||||
FALCON_CLUT_RDL : OUTPUT;
|
||||
FALCON_CLUT_WR[3..0] : OUTPUT;
|
||||
ST_CLUT_RD : OUTPUT;
|
||||
ST_CLUT_WR[1..0] : OUTPUT;
|
||||
CLUT_MUX_ADR[3..0] : OUTPUT;
|
||||
HSYNC : OUTPUT;
|
||||
VSYNC : OUTPUT;
|
||||
nBLANK : OUTPUT;
|
||||
nSYNC : OUTPUT;
|
||||
nPD_VGA : OUTPUT;
|
||||
FIFO_RDE : OUTPUT;
|
||||
COLOR2 : OUTPUT;
|
||||
COLOR4 : OUTPUT;
|
||||
PIXEL_CLK : OUTPUT;
|
||||
CLUT_OFF[3..0] : OUTPUT;
|
||||
BLITTER_ON : OUTPUT;
|
||||
VIDEO_RAM_CTR[15..0] : OUTPUT;
|
||||
VIDEO_MOD_TA : OUTPUT;
|
||||
CCR[23..0] : OUTPUT;
|
||||
CCSEL[2..0] : OUTPUT;
|
||||
ACP_CLUT_WR[3..0] : OUTPUT;
|
||||
INTER_ZEI : OUTPUT;
|
||||
DOP_FIFO_CLR : OUTPUT;
|
||||
VIDEO_RECONFIG : OUTPUT;
|
||||
VR_WR : OUTPUT;
|
||||
VR_RD : OUTPUT;
|
||||
CLR_FIFO : OUTPUT;
|
||||
FB_AD[31..0] : BIDIR;
|
||||
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
CLK17M :DFF;
|
||||
CLK13M :DFF;
|
||||
ACP_CLUT_CS :NODE;
|
||||
ACP_CLUT :NODE;
|
||||
VIDEO_PLL_CONFIG_CS :NODE;
|
||||
VR_WR :DFF;
|
||||
VR_DOUT[8..0] :DFFE;
|
||||
VR_FRQ[7..0] :DFFE;
|
||||
VIDEO_PLL_RECONFIG_CS :NODE;
|
||||
VIDEO_RECONFIG :DFF;
|
||||
FALCON_CLUT_CS :NODE;
|
||||
FALCON_CLUT :NODE;
|
||||
ST_CLUT_CS :NODE;
|
||||
ST_CLUT :NODE;
|
||||
FB_B[3..0] :NODE;
|
||||
FB_16B[1..0] :NODE;
|
||||
ST_SHIFT_MODE[1..0] :DFFE;
|
||||
ST_SHIFT_MODE_CS :NODE;
|
||||
FALCON_SHIFT_MODE[10..0] :DFFE;
|
||||
FALCON_SHIFT_MODE_CS :NODE;
|
||||
CLUT_MUX_ADR[3..0] :DFF;
|
||||
CLUT_MUX_AV[1..0][3..0] :DFF;
|
||||
ACP_VCTR_CS :NODE;
|
||||
ACP_VCTR[31..0] :DFFE;
|
||||
CCR_CS :NODE;
|
||||
CCR[23..0] :DFFE;
|
||||
ACP_VIDEO_ON :NODE;
|
||||
SYS_CTR[6..0] :DFFE;
|
||||
SYS_CTR_CS :NODE;
|
||||
VDL_LOF[15..0] :DFFE;
|
||||
VDL_LOF_CS :NODE;
|
||||
VDL_LWD[15..0] :DFFE;
|
||||
VDL_LWD_CS :NODE;
|
||||
-- DIV. CONTROL REGISTER
|
||||
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
|
||||
HSYNC :DFF;
|
||||
HSYNC_I[7..0] :DFF;
|
||||
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
|
||||
HSYNC_START :DFF;
|
||||
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
|
||||
VSYNC :DFF;
|
||||
VSYNC_START :DFFE;
|
||||
VSYNC_I[2..0] :DFFE;
|
||||
nBLANK :DFF;
|
||||
DISP_ON :DFF;
|
||||
DPO_ZL :DFFE;
|
||||
DPO_ON :DFF;
|
||||
DPO_OFF :DFF;
|
||||
VDTRON :DFF;
|
||||
VDO_ZL :DFFE;
|
||||
VDO_ON :DFF;
|
||||
VDO_OFF :DFF;
|
||||
VHCNT[11..0] :DFF;
|
||||
SUB_PIXEL_CNT[6..0] :DFFE;
|
||||
VVCNT[10..0] :DFFE;
|
||||
VERZ[2..0][9..0] :DFF;
|
||||
RAND[6..0] :DFF;
|
||||
RAND_ON :NODE;
|
||||
FIFO_RDE :DFF;
|
||||
CLR_FIFO :DFFE;
|
||||
START_ZEILE :DFFE;
|
||||
SYNC_PIX :DFF;
|
||||
SYNC_PIX1 :DFF;
|
||||
SYNC_PIX2 :DFF;
|
||||
CCSEL[2..0] :DFF;
|
||||
COLOR16 :NODE;
|
||||
COLOR24 :NODE;
|
||||
-- ATARI RESOLUTION
|
||||
ATARI_SYNC :NODE;
|
||||
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
|
||||
ATARI_HH_CS :NODE;
|
||||
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
|
||||
ATARI_VH_CS :NODE;
|
||||
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
|
||||
ATARI_HL_CS :NODE;
|
||||
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
|
||||
ATARI_VL_CS :NODE;
|
||||
-- HORIZONTAL
|
||||
RAND_LINKS[11..0] :NODE;
|
||||
RAND_LINKS_FULL[23..0] :NODE; -- GE
|
||||
HDIS_START[11..0] :NODE;
|
||||
HDIS_END[11..0] :NODE;
|
||||
RAND_RECHTS[11..0] :NODE;
|
||||
HS_START[11..0] :NODE;
|
||||
HS_START_FULL[23..0] :NODE; -- GE
|
||||
H_TOTAL[11..0] :NODE;
|
||||
H_TOTAL_FULL[23..0] :NODE; -- GE
|
||||
HDIS_LEN[11..0] :NODE;
|
||||
MULF[5..0] :NODE;
|
||||
VDL_HHT[11..0] :DFFE;
|
||||
VDL_HHT_CS :NODE;
|
||||
VDL_HBE[11..0] :DFFE;
|
||||
VDL_HBE_CS :NODE;
|
||||
VDL_HDB[11..0] :DFFE;
|
||||
VDL_HDB_CS :NODE;
|
||||
VDL_HDE[11..0] :DFFE;
|
||||
VDL_HDE_CS :NODE;
|
||||
VDL_HBB[11..0] :DFFE;
|
||||
VDL_HBB_CS :NODE;
|
||||
VDL_HSS[11..0] :DFFE;
|
||||
VDL_HSS_CS :NODE;
|
||||
-- VERTIKAL
|
||||
RAND_OBEN[10..0] :NODE;
|
||||
VDIS_START[10..0] :NODE;
|
||||
VDIS_END[10..0] :NODE;
|
||||
RAND_UNTEN[10..0] :NODE;
|
||||
VS_START[10..0] :NODE;
|
||||
V_TOTAL[10..0] :NODE;
|
||||
FALCON_VIDEO :NODE;
|
||||
ST_VIDEO :NODE;
|
||||
INTER_ZEI :DFF;
|
||||
DOP_ZEI :DFF;
|
||||
DOP_FIFO_CLR :DFF;
|
||||
|
||||
VDL_VBE[10..0] :DFFE;
|
||||
VDL_VBE_CS :NODE;
|
||||
VDL_VDB[10..0] :DFFE;
|
||||
VDL_VDB_CS :NODE;
|
||||
VDL_VDE[10..0] :DFFE;
|
||||
VDL_VDE_CS :NODE;
|
||||
VDL_VBB[10..0] :DFFE;
|
||||
VDL_VBB_CS :NODE;
|
||||
VDL_VSS[10..0] :DFFE;
|
||||
VDL_VSS_CS :NODE;
|
||||
VDL_VFT[10..0] :DFFE;
|
||||
VDL_VFT_CS :NODE;
|
||||
VDL_VCT[8..0] :DFFE;
|
||||
VDL_VCT_CS :NODE;
|
||||
VDL_VMD[3..0] :DFFE;
|
||||
VDL_VMD_CS :NODE;
|
||||
|
||||
BEGIN
|
||||
-- BYT SELECT 32 BIT
|
||||
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
|
||||
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
|
||||
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
|
||||
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
-- BYT SELECT 16 BIT
|
||||
FB_16B0 = FB_ADR[0]==0; -- ADR==0
|
||||
FB_16B1 = FB_ADR[0]==1 -- ADR==1
|
||||
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
|
||||
-- ACP CLUT --
|
||||
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
|
||||
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
|
||||
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
|
||||
CLUT_TA.CLK = MAIN_CLK;
|
||||
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
|
||||
--FALCON CLUT --
|
||||
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400
|
||||
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
|
||||
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
|
||||
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
|
||||
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
|
||||
-- ST CLUT --
|
||||
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20
|
||||
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
|
||||
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
|
||||
-- ST SHIFT MODE
|
||||
ST_SHIFT_MODE[].CLK = MAIN_CLK;
|
||||
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
|
||||
ST_SHIFT_MODE[] = FB_AD[25..24];
|
||||
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
|
||||
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
|
||||
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
|
||||
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
|
||||
-- FALCON SHIFT MODE
|
||||
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
|
||||
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
|
||||
FALCON_SHIFT_MODE[] = FB_AD[26..16];
|
||||
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
|
||||
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
|
||||
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
|
||||
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
|
||||
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
|
||||
ACP_VCTR[].CLK = MAIN_CLK;
|
||||
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
|
||||
ACP_VCTR[31..8] = FB_AD[31..8];
|
||||
ACP_VCTR[5..0] = FB_AD[5..0];
|
||||
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
|
||||
ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
|
||||
ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
|
||||
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
|
||||
ACP_VIDEO_ON = ACP_VCTR0;
|
||||
nPD_VGA = ACP_VCTR1;
|
||||
-- ATARI MODUS
|
||||
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
|
||||
-- HORIZONTAL TIMING 640x480
|
||||
ATARI_HH[].CLK = MAIN_CLK;
|
||||
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
|
||||
ATARI_HH[] = FB_AD[];
|
||||
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
|
||||
-- VERTIKAL TIMING 640x480
|
||||
ATARI_VH[].CLK = MAIN_CLK;
|
||||
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
|
||||
ATARI_VH[] = FB_AD[];
|
||||
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
|
||||
-- HORIZONTAL TIMING 320x240
|
||||
ATARI_HL[].CLK = MAIN_CLK;
|
||||
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
|
||||
ATARI_HL[] = FB_AD[];
|
||||
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
|
||||
-- VERTIKAL TIMING 320x240
|
||||
ATARI_VL[].CLK = MAIN_CLK;
|
||||
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
|
||||
ATARI_VL[] = FB_AD[];
|
||||
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
|
||||
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
|
||||
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
|
||||
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
|
||||
-- VIDEO PLL CONFIG
|
||||
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
|
||||
VR_WR.CLK = MAIN_CLK;
|
||||
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
|
||||
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
|
||||
VR_DOUT[].CLK = MAIN_CLK;
|
||||
VR_DOUT[].ENA = !VR_BUSY;
|
||||
VR_DOUT[] = VR_D[];
|
||||
VR_FRQ[].CLK = MAIN_CLK;
|
||||
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
|
||||
VR_FRQ[] = FB_AD[23..16];
|
||||
-- VIDEO PLL RECONFIG
|
||||
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
|
||||
VIDEO_RECONFIG.CLK = MAIN_CLK;
|
||||
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
|
||||
------------------------------------------------------------------------------------------------------------------------
|
||||
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
|
||||
-------------- COLOR MODE IM ACP SETZEN
|
||||
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
|
||||
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
|
||||
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
|
||||
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
|
||||
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
|
||||
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
|
||||
FALCON_VIDEO = ACP_VCTR7;
|
||||
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
|
||||
ST_VIDEO = ACP_VCTR6;
|
||||
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
|
||||
CCSEL[].CLK = PIXEL_CLK;
|
||||
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
|
||||
# B"001" & FALCON_CLUT
|
||||
# B"100" & ACP_CLUT
|
||||
# B"101" & COLOR16
|
||||
# B"110" & COLOR24
|
||||
# B"111" & RAND_ON;
|
||||
-- DIVERSE (VIDEO)-REGISTER ----------------------------
|
||||
-- RANDFARBE
|
||||
CCR[].CLK = MAIN_CLK;
|
||||
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
|
||||
CCR[] = FB_AD[23..0];
|
||||
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
|
||||
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
|
||||
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
|
||||
--SYS CTR
|
||||
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
|
||||
SYS_CTR[].CLK = MAIN_CLK;
|
||||
SYS_CTR[6..0] = FB_AD[22..16];
|
||||
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
|
||||
BLITTER_ON = !SYS_CTR3;
|
||||
--VDL_LOF
|
||||
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
|
||||
VDL_LOF[].CLK = MAIN_CLK;
|
||||
VDL_LOF[] = FB_AD[31..16];
|
||||
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
|
||||
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
|
||||
--VDL_LWD
|
||||
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
|
||||
VDL_LWD[].CLK = MAIN_CLK;
|
||||
VDL_LWD[] = FB_AD[31..16];
|
||||
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
|
||||
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
|
||||
-- HORIZONTAL
|
||||
-- VDL_HHT
|
||||
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
|
||||
VDL_HHT[].CLK = MAIN_CLK;
|
||||
VDL_HHT[] = FB_AD[27..16];
|
||||
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
|
||||
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HBE
|
||||
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
|
||||
VDL_HBE[].CLK = MAIN_CLK;
|
||||
VDL_HBE[] = FB_AD[27..16];
|
||||
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
|
||||
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HDB
|
||||
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
|
||||
VDL_HDB[].CLK = MAIN_CLK;
|
||||
VDL_HDB[] = FB_AD[27..16];
|
||||
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
|
||||
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_HDE
|
||||
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
|
||||
VDL_HDE[].CLK = MAIN_CLK;
|
||||
VDL_HDE[] = FB_AD[27..16];
|
||||
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
|
||||
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_HBB
|
||||
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
|
||||
VDL_HBB[].CLK = MAIN_CLK;
|
||||
VDL_HBB[] = FB_AD[27..16];
|
||||
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
|
||||
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_HSS
|
||||
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
|
||||
VDL_HSS[].CLK = MAIN_CLK;
|
||||
VDL_HSS[] = FB_AD[27..16];
|
||||
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
|
||||
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
|
||||
-- VERTIKAL
|
||||
-- VDL_VBE
|
||||
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
|
||||
VDL_VBE[].CLK = MAIN_CLK;
|
||||
VDL_VBE[] = FB_AD[26..16];
|
||||
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
|
||||
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VDB
|
||||
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
|
||||
VDL_VDB[].CLK = MAIN_CLK;
|
||||
VDL_VDB[] = FB_AD[26..16];
|
||||
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
|
||||
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VDE
|
||||
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
|
||||
VDL_VDE[].CLK = MAIN_CLK;
|
||||
VDL_VDE[] = FB_AD[26..16];
|
||||
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
|
||||
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VBB
|
||||
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
|
||||
VDL_VBB[].CLK = MAIN_CLK;
|
||||
VDL_VBB[] = FB_AD[26..16];
|
||||
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
|
||||
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VSS
|
||||
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
|
||||
VDL_VSS[].CLK = MAIN_CLK;
|
||||
VDL_VSS[] = FB_AD[26..16];
|
||||
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
|
||||
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VFT
|
||||
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
|
||||
VDL_VFT[].CLK = MAIN_CLK;
|
||||
VDL_VFT[] = FB_AD[26..16];
|
||||
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
|
||||
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
|
||||
-- VDL_VCT
|
||||
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
|
||||
VDL_VCT[].CLK = MAIN_CLK;
|
||||
VDL_VCT[] = FB_AD[24..16];
|
||||
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
|
||||
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
|
||||
-- VDL_VMD
|
||||
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
|
||||
VDL_VMD[].CLK = MAIN_CLK;
|
||||
VDL_VMD[] = FB_AD[19..16];
|
||||
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
|
||||
--- REGISTER OUT
|
||||
FB_AD[31..16] = lpm_bustri_WORD(
|
||||
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
|
||||
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
|
||||
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
|
||||
# VDL_LOF_CS & VDL_LOF[]
|
||||
# VDL_LWD_CS & VDL_LWD[]
|
||||
# VDL_HBE_CS & (0,VDL_HBE[])
|
||||
# VDL_HDB_CS & (0,VDL_HDB[])
|
||||
# VDL_HDE_CS & (0,VDL_HDE[])
|
||||
# VDL_HBB_CS & (0,VDL_HBB[])
|
||||
# VDL_HSS_CS & (0,VDL_HSS[])
|
||||
# VDL_HHT_CS & (0,VDL_HHT[])
|
||||
# VDL_VBE_CS & (0,VDL_VBE[])
|
||||
# VDL_VDB_CS & (0,VDL_VDB[])
|
||||
# VDL_VDE_CS & (0,VDL_VDE[])
|
||||
# VDL_VBB_CS & (0,VDL_VBB[])
|
||||
# VDL_VSS_CS & (0,VDL_VSS[])
|
||||
# VDL_VFT_CS & (0,VDL_VFT[])
|
||||
# VDL_VCT_CS & (0,VDL_VCT[])
|
||||
# VDL_VMD_CS & (0,VDL_VMD[])
|
||||
# ACP_VCTR_CS & ACP_VCTR[31..16]
|
||||
# ATARI_HH_CS & ATARI_HH[31..16]
|
||||
# ATARI_VH_CS & ATARI_VH[31..16]
|
||||
# ATARI_HL_CS & ATARI_HL[31..16]
|
||||
# ATARI_VL_CS & ATARI_VL[31..16]
|
||||
# CCR_CS & (0,CCR[23..16])
|
||||
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
|
||||
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
|
||||
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
|
||||
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
|
||||
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
|
||||
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
|
||||
|
||||
FB_AD[15..0] = lpm_bustri_WORD(
|
||||
ACP_VCTR_CS & ACP_VCTR[15..0]
|
||||
# ATARI_HH_CS & ATARI_HH[15..0]
|
||||
# ATARI_VH_CS & ATARI_VH[15..0]
|
||||
# ATARI_HL_CS & ATARI_HL[15..0]
|
||||
# ATARI_VL_CS & ATARI_VL[15..0]
|
||||
# CCR_CS & CCR[15..0]
|
||||
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
|
||||
|
||||
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
|
||||
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
|
||||
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
|
||||
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
|
||||
|
||||
-- VIDEO AUSGABE SETZEN
|
||||
CLK17M.CLK = CLK33M;
|
||||
CLK17M = !CLK17M;
|
||||
CLK13M.CLK = CLK25M;
|
||||
CLK13M = !CLK13M;
|
||||
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
|
||||
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
|
||||
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
|
||||
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
|
||||
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
|
||||
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
|
||||
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
|
||||
--------------------------------------------------------------
|
||||
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
|
||||
----------------------------------------------------------------
|
||||
HSY_LEN[].CLK = MAIN_CLK;
|
||||
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
|
||||
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
|
||||
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
|
||||
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
|
||||
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
|
||||
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
|
||||
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
|
||||
|
||||
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
|
||||
# 4 & !ST_VIDEO & !VDL_VMD2
|
||||
# 16 & ST_VIDEO & VDL_VMD2
|
||||
# 32 & ST_VIDEO & !VDL_VMD2;
|
||||
|
||||
|
||||
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
|
||||
# 640 & !VDL_VMD2;
|
||||
|
||||
-- DOPPELZEILENMODUS
|
||||
DOP_ZEI.CLK = MAIN_CLK;
|
||||
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
|
||||
INTER_ZEI.CLK = PIXEL_CLK;
|
||||
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
||||
DOP_FIFO_CLR.CLK = PIXEL_CLK;
|
||||
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
|
||||
|
||||
RAND_LINKS_FULL[] = VDL_HBE[] * (0,MULF[5..1]); -- GE
|
||||
HS_START_FULL[] = (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]); -- GE
|
||||
H_TOTAL_FULL[] = (VDL_HHT[]+2) * (0,MULF[]); -- GE
|
||||
|
||||
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
|
||||
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# RAND_LINKS_FULL[11..0] & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
|
||||
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
|
||||
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
|
||||
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
|
||||
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
|
||||
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# HS_START_FULL[11..0] & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
|
||||
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# H_TOTAL_FULL[11..0] & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
||||
|
||||
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
|
||||
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
|
||||
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
|
||||
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
|
||||
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
|
||||
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
|
||||
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
|
||||
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
|
||||
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
|
||||
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
|
||||
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
||||
-- Z<>HLER
|
||||
LAST.CLK = PIXEL_CLK;
|
||||
LAST = VHCNT[]==(H_TOTAL[]-2);
|
||||
VHCNT[].CLK = PIXEL_CLK;
|
||||
VHCNT[] = (VHCNT[] + 1) & !LAST;
|
||||
VVCNT[].CLK = PIXEL_CLK;
|
||||
VVCNT[].ENA = LAST;
|
||||
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
|
||||
-- DISPLAY ON OFF
|
||||
DPO_ZL.CLK = PIXEL_CLK;
|
||||
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
|
||||
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
|
||||
DPO_ON.CLK = PIXEL_CLK;
|
||||
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
|
||||
DPO_OFF.CLK = PIXEL_CLK;
|
||||
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
|
||||
DISP_ON.CLK = PIXEL_CLK;
|
||||
DISP_ON = DISP_ON & !DPO_OFF
|
||||
# DPO_ON & DPO_ZL;
|
||||
-- DATENTRANSFER ON OFF
|
||||
VDO_ON.CLK = PIXEL_CLK;
|
||||
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
|
||||
VDO_OFF.CLK = PIXEL_CLK;
|
||||
VDO_OFF = VHCNT[]==HDIS_END[];
|
||||
VDO_ZL.CLK = PIXEL_CLK;
|
||||
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
|
||||
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
|
||||
VDTRON.CLK = PIXEL_CLK;
|
||||
VDTRON = VDTRON & !VDO_OFF
|
||||
# VDO_ON & VDO_ZL;
|
||||
-- VERZ<52>GERUNG UND SYNC
|
||||
HSYNC_START.CLK = PIXEL_CLK;
|
||||
HSYNC_START = VHCNT[]==HS_START[]-3;
|
||||
HSYNC_I[].CLK = PIXEL_CLK;
|
||||
HSYNC_I[] = HSY_LEN[] & HSYNC_START
|
||||
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
|
||||
VSYNC_START.CLK = PIXEL_CLK;
|
||||
VSYNC_START.ENA = LAST;
|
||||
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
|
||||
VSYNC_I[].CLK = PIXEL_CLK;
|
||||
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
|
||||
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
|
||||
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
|
||||
VERZ[][].CLK = PIXEL_CLK;
|
||||
VERZ[][1] = VERZ[][0];
|
||||
VERZ[][2] = VERZ[][1];
|
||||
VERZ[][3] = VERZ[][2];
|
||||
VERZ[][4] = VERZ[][3];
|
||||
VERZ[][5] = VERZ[][4];
|
||||
VERZ[][6] = VERZ[][5];
|
||||
VERZ[][7] = VERZ[][6];
|
||||
VERZ[][8] = VERZ[][7];
|
||||
VERZ[][9] = VERZ[][8];
|
||||
VERZ[0][0] = DISP_ON;
|
||||
VERZ[1][0] = HSYNC_I[]!=0;
|
||||
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
|
||||
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
|
||||
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
|
||||
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
|
||||
nBLANK.CLK = PIXEL_CLK;
|
||||
nBLANK = VERZ[0][8];
|
||||
HSYNC.CLK = PIXEL_CLK;
|
||||
HSYNC = VERZ[1][9];
|
||||
VSYNC.CLK = PIXEL_CLK;
|
||||
VSYNC = VERZ[2][9];
|
||||
nSYNC = GND;
|
||||
-- RANDFARBE MACHEN ------------------------------------
|
||||
RAND[].CLK = PIXEL_CLK;
|
||||
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
|
||||
RAND[1] = RAND[0];
|
||||
RAND[2] = RAND[1];
|
||||
RAND[3] = RAND[2];
|
||||
RAND[4] = RAND[3];
|
||||
RAND[5] = RAND[4];
|
||||
RAND[6] = RAND[5];
|
||||
RAND_ON = RAND[6];
|
||||
----------------------------------------------------------
|
||||
CLR_FIFO.CLK = PIXEL_CLK;
|
||||
CLR_FIFO.ENA = LAST;
|
||||
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
|
||||
START_ZEILE.CLK = PIXEL_CLK;
|
||||
START_ZEILE.ENA = LAST;
|
||||
START_ZEILE = VVCNT[]==0; -- ZEILE 1
|
||||
SYNC_PIX.CLK = PIXEL_CLK;
|
||||
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
|
||||
SYNC_PIX1.CLK = PIXEL_CLK;
|
||||
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
|
||||
SYNC_PIX2.CLK = PIXEL_CLK;
|
||||
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
|
||||
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
|
||||
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
|
||||
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
|
||||
FIFO_RDE.CLK = PIXEL_CLK;
|
||||
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
|
||||
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
|
||||
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
|
||||
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
|
||||
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
|
||||
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
|
||||
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
|
||||
|
||||
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
|
||||
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
|
||||
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
|
||||
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
|
||||
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
|
||||
END;
|
||||
1474
FPGA_by_Gregory_Estrade/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v
Normal file
1474
FPGA_by_Gregory_Estrade/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v
Normal file
File diff suppressed because it is too large
Load Diff
478
FPGA_by_Gregory_Estrade/ahdl2v/interrupt_handler.tdf
Normal file
478
FPGA_by_Gregory_Estrade/ahdl2v/interrupt_handler.tdf
Normal file
@@ -0,0 +1,478 @@
|
||||
TITLE "INTERRUPT HANDLER UND C1287";
|
||||
|
||||
-- CREATED BY FREDI ASCHWANDEN
|
||||
|
||||
INCLUDE "lpm_bustri_LONG.inc";
|
||||
INCLUDE "lpm_bustri_BYT.inc";
|
||||
|
||||
|
||||
-- Parameters Statement (optional)
|
||||
|
||||
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
|
||||
|
||||
|
||||
-- Subdesign Section
|
||||
|
||||
SUBDESIGN interrupt_handler
|
||||
(
|
||||
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
MAIN_CLK : INPUT;
|
||||
nFB_WR : INPUT;
|
||||
nFB_CS1 : INPUT;
|
||||
nFB_CS2 : INPUT;
|
||||
FB_SIZE0 : INPUT;
|
||||
FB_SIZE1 : INPUT;
|
||||
FB_ADR[31..0] : INPUT;
|
||||
PIC_INT : INPUT;
|
||||
E0_INT : INPUT;
|
||||
DVI_INT : INPUT;
|
||||
nPCI_INTA : INPUT;
|
||||
nPCI_INTB : INPUT;
|
||||
nPCI_INTC : INPUT;
|
||||
nPCI_INTD : INPUT;
|
||||
nMFP_INT : INPUT;
|
||||
nFB_OE : INPUT;
|
||||
DSP_INT : INPUT;
|
||||
VSYNC : INPUT;
|
||||
HSYNC : INPUT;
|
||||
DMA_DRQ : INPUT;
|
||||
nIRQ[7..2] : OUTPUT;
|
||||
INT_HANDLER_TA : OUTPUT;
|
||||
ACP_CONF[31..0] : OUTPUT;
|
||||
TIN0 : OUTPUT;
|
||||
FB_AD[31..0] : BIDIR;
|
||||
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
FB_B[3..0] :NODE;
|
||||
INT_CTR[31..0] :DFFE;
|
||||
INT_CTR_CS :NODE;
|
||||
INT_LATCH[31..0] :DFF;
|
||||
INT_LATCH_CS :NODE;
|
||||
INT_CLEAR[31..0] :DFF;
|
||||
INT_CLEAR_CS :NODE;
|
||||
INT_IN[31..0] :NODE;
|
||||
INT_ENA[31..0] :DFFE;
|
||||
INT_ENA_CS :NODE;
|
||||
ACP_CONF[31..0] :DFFE;
|
||||
ACP_CONF_CS :NODE;
|
||||
PSEUDO_BUS_ERROR :NODE;
|
||||
UHR_AS :NODE;
|
||||
UHR_DS :NODE;
|
||||
RTC_ADR[5..0] :DFFE;
|
||||
ACHTELSEKUNDEN[2..0] :DFFE;
|
||||
WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63
|
||||
PIC_INT_SYNC[2..0] :DFF;
|
||||
INC_SEC :NODE;
|
||||
INC_MIN :NODE;
|
||||
INC_STD :NODE;
|
||||
INC_TAG :NODE;
|
||||
ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
|
||||
WINTERZEIT :NODE;
|
||||
SOMMERZEIT :NODE;
|
||||
INC_MONAT :NODE;
|
||||
INC_JAHR :NODE;
|
||||
UPDATE_ON :NODE;
|
||||
|
||||
BEGIN
|
||||
-- BYT SELECT
|
||||
FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
|
||||
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT
|
||||
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
|
||||
FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
|
||||
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT
|
||||
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
|
||||
FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
|
||||
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT
|
||||
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
|
||||
FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
|
||||
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
|
||||
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
|
||||
|
||||
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
|
||||
INT_CTR[].CLK = MAIN_CLK;
|
||||
INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
|
||||
INT_CTR[] = FB_AD[];
|
||||
INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
|
||||
INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
|
||||
INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
|
||||
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
|
||||
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
|
||||
INT_ENA[].CLK = MAIN_CLK;
|
||||
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
|
||||
INT_ENA[] = FB_AD[];
|
||||
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
|
||||
INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
|
||||
INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
|
||||
INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
|
||||
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
|
||||
INT_CLEAR[].CLK = MAIN_CLK;
|
||||
INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
|
||||
INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
|
||||
INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
|
||||
INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
|
||||
INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
|
||||
-- INTERRUPT LATCH REGISTER READ ONLY
|
||||
INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
|
||||
-- INTERRUPT
|
||||
!nIRQ2 = HSYNC & INT_ENA[26];
|
||||
!nIRQ3 = INT_CTR0 & INT_ENA[27];
|
||||
!nIRQ4 = VSYNC & INT_ENA[28];
|
||||
nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29];
|
||||
!nIRQ6 = !nMFP_INT & INT_ENA[30];
|
||||
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
|
||||
|
||||
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
|
||||
# FB_ADR[19..4]==H"F8E0" -- VME
|
||||
# FB_ADR[19..4]==H"F920" -- PADDLE
|
||||
# FB_ADR[19..4]==H"F921" -- PADDLE
|
||||
# FB_ADR[19..4]==H"F922" -- PADDLE
|
||||
# FB_ADR[19..4]==H"FFA8" -- MFP2
|
||||
# FB_ADR[19..4]==H"FFA9" -- MFP2
|
||||
# FB_ADR[19..4]==H"FFAA" -- MFP2
|
||||
# FB_ADR[19..4]==H"FFA8" -- MFP2
|
||||
# FB_ADR[19..8]==H"F87" -- TT SCSI
|
||||
# FB_ADR[19..4]==H"FFC2" -- ST UHR
|
||||
# FB_ADR[19..4]==H"FFC3" -- ST UHR
|
||||
# FB_ADR[19..4]==H"F890" -- DMA SOUND
|
||||
# FB_ADR[19..4]==H"F891" -- DMA SOUND
|
||||
# FB_ADR[19..4]==H"F892"); -- DMA SOUND
|
||||
-- IF VIDEO ADR CHANGE
|
||||
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
|
||||
|
||||
-- INTERRUPT LATCH
|
||||
INT_LATCH[] = H"FFFFFFFF";
|
||||
INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
|
||||
INT_LATCH1.CLK = E0_INT & INT_ENA[1];
|
||||
INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
|
||||
INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
|
||||
INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
|
||||
INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
|
||||
INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
|
||||
INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
|
||||
INT_LATCH8.CLK = VSYNC & INT_ENA[8];
|
||||
INT_LATCH9.CLK = HSYNC & INT_ENA[9];
|
||||
|
||||
-- INTERRUPT CLEAR
|
||||
INT_LATCH[].CLRN = !INT_CLEAR[];
|
||||
|
||||
-- INT_IN
|
||||
INT_IN0 = PIC_INT;
|
||||
INT_IN1 = E0_INT;
|
||||
INT_IN2 = DVI_INT;
|
||||
INT_IN3 = !nPCI_INTA;
|
||||
INT_IN4 = !nPCI_INTB;
|
||||
INT_IN5 = !nPCI_INTC;
|
||||
INT_IN6 = !nPCI_INTD;
|
||||
INT_IN7 = DSP_INT;
|
||||
INT_IN8 = VSYNC;
|
||||
INT_IN9 = HSYNC;
|
||||
INT_IN[25..10] = H"0";
|
||||
INT_IN26 = HSYNC;
|
||||
INT_IN27 = INT_CTR0;
|
||||
INT_IN28 = VSYNC;
|
||||
INT_IN29 = INT_LATCH[]!=H"00000000";
|
||||
INT_IN30 = !nMFP_INT;
|
||||
INT_IN31 = DMA_DRQ;
|
||||
--***************************************************************************************
|
||||
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
|
||||
ACP_CONF[].CLK = MAIN_CLK;
|
||||
ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4
|
||||
ACP_CONF[] = FB_AD[];
|
||||
ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
|
||||
ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
|
||||
ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
|
||||
ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
|
||||
--***************************************************************************************
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
|
||||
----------------------------------------------------------
|
||||
RTC_ADR[].CLK = MAIN_CLK;
|
||||
RTC_ADR[] = FB_AD[21..16];
|
||||
UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961
|
||||
UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963
|
||||
RTC_ADR[].ENA = UHR_AS & !nFB_WR;
|
||||
WERTE[][].CLK = MAIN_CLK;
|
||||
WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][1] = FB_AD[23..16];
|
||||
WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][3] = FB_AD[23..16];
|
||||
WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][5] = FB_AD[23..16];
|
||||
WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
|
||||
WERTE[7..0][10] = FB_AD[23..16];
|
||||
WERTE[7..0][11] = FB_AD[23..16];
|
||||
WERTE[7..0][12] = FB_AD[23..16];
|
||||
WERTE[7..0][13] = FB_AD[23..16];
|
||||
WERTE[7..0][14] = FB_AD[23..16];
|
||||
WERTE[7..0][15] = FB_AD[23..16];
|
||||
WERTE[7..0][16] = FB_AD[23..16];
|
||||
WERTE[7..0][17] = FB_AD[23..16];
|
||||
WERTE[7..0][18] = FB_AD[23..16];
|
||||
WERTE[7..0][19] = FB_AD[23..16];
|
||||
WERTE[7..0][20] = FB_AD[23..16];
|
||||
WERTE[7..0][21] = FB_AD[23..16];
|
||||
WERTE[7..0][22] = FB_AD[23..16];
|
||||
WERTE[7..0][23] = FB_AD[23..16];
|
||||
WERTE[7..0][24] = FB_AD[23..16];
|
||||
WERTE[7..0][25] = FB_AD[23..16];
|
||||
WERTE[7..0][26] = FB_AD[23..16];
|
||||
WERTE[7..0][27] = FB_AD[23..16];
|
||||
WERTE[7..0][28] = FB_AD[23..16];
|
||||
WERTE[7..0][29] = FB_AD[23..16];
|
||||
WERTE[7..0][30] = FB_AD[23..16];
|
||||
WERTE[7..0][31] = FB_AD[23..16];
|
||||
WERTE[7..0][32] = FB_AD[23..16];
|
||||
WERTE[7..0][33] = FB_AD[23..16];
|
||||
WERTE[7..0][34] = FB_AD[23..16];
|
||||
WERTE[7..0][35] = FB_AD[23..16];
|
||||
WERTE[7..0][36] = FB_AD[23..16];
|
||||
WERTE[7..0][37] = FB_AD[23..16];
|
||||
WERTE[7..0][38] = FB_AD[23..16];
|
||||
WERTE[7..0][39] = FB_AD[23..16];
|
||||
WERTE[7..0][40] = FB_AD[23..16];
|
||||
WERTE[7..0][41] = FB_AD[23..16];
|
||||
WERTE[7..0][42] = FB_AD[23..16];
|
||||
WERTE[7..0][43] = FB_AD[23..16];
|
||||
WERTE[7..0][44] = FB_AD[23..16];
|
||||
WERTE[7..0][45] = FB_AD[23..16];
|
||||
WERTE[7..0][46] = FB_AD[23..16];
|
||||
WERTE[7..0][47] = FB_AD[23..16];
|
||||
WERTE[7..0][48] = FB_AD[23..16];
|
||||
WERTE[7..0][49] = FB_AD[23..16];
|
||||
WERTE[7..0][50] = FB_AD[23..16];
|
||||
WERTE[7..0][51] = FB_AD[23..16];
|
||||
WERTE[7..0][52] = FB_AD[23..16];
|
||||
WERTE[7..0][53] = FB_AD[23..16];
|
||||
WERTE[7..0][54] = FB_AD[23..16];
|
||||
WERTE[7..0][55] = FB_AD[23..16];
|
||||
WERTE[7..0][56] = FB_AD[23..16];
|
||||
WERTE[7..0][57] = FB_AD[23..16];
|
||||
WERTE[7..0][58] = FB_AD[23..16];
|
||||
WERTE[7..0][59] = FB_AD[23..16];
|
||||
WERTE[7..0][60] = FB_AD[23..16];
|
||||
WERTE[7..0][61] = FB_AD[23..16];
|
||||
WERTE[7..0][62] = FB_AD[23..16];
|
||||
WERTE[7..0][63] = FB_AD[23..16];
|
||||
WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
|
||||
WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
|
||||
WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
|
||||
WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
|
||||
WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
|
||||
WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
|
||||
WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
|
||||
WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
|
||||
WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
|
||||
WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
|
||||
WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
|
||||
WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
|
||||
WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
|
||||
WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
|
||||
WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
|
||||
WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
|
||||
WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
|
||||
WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
|
||||
WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
|
||||
WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
|
||||
WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
|
||||
WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
|
||||
WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
|
||||
WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
|
||||
WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
|
||||
WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
|
||||
WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
|
||||
WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
|
||||
WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
|
||||
WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
|
||||
WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
|
||||
WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
|
||||
WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
|
||||
WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
|
||||
WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
|
||||
WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
|
||||
WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
|
||||
WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
|
||||
WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
|
||||
WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
|
||||
WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
|
||||
WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
|
||||
WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
|
||||
WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
|
||||
WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
|
||||
WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
|
||||
WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
|
||||
WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
|
||||
WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
|
||||
WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
|
||||
WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
|
||||
WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
|
||||
WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
|
||||
WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
|
||||
WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
|
||||
WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
|
||||
WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
|
||||
WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
|
||||
WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
|
||||
WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
|
||||
WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
|
||||
WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
|
||||
WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
|
||||
WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
|
||||
PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT;
|
||||
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
|
||||
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
|
||||
UPDATE_ON = !WERTE[7][11];
|
||||
WERTE[6][10].CLRN = GND; -- KEIN UIP
|
||||
UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF
|
||||
WERTE[2][11] = VCC; -- IMMER BINARY
|
||||
WERTE[1][11] = VCC; -- IMMER 24H FORMAT
|
||||
WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
|
||||
WERTE[7][13] = VCC; -- IMMER RICHTIG
|
||||
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
|
||||
SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
|
||||
WERTE[0][13] = SOMMERZEIT;
|
||||
WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
|
||||
WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER
|
||||
-- ACHTELSEKUNDEN
|
||||
ACHTELSEKUNDEN[].CLK = MAIN_CLK;
|
||||
ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
|
||||
ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
|
||||
-- SEKUNDEN
|
||||
INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
|
||||
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
|
||||
WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
|
||||
-- MINUTEN
|
||||
INC_MIN = INC_SEC & WERTE[][0]==59; --
|
||||
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
|
||||
WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
|
||||
-- STUNDEN
|
||||
INC_STD = INC_MIN & WERTE[][2]==59;
|
||||
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
|
||||
WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
|
||||
-- WOCHENTAG UND TAG
|
||||
INC_TAG = INC_STD & WERTE[][2]==23;
|
||||
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
|
||||
# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
|
||||
ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
|
||||
# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
|
||||
# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
|
||||
# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
|
||||
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
|
||||
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
|
||||
-- MONATE
|
||||
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
|
||||
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
|
||||
# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
|
||||
-- JAHR
|
||||
INC_JAHR = INC_MONAT & WERTE[][8]==12; --
|
||||
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
|
||||
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
|
||||
-- TRISTATE OUTPUT
|
||||
|
||||
FB_AD[31..24] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[31..24]
|
||||
# INT_ENA_CS & INT_ENA[31..24]
|
||||
# INT_LATCH_CS & INT_LATCH[31..24]
|
||||
# INT_CLEAR_CS & INT_IN[31..24]
|
||||
# ACP_CONF_CS & ACP_CONF[31..24]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
|
||||
FB_AD[23..16] = lpm_bustri_BYT(
|
||||
WERTE[][0] & RTC_ADR[]==0 & UHR_DS
|
||||
# WERTE[][1] & RTC_ADR[]==1 & UHR_DS
|
||||
# WERTE[][2] & RTC_ADR[]==2 & UHR_DS
|
||||
# WERTE[][3] & RTC_ADR[]==3 & UHR_DS
|
||||
# WERTE[][4] & RTC_ADR[]==4 & UHR_DS
|
||||
# WERTE[][5] & RTC_ADR[]==5 & UHR_DS
|
||||
# WERTE[][6] & RTC_ADR[]==6 & UHR_DS
|
||||
# WERTE[][7] & RTC_ADR[]==7 & UHR_DS
|
||||
# WERTE[][8] & RTC_ADR[]==8 & UHR_DS
|
||||
# WERTE[][9] & RTC_ADR[]==9 & UHR_DS
|
||||
# WERTE[][10] & RTC_ADR[]==10 & UHR_DS
|
||||
# WERTE[][11] & RTC_ADR[]==11 & UHR_DS
|
||||
# WERTE[][12] & RTC_ADR[]==12 & UHR_DS
|
||||
# WERTE[][13] & RTC_ADR[]==13 & UHR_DS
|
||||
# WERTE[][14] & RTC_ADR[]==14 & UHR_DS
|
||||
# WERTE[][15] & RTC_ADR[]==15 & UHR_DS
|
||||
# WERTE[][16] & RTC_ADR[]==16 & UHR_DS
|
||||
# WERTE[][17] & RTC_ADR[]==17 & UHR_DS
|
||||
# WERTE[][18] & RTC_ADR[]==18 & UHR_DS
|
||||
# WERTE[][19] & RTC_ADR[]==19 & UHR_DS
|
||||
# WERTE[][20] & RTC_ADR[]==20 & UHR_DS
|
||||
# WERTE[][21] & RTC_ADR[]==21 & UHR_DS
|
||||
# WERTE[][22] & RTC_ADR[]==22 & UHR_DS
|
||||
# WERTE[][23] & RTC_ADR[]==23 & UHR_DS
|
||||
# WERTE[][24] & RTC_ADR[]==24 & UHR_DS
|
||||
# WERTE[][25] & RTC_ADR[]==25 & UHR_DS
|
||||
# WERTE[][26] & RTC_ADR[]==26 & UHR_DS
|
||||
# WERTE[][27] & RTC_ADR[]==27 & UHR_DS
|
||||
# WERTE[][28] & RTC_ADR[]==28 & UHR_DS
|
||||
# WERTE[][29] & RTC_ADR[]==29 & UHR_DS
|
||||
# WERTE[][30] & RTC_ADR[]==30 & UHR_DS
|
||||
# WERTE[][31] & RTC_ADR[]==31 & UHR_DS
|
||||
# WERTE[][32] & RTC_ADR[]==32 & UHR_DS
|
||||
# WERTE[][33] & RTC_ADR[]==33 & UHR_DS
|
||||
# WERTE[][34] & RTC_ADR[]==34 & UHR_DS
|
||||
# WERTE[][35] & RTC_ADR[]==35 & UHR_DS
|
||||
# WERTE[][36] & RTC_ADR[]==36 & UHR_DS
|
||||
# WERTE[][37] & RTC_ADR[]==37 & UHR_DS
|
||||
# WERTE[][38] & RTC_ADR[]==38 & UHR_DS
|
||||
# WERTE[][39] & RTC_ADR[]==39 & UHR_DS
|
||||
# WERTE[][40] & RTC_ADR[]==40 & UHR_DS
|
||||
# WERTE[][41] & RTC_ADR[]==41 & UHR_DS
|
||||
# WERTE[][42] & RTC_ADR[]==42 & UHR_DS
|
||||
# WERTE[][43] & RTC_ADR[]==43 & UHR_DS
|
||||
# WERTE[][44] & RTC_ADR[]==44 & UHR_DS
|
||||
# WERTE[][45] & RTC_ADR[]==45 & UHR_DS
|
||||
# WERTE[][46] & RTC_ADR[]==46 & UHR_DS
|
||||
# WERTE[][47] & RTC_ADR[]==47 & UHR_DS
|
||||
# WERTE[][48] & RTC_ADR[]==48 & UHR_DS
|
||||
# WERTE[][49] & RTC_ADR[]==49 & UHR_DS
|
||||
# WERTE[][50] & RTC_ADR[]==50 & UHR_DS
|
||||
# WERTE[][51] & RTC_ADR[]==51 & UHR_DS
|
||||
# WERTE[][52] & RTC_ADR[]==52 & UHR_DS
|
||||
# WERTE[][53] & RTC_ADR[]==53 & UHR_DS
|
||||
# WERTE[][54] & RTC_ADR[]==54 & UHR_DS
|
||||
# WERTE[][55] & RTC_ADR[]==55 & UHR_DS
|
||||
# WERTE[][56] & RTC_ADR[]==56 & UHR_DS
|
||||
# WERTE[][57] & RTC_ADR[]==57 & UHR_DS
|
||||
# WERTE[][58] & RTC_ADR[]==58 & UHR_DS
|
||||
# WERTE[][59] & RTC_ADR[]==59 & UHR_DS
|
||||
# WERTE[][60] & RTC_ADR[]==60 & UHR_DS
|
||||
# WERTE[][61] & RTC_ADR[]==61 & UHR_DS
|
||||
# WERTE[][62] & RTC_ADR[]==62 & UHR_DS
|
||||
# WERTE[][63] & RTC_ADR[]==63 & UHR_DS
|
||||
# (0,RTC_ADR[]) & UHR_AS
|
||||
# INT_CTR_CS & INT_CTR[23..16]
|
||||
# INT_ENA_CS & INT_ENA[23..16]
|
||||
# INT_LATCH_CS & INT_LATCH[23..16]
|
||||
# INT_CLEAR_CS & INT_IN[23..16]
|
||||
# ACP_CONF_CS & ACP_CONF[23..16]
|
||||
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
|
||||
FB_AD[15..8] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[15..8]
|
||||
# INT_ENA_CS & INT_ENA[15..8]
|
||||
# INT_LATCH_CS & INT_LATCH[15..8]
|
||||
# INT_CLEAR_CS & INT_IN[15..8]
|
||||
# ACP_CONF_CS & ACP_CONF[15..8]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
|
||||
FB_AD[7..0] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[7..0]
|
||||
# INT_ENA_CS & INT_ENA[7..0]
|
||||
# INT_LATCH_CS & INT_LATCH[7..0]
|
||||
# INT_CLEAR_CS & INT_IN[7..0]
|
||||
# ACP_CONF_CS & ACP_CONF[7..0]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
|
||||
|
||||
INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
|
||||
END;
|
||||
|
||||
|
||||
3578
FPGA_by_Gregory_Estrade/ahdl2v/interrupt_handler.v
Normal file
3578
FPGA_by_Gregory_Estrade/ahdl2v/interrupt_handler.v
Normal file
File diff suppressed because it is too large
Load Diff
78
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri.tdf
Normal file
78
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri.tdf
Normal file
@@ -0,0 +1,78 @@
|
||||
--------------------------------------------------------------------
|
||||
--
|
||||
-- LPM_BUSTRI Parameterized Megafunction
|
||||
--
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- Quartus II 13.1.0 Build 162 10/23/2013
|
||||
--
|
||||
-- Version 2.0
|
||||
--
|
||||
--------------------------------------------------------------------
|
||||
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
LPM_WIDTH
|
||||
);
|
||||
|
||||
SUBDESIGN lpm_bustri
|
||||
(
|
||||
tridata[LPM_WIDTH-1..0] : BIDIR;
|
||||
data[LPM_WIDTH-1..0] : INPUT = VCC;
|
||||
enabletr : INPUT = VCC;
|
||||
enabledt : INPUT = VCC;
|
||||
result[LPM_WIDTH-1..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
% Are the enable inputs used? %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[LPM_WIDTH-1..0] : TRI;
|
||||
END GENERATE;
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[LPM_WIDTH-1..0] : TRI;
|
||||
END GENERATE;
|
||||
|
||||
BEGIN
|
||||
|
||||
ASSERT (LPM_WIDTH > 0)
|
||||
REPORT "Value of LPM_WIDTH parameter value must be greater than 0"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_WIDTH;
|
||||
|
||||
ASSERT (USED(enabledt) & USED(data))
|
||||
REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_DATA;
|
||||
|
||||
% Connect buffers if they are used %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[].oe = enabledt;
|
||||
dout[] = data[];
|
||||
tridata[] = dout[];
|
||||
END GENERATE;
|
||||
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[].oe = enabletr;
|
||||
din[] = tridata[];
|
||||
result[] = din[];
|
||||
ELSE GENERATE
|
||||
result[] = tridata[];
|
||||
END GENERATE;
|
||||
IF !USED(result) GENERATE
|
||||
result[] = GND;
|
||||
END GENERATE;
|
||||
END;
|
||||
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.inc
Normal file
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.inc
Normal file
@@ -0,0 +1,24 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_bustri_BYT
|
||||
(
|
||||
data[7..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[7..0]
|
||||
);
|
||||
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.tdf
Normal file
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.tdf
Normal file
@@ -0,0 +1,72 @@
|
||||
--------------------------------------------------------------------
|
||||
--
|
||||
-- LPM_BUSTRI Parameterized Megafunction
|
||||
--
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- Quartus II 13.1.0 Build 162 10/23/2013
|
||||
--
|
||||
-- Version 2.0
|
||||
--
|
||||
--------------------------------------------------------------------
|
||||
|
||||
SUBDESIGN lpm_bustri_BYT
|
||||
(
|
||||
tridata[8-1..0] : BIDIR;
|
||||
data[8-1..0] : INPUT = VCC;
|
||||
enabletr : INPUT = VCC;
|
||||
enabledt : INPUT = VCC;
|
||||
result[8-1..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
% Are the enable inputs used? %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[8-1..0] : TRI;
|
||||
END GENERATE;
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[8-1..0] : TRI;
|
||||
END GENERATE;
|
||||
|
||||
BEGIN
|
||||
|
||||
ASSERT (8 > 0)
|
||||
REPORT "Value of 8 parameter value must be greater than 0"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_WIDTH;
|
||||
|
||||
ASSERT (USED(enabledt) & USED(data))
|
||||
REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_DATA;
|
||||
|
||||
% Connect buffers if they are used %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[].oe = enabledt;
|
||||
dout[] = data[];
|
||||
tridata[] = dout[];
|
||||
END GENERATE;
|
||||
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[].oe = enabletr;
|
||||
din[] = tridata[];
|
||||
result[] = din[];
|
||||
ELSE GENERATE
|
||||
result[] = tridata[];
|
||||
END GENERATE;
|
||||
IF !USED(result) GENERATE
|
||||
result[] = GND;
|
||||
END GENERATE;
|
||||
END;
|
||||
78
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.v
Normal file
78
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_BYT.v
Normal file
@@ -0,0 +1,78 @@
|
||||
// Xilinx XPort Language Converter, Version 4.1 (110)
|
||||
//
|
||||
// AHDL Design Source: lpm_bustri_BYT.tdf
|
||||
// Verilog Design Output: lpm_bustri_BYT.v
|
||||
// Created 03-Mar-2014 09:18 PM
|
||||
//
|
||||
// Copyright (c) 2014, Xilinx, Inc. All Rights Reserved.
|
||||
// Xilinx Inc makes no warranty, expressed or implied, with respect to
|
||||
// the operation and/or functionality of the converted output files.
|
||||
//
|
||||
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// LPM_BUSTRI Parameterized Megafunction
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// Quartus II 13.1.0 Build 162 10/23/2013
|
||||
// Version 2.0
|
||||
// ------------------------------------------------------------------
|
||||
module lpm_bustri_BYT(tridata, data, enabletr, enabledt, result);
|
||||
input [7:0] data;
|
||||
input enabletr, enabledt;
|
||||
output [7:0] result;
|
||||
inout [7:0] tridata;
|
||||
|
||||
// Are the enable inputs used?
|
||||
wire [7:0] dout;
|
||||
wire [7:0] dout_in;
|
||||
wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
|
||||
result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
|
||||
result6_1, result6_2, result7_1, result7_2, dout0_oe_ctrl;
|
||||
|
||||
assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
|
||||
assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
|
||||
assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
|
||||
assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
|
||||
assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
|
||||
assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
|
||||
assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
|
||||
assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
|
||||
|
||||
// Start of original equations
|
||||
|
||||
// Connect buffers if they are used
|
||||
assign dout0_oe_ctrl = enabledt;
|
||||
assign dout_in = data;
|
||||
assign tridata = dout;
|
||||
assign {result7_1, result6_1, result5_1, result4_1, result3_1, result2_1,
|
||||
result1_1, result0_1} = tridata;
|
||||
assign {result7_2, result6_2, result5_2, result4_2, result3_2, result2_2,
|
||||
result1_2, result0_2} = {8{gnd}};
|
||||
|
||||
|
||||
// Assignments added to explicitly combine the
|
||||
// effects of multiple drivers in the source
|
||||
assign result[0] = result0_1 | result0_2;
|
||||
assign result[1] = result1_1 | result1_2;
|
||||
assign result[2] = result2_1 | result2_2;
|
||||
assign result[3] = result3_1 | result3_2;
|
||||
assign result[4] = result4_1 | result4_2;
|
||||
assign result[5] = result5_1 | result5_2;
|
||||
assign result[6] = result6_1 | result6_2;
|
||||
assign result[7] = result7_1 | result7_2;
|
||||
|
||||
// Define power signal(s)
|
||||
assign gnd = 1'b0;
|
||||
endmodule
|
||||
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_LONG.inc
Normal file
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_LONG.inc
Normal file
@@ -0,0 +1,24 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_bustri_LONG
|
||||
(
|
||||
data[31..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[31..0]
|
||||
);
|
||||
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_LONG.tdf
Normal file
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_LONG.tdf
Normal file
@@ -0,0 +1,72 @@
|
||||
--------------------------------------------------------------------
|
||||
--
|
||||
-- LPM_BUSTRI Parameterized Megafunction
|
||||
--
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- Quartus II 13.1.0 Build 162 10/23/2013
|
||||
--
|
||||
-- Version 2.0
|
||||
--
|
||||
--------------------------------------------------------------------
|
||||
|
||||
SUBDESIGN lpm_bustri_LONG
|
||||
(
|
||||
tridata[32-1..0] : BIDIR;
|
||||
data[32-1..0] : INPUT = VCC;
|
||||
enabletr : INPUT = VCC;
|
||||
enabledt : INPUT = VCC;
|
||||
result[32-1..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
% Are the enable inputs used? %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[32-1..0] : TRI;
|
||||
END GENERATE;
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[32-1..0] : TRI;
|
||||
END GENERATE;
|
||||
|
||||
BEGIN
|
||||
|
||||
ASSERT (32 > 0)
|
||||
REPORT "Value of 32 parameter value must be greater than 0"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_WIDTH;
|
||||
|
||||
ASSERT (USED(enabledt) & USED(data))
|
||||
REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_DATA;
|
||||
|
||||
% Connect buffers if they are used %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[].oe = enabledt;
|
||||
dout[] = data[];
|
||||
tridata[] = dout[];
|
||||
END GENERATE;
|
||||
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[].oe = enabletr;
|
||||
din[] = tridata[];
|
||||
result[] = din[];
|
||||
ELSE GENERATE
|
||||
result[] = tridata[];
|
||||
END GENERATE;
|
||||
IF !USED(result) GENERATE
|
||||
result[] = GND;
|
||||
END GENERATE;
|
||||
END;
|
||||
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.inc
Normal file
24
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.inc
Normal file
@@ -0,0 +1,24 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_bustri_WORD
|
||||
(
|
||||
data[15..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[15..0]
|
||||
);
|
||||
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.tdf
Normal file
72
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.tdf
Normal file
@@ -0,0 +1,72 @@
|
||||
--------------------------------------------------------------------
|
||||
--
|
||||
-- LPM_BUSTRI Parameterized Megafunction
|
||||
--
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- Quartus II 13.1.0 Build 162 10/23/2013
|
||||
--
|
||||
-- Version 2.0
|
||||
--
|
||||
--------------------------------------------------------------------
|
||||
|
||||
SUBDESIGN lpm_bustri_WORD
|
||||
(
|
||||
tridata[16-1..0] : BIDIR;
|
||||
data[16-1..0] : INPUT = VCC;
|
||||
enabletr : INPUT = VCC;
|
||||
enabledt : INPUT = VCC;
|
||||
result[16-1..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
% Are the enable inputs used? %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[16-1..0] : TRI;
|
||||
END GENERATE;
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[16-1..0] : TRI;
|
||||
END GENERATE;
|
||||
|
||||
BEGIN
|
||||
|
||||
ASSERT (16 > 0)
|
||||
REPORT "Value of 16 parameter value must be greater than 0"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_WIDTH;
|
||||
|
||||
ASSERT (USED(enabledt) & USED(data))
|
||||
REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
|
||||
SEVERITY ERROR
|
||||
HELP_ID LPM_BUSTRI_DATA;
|
||||
|
||||
% Connect buffers if they are used %
|
||||
IF (USED(enabledt)) GENERATE
|
||||
dout[].oe = enabledt;
|
||||
dout[] = data[];
|
||||
tridata[] = dout[];
|
||||
END GENERATE;
|
||||
|
||||
IF (USED(enabletr)) GENERATE
|
||||
din[].oe = enabletr;
|
||||
din[] = tridata[];
|
||||
result[] = din[];
|
||||
ELSE GENERATE
|
||||
result[] = tridata[];
|
||||
END GENERATE;
|
||||
IF !USED(result) GENERATE
|
||||
result[] = GND;
|
||||
END GENERATE;
|
||||
END;
|
||||
99
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.v
Normal file
99
FPGA_by_Gregory_Estrade/ahdl2v/lpm_bustri_WORD.v
Normal file
@@ -0,0 +1,99 @@
|
||||
// Xilinx XPort Language Converter, Version 4.1 (110)
|
||||
//
|
||||
// AHDL Design Source: lpm_bustri_WORD.tdf
|
||||
// Verilog Design Output: lpm_bustri_WORD.v
|
||||
// Created 02-Mar-2014 04:36 PM
|
||||
//
|
||||
// Copyright (c) 2014, Xilinx, Inc. All Rights Reserved.
|
||||
// Xilinx Inc makes no warranty, expressed or implied, with respect to
|
||||
// the operation and/or functionality of the converted output files.
|
||||
//
|
||||
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// LPM_BUSTRI Parameterized Megafunction
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
// Quartus II 13.1.0 Build 162 10/23/2013
|
||||
// Version 2.0
|
||||
// ------------------------------------------------------------------
|
||||
module lpm_bustri_WORD(tridata, data, enabletr, enabledt, result);
|
||||
input [15:0] data;
|
||||
input enabletr, enabledt;
|
||||
output [15:0] result;
|
||||
inout [15:0] tridata;
|
||||
|
||||
// Are the enable inputs used?
|
||||
wire [15:0] dout;
|
||||
wire [15:0] dout_in;
|
||||
wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
|
||||
result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
|
||||
result6_1, result6_2, result7_1, result7_2, result8_1, result8_2,
|
||||
result9_1, result9_2, result10_1, result10_2, result11_1, result11_2,
|
||||
result12_1, result12_2, result13_1, result13_2, result14_1,
|
||||
result14_2, result15_1, result15_2, dout0_oe_ctrl;
|
||||
|
||||
assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
|
||||
assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
|
||||
assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
|
||||
assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
|
||||
assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
|
||||
assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
|
||||
assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
|
||||
assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
|
||||
assign dout[8] = (dout0_oe_ctrl) ? dout_in[8] : 1'bz;
|
||||
assign dout[9] = (dout0_oe_ctrl) ? dout_in[9] : 1'bz;
|
||||
assign dout[10] = (dout0_oe_ctrl) ? dout_in[10] : 1'bz;
|
||||
assign dout[11] = (dout0_oe_ctrl) ? dout_in[11] : 1'bz;
|
||||
assign dout[12] = (dout0_oe_ctrl) ? dout_in[12] : 1'bz;
|
||||
assign dout[13] = (dout0_oe_ctrl) ? dout_in[13] : 1'bz;
|
||||
assign dout[14] = (dout0_oe_ctrl) ? dout_in[14] : 1'bz;
|
||||
assign dout[15] = (dout0_oe_ctrl) ? dout_in[15] : 1'bz;
|
||||
|
||||
// Start of original equations
|
||||
|
||||
// Connect buffers if they are used
|
||||
assign dout0_oe_ctrl = enabledt;
|
||||
assign dout_in = data;
|
||||
assign tridata = dout;
|
||||
assign {result15_1, result14_1, result13_1, result12_1, result11_1,
|
||||
result10_1, result9_1, result8_1, result7_1, result6_1, result5_1,
|
||||
result4_1, result3_1, result2_1, result1_1, result0_1} = tridata;
|
||||
assign {result15_2, result14_2, result13_2, result12_2, result11_2,
|
||||
result10_2, result9_2, result8_2, result7_2, result6_2, result5_2,
|
||||
result4_2, result3_2, result2_2, result1_2, result0_2} = {16{gnd}};
|
||||
|
||||
|
||||
// Assignments added to explicitly combine the
|
||||
// effects of multiple drivers in the source
|
||||
assign result[0] = result0_1 | result0_2;
|
||||
assign result[1] = result1_1 | result1_2;
|
||||
assign result[2] = result2_1 | result2_2;
|
||||
assign result[3] = result3_1 | result3_2;
|
||||
assign result[4] = result4_1 | result4_2;
|
||||
assign result[5] = result5_1 | result5_2;
|
||||
assign result[6] = result6_1 | result6_2;
|
||||
assign result[7] = result7_1 | result7_2;
|
||||
assign result[8] = result8_1 | result8_2;
|
||||
assign result[9] = result9_1 | result9_2;
|
||||
assign result[10] = result10_1 | result10_2;
|
||||
assign result[11] = result11_1 | result11_2;
|
||||
assign result[12] = result12_1 | result12_2;
|
||||
assign result[13] = result13_1 | result13_2;
|
||||
assign result[14] = result14_1 | result14_2;
|
||||
assign result[15] = result15_1 | result15_2;
|
||||
|
||||
// Define power signal(s)
|
||||
assign gnd = 1'b0;
|
||||
endmodule
|
||||
BIN
FPGA_by_Gregory_Estrade/ahdl2v/xport.exe
Normal file
BIN
FPGA_by_Gregory_Estrade/ahdl2v/xport.exe
Normal file
Binary file not shown.
Reference in New Issue
Block a user