forked from Firebee/FPGA_Config
add config from 30-11-2018
This commit is contained in:
ragnar
391
FPGA_30_11_2018/Interrupt_Handler/interrupt_handler.tdf
Normal file
391
FPGA_30_11_2018/Interrupt_Handler/interrupt_handler.tdf
Normal file
@@ -0,0 +1,391 @@
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TITLE "INTERRUPT HANDLER UND C1287";
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-- CREATED BY FREDI ASCHWANDEN
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INCLUDE "lpm_bustri_LONG.inc";
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INCLUDE "lpm_bustri_BYT.inc";
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-- Parameters Statement (optional)
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-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
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-- Subdesign Section
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SUBDESIGN interrupt_handler
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(
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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MAIN_CLK : INPUT;
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nFB_WR : INPUT;
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nFB_CS1 : INPUT;
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nFB_CS2 : INPUT;
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FB_SIZE0 : INPUT;
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FB_SIZE1 : INPUT;
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FB_ADR[31..0] : INPUT;
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FPGA_DATE[31..0] : INPUT;
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PIC_INT : INPUT;
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E0_INT : INPUT;
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DVI_INT : INPUT;
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nPCI_INTA : INPUT;
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nPCI_INTB : INPUT;
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nPCI_INTC : INPUT;
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nPCI_INTD : INPUT;
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nMFP_INT : INPUT;
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nFB_OE : INPUT;
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DSP_INT : INPUT;
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VSYNC : INPUT;
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HSYNC : INPUT;
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DMA_DRQ : INPUT;
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nRSTO : INPUT;
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nIRQ[7..2] : OUTPUT;
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INT_HANDLER_TA : OUTPUT;
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ACP_CONF[31..0] : OUTPUT;
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TIN0 : OUTPUT;
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FB_AD[31..0] : BIDIR;
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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)
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VARIABLE
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FB_B[3..0] :NODE;
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INT_CTR[31..0] :DFFE;
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INT_CTR_CS :NODE;
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INT_LATCH[31..0] :DFF;
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INT_LATCH_CS :NODE;
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INT_CLEAR[31..0] :DFF;
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INT_CLEAR_CS :NODE;
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INT_IN[31..0] :NODE;
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INT_ENA[31..0] :DFFE;
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INT_ENA_CS :NODE;
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INT_L[9..0] :DFF;
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INT_LA[9..0][3..0] :DFF;
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ACP_CONF[31..0] :DFFE;
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ACP_CONF_CS :NODE;
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FPGA_DATE_CS :NODE;
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PSEUDO_BUS_ERROR :NODE;
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UHR_AS :NODE;
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UHR_DS :NODE;
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RTC_ADR[5..0] :DFFE;
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ACHTELSEKUNDEN[2..0] :DFFE;
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WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63
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PIC_INT_SYNC[2..0] :DFF;
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INC_SEC :NODE;
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INC_MIN :NODE;
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INC_STD :NODE;
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INC_TAG :NODE;
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ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
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WINTERZEIT :NODE;
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SOMMERZEIT :NODE;
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INC_MONAT :NODE;
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INC_JAHR :NODE;
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UPDATE_ON :NODE;
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BEGIN
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-- BYT SELECT
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FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
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# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT
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# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
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FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
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# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT
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# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
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FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
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# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT
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# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
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FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
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# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
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# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
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-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
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INT_CTR[].CLK = MAIN_CLK;
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INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
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INT_CTR[] = FB_AD[];
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INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
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INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
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INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
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INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
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-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
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INT_ENA[].CLK = MAIN_CLK;
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INT_ENA[].CLRN = nRSTO;
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INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
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INT_ENA[] = FB_AD[];
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INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
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INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
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INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
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INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
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-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
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INT_CLEAR[].CLK = MAIN_CLK;
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INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
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INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
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INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
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INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
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INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
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-- INTERRUPT LATCH REGISTER READ ONLY
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INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
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-- INTERRUPT
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!nIRQ2 = HSYNC & INT_ENA[26];
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!nIRQ3 = INT_CTR0 & INT_ENA[27];
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!nIRQ4 = VSYNC & INT_ENA[28];
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!nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29];
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!nIRQ6 = !nMFP_INT & INT_ENA[30];
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!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
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PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
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# FB_ADR[19..4]==H"F8E0" -- VME
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-- # FB_ADR[19..4]==H"F920" -- PADDLE
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-- # FB_ADR[19..4]==H"F921" -- PADDLE
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-- # FB_ADR[19..4]==H"F922" -- PADDLE
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# FB_ADR[19..4]==H"FFA8" -- MFP2
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# FB_ADR[19..4]==H"FFA9" -- MFP2
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# FB_ADR[19..4]==H"FFAA" -- MFP2
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# FB_ADR[19..4]==H"FFA8" -- MFP2
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# FB_ADR[19..8]==H"F87" -- TT SCSI
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# FB_ADR[19..4]==H"FFC2" -- ST UHR
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# FB_ADR[19..4]==H"FFC3" -- ST UHR
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-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
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-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
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-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
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);
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-- IF VIDEO ADR CHANGE
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TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
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-- INTERRUPT LATCH
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INT_L[].CLK = MAIN_CLK;
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INT_L[].CLRN = nRSTO;
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INT_L0 = PIC_INT & INT_ENA[0];
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INT_L1 = E0_INT & INT_ENA[1];
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INT_L2 = DVI_INT & INT_ENA[2];
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INT_L3 = !nPCI_INTA & INT_ENA[3];
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INT_L4 = !nPCI_INTB & INT_ENA[4];
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INT_L5 = !nPCI_INTC & INT_ENA[5];
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INT_L6 = !nPCI_INTD & INT_ENA[6];
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INT_L7 = DSP_INT & INT_ENA[7];
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INT_L8 = VSYNC & INT_ENA[8];
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INT_L9 = HSYNC & INT_ENA[9];
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INT_LA[][].CLK = MAIN_CLK;
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INT_LATCH[] = H"FFFFFFFF";
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INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
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FOR I IN 0 TO 9 GENERATE
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INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
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INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
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# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
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# 15 & INT_L[I] & INT_LA[I][]>6
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# 0 & !INT_L[I] & INT_LA[I][]<9;
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INT_LATCH[I].CLK = INT_LA[I][3];
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END GENERATE;
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-- INT_IN
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INT_IN0 = PIC_INT;
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INT_IN1 = E0_INT;
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INT_IN2 = DVI_INT;
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INT_IN3 = !nPCI_INTA;
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INT_IN4 = !nPCI_INTB;
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INT_IN5 = !nPCI_INTC;
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INT_IN6 = !nPCI_INTD;
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INT_IN7 = DSP_INT;
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INT_IN8 = VSYNC;
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INT_IN9 = HSYNC;
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INT_IN[25..10] = H"0";
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INT_IN26 = HSYNC;
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INT_IN27 = INT_CTR0;
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INT_IN28 = VSYNC;
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INT_IN29 = INT_LATCH[]!=H"00000000";
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INT_IN30 = !nMFP_INT;
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INT_IN31 = DMA_DRQ;
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--***************************************************************************************
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-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
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ACP_CONF[].CLK = MAIN_CLK;
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ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4
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ACP_CONF[] = FB_AD[];
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ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
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ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
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ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
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ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
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--***************************************************************************************
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-- FPGA DATE HEX (ddmmyyyy)
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FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040"; -- $4'0000/4
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--***************************************************************************************
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--------------------------------------------------------------
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-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
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----------------------------------------------------------
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RTC_ADR[].CLK = MAIN_CLK;
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RTC_ADR[] = FB_AD[21..16];
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UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961
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UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963
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RTC_ADR[].ENA = UHR_AS & !nFB_WR;
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WERTE[][].CLK = MAIN_CLK;
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WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
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WERTE[7..0][1] = FB_AD[23..16];
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WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
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WERTE[7..0][3] = FB_AD[23..16];
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WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
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WERTE[7..0][5] = FB_AD[23..16];
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WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
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WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
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WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
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WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
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FOR I IN 10 TO 63 GENERATE
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WERTE[7..0][I] = FB_AD[23..16];
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END GENERATE;
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FOR I IN 0 TO 63 GENERATE
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WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
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END GENERATE;
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PIC_INT_SYNC[].CLK = MAIN_CLK;
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PIC_INT_SYNC[0] = PIC_INT;
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PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
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PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
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UPDATE_ON = !WERTE[7][11];
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WERTE[6][10].CLRN = GND; -- KEIN UIP
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UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF
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WERTE[2][11] = VCC; -- IMMER BINARY
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WERTE[1][11] = VCC; -- IMMER 24H FORMAT
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WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
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WERTE[7][13] = VCC; -- IMMER RICHTIG
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-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
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SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
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WERTE[0][13] = SOMMERZEIT;
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WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
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WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER
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-- ACHTELSEKUNDEN
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ACHTELSEKUNDEN[].CLK = MAIN_CLK;
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ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
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ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
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-- SEKUNDEN
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INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
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WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
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WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
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-- MINUTEN
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INC_MIN = INC_SEC & WERTE[][0]==59; --
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WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
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WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
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-- STUNDEN
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INC_STD = INC_MIN & WERTE[][2]==59;
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WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
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WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
|
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-- WOCHENTAG UND TAG
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INC_TAG = INC_STD & WERTE[][2]==23;
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WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
|
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# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
|
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ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
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# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
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# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
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# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
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WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
|
||||
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
|
||||
-- MONATE
|
||||
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
|
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WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
|
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# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
|
||||
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
|
||||
-- JAHR
|
||||
INC_JAHR = INC_MONAT & WERTE[][8]==12; --
|
||||
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
|
||||
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
|
||||
-- TRISTATE OUTPUT
|
||||
|
||||
FB_AD[31..24] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[31..24]
|
||||
# INT_ENA_CS & INT_ENA[31..24]
|
||||
# INT_LATCH_CS & INT_LATCH[31..24]
|
||||
# INT_CLEAR_CS & INT_IN[31..24]
|
||||
# ACP_CONF_CS & ACP_CONF[31..24]
|
||||
# FPGA_DATE_CS & FPGA_DATE[31..24]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
|
||||
FB_AD[23..16] = lpm_bustri_BYT(
|
||||
WERTE[][0] & RTC_ADR[]==0 & UHR_DS
|
||||
# WERTE[][1] & RTC_ADR[]==1 & UHR_DS
|
||||
# WERTE[][2] & RTC_ADR[]==2 & UHR_DS
|
||||
# WERTE[][3] & RTC_ADR[]==3 & UHR_DS
|
||||
# WERTE[][4] & RTC_ADR[]==4 & UHR_DS
|
||||
# WERTE[][5] & RTC_ADR[]==5 & UHR_DS
|
||||
# WERTE[][6] & RTC_ADR[]==6 & UHR_DS
|
||||
# WERTE[][7] & RTC_ADR[]==7 & UHR_DS
|
||||
# WERTE[][8] & RTC_ADR[]==8 & UHR_DS
|
||||
# WERTE[][9] & RTC_ADR[]==9 & UHR_DS
|
||||
# WERTE[][10] & RTC_ADR[]==10 & UHR_DS
|
||||
# WERTE[][11] & RTC_ADR[]==11 & UHR_DS
|
||||
# WERTE[][12] & RTC_ADR[]==12 & UHR_DS
|
||||
# WERTE[][13] & RTC_ADR[]==13 & UHR_DS
|
||||
# WERTE[][14] & RTC_ADR[]==14 & UHR_DS
|
||||
# WERTE[][15] & RTC_ADR[]==15 & UHR_DS
|
||||
# WERTE[][16] & RTC_ADR[]==16 & UHR_DS
|
||||
# WERTE[][17] & RTC_ADR[]==17 & UHR_DS
|
||||
# WERTE[][18] & RTC_ADR[]==18 & UHR_DS
|
||||
# WERTE[][19] & RTC_ADR[]==19 & UHR_DS
|
||||
# WERTE[][20] & RTC_ADR[]==20 & UHR_DS
|
||||
# WERTE[][21] & RTC_ADR[]==21 & UHR_DS
|
||||
# WERTE[][22] & RTC_ADR[]==22 & UHR_DS
|
||||
# WERTE[][23] & RTC_ADR[]==23 & UHR_DS
|
||||
# WERTE[][24] & RTC_ADR[]==24 & UHR_DS
|
||||
# WERTE[][25] & RTC_ADR[]==25 & UHR_DS
|
||||
# WERTE[][26] & RTC_ADR[]==26 & UHR_DS
|
||||
# WERTE[][27] & RTC_ADR[]==27 & UHR_DS
|
||||
# WERTE[][28] & RTC_ADR[]==28 & UHR_DS
|
||||
# WERTE[][29] & RTC_ADR[]==29 & UHR_DS
|
||||
# WERTE[][30] & RTC_ADR[]==30 & UHR_DS
|
||||
# WERTE[][31] & RTC_ADR[]==31 & UHR_DS
|
||||
# WERTE[][32] & RTC_ADR[]==32 & UHR_DS
|
||||
# WERTE[][33] & RTC_ADR[]==33 & UHR_DS
|
||||
# WERTE[][34] & RTC_ADR[]==34 & UHR_DS
|
||||
# WERTE[][35] & RTC_ADR[]==35 & UHR_DS
|
||||
# WERTE[][36] & RTC_ADR[]==36 & UHR_DS
|
||||
# WERTE[][37] & RTC_ADR[]==37 & UHR_DS
|
||||
# WERTE[][38] & RTC_ADR[]==38 & UHR_DS
|
||||
# WERTE[][39] & RTC_ADR[]==39 & UHR_DS
|
||||
# WERTE[][40] & RTC_ADR[]==40 & UHR_DS
|
||||
# WERTE[][41] & RTC_ADR[]==41 & UHR_DS
|
||||
# WERTE[][42] & RTC_ADR[]==42 & UHR_DS
|
||||
# WERTE[][43] & RTC_ADR[]==43 & UHR_DS
|
||||
# WERTE[][44] & RTC_ADR[]==44 & UHR_DS
|
||||
# WERTE[][45] & RTC_ADR[]==45 & UHR_DS
|
||||
# WERTE[][46] & RTC_ADR[]==46 & UHR_DS
|
||||
# WERTE[][47] & RTC_ADR[]==47 & UHR_DS
|
||||
# WERTE[][48] & RTC_ADR[]==48 & UHR_DS
|
||||
# WERTE[][49] & RTC_ADR[]==49 & UHR_DS
|
||||
# WERTE[][50] & RTC_ADR[]==50 & UHR_DS
|
||||
# WERTE[][51] & RTC_ADR[]==51 & UHR_DS
|
||||
# WERTE[][52] & RTC_ADR[]==52 & UHR_DS
|
||||
# WERTE[][53] & RTC_ADR[]==53 & UHR_DS
|
||||
# WERTE[][54] & RTC_ADR[]==54 & UHR_DS
|
||||
# WERTE[][55] & RTC_ADR[]==55 & UHR_DS
|
||||
# WERTE[][56] & RTC_ADR[]==56 & UHR_DS
|
||||
# WERTE[][57] & RTC_ADR[]==57 & UHR_DS
|
||||
# WERTE[][58] & RTC_ADR[]==58 & UHR_DS
|
||||
# WERTE[][59] & RTC_ADR[]==59 & UHR_DS
|
||||
# WERTE[][60] & RTC_ADR[]==60 & UHR_DS
|
||||
# WERTE[][61] & RTC_ADR[]==61 & UHR_DS
|
||||
# WERTE[][62] & RTC_ADR[]==62 & UHR_DS
|
||||
# WERTE[][63] & RTC_ADR[]==63 & UHR_DS
|
||||
# (0,RTC_ADR[]) & UHR_AS
|
||||
# INT_CTR_CS & INT_CTR[23..16]
|
||||
# INT_ENA_CS & INT_ENA[23..16]
|
||||
# INT_LATCH_CS & INT_LATCH[23..16]
|
||||
# INT_CLEAR_CS & INT_IN[23..16]
|
||||
# ACP_CONF_CS & ACP_CONF[23..16]
|
||||
# FPGA_DATE_CS & FPGA_DATE[23..16]
|
||||
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
|
||||
FB_AD[15..8] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[15..8]
|
||||
# INT_ENA_CS & INT_ENA[15..8]
|
||||
# INT_LATCH_CS & INT_LATCH[15..8]
|
||||
# INT_CLEAR_CS & INT_IN[15..8]
|
||||
# ACP_CONF_CS & ACP_CONF[15..8]
|
||||
# FPGA_DATE_CS & FPGA_DATE[15..8]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
|
||||
FB_AD[7..0] = lpm_bustri_BYT(
|
||||
INT_CTR_CS & INT_CTR[7..0]
|
||||
# INT_ENA_CS & INT_ENA[7..0]
|
||||
# INT_LATCH_CS & INT_LATCH[7..0]
|
||||
# INT_CLEAR_CS & INT_IN[7..0]
|
||||
# ACP_CONF_CS & ACP_CONF[7..0]
|
||||
# FPGA_DATE_CS & FPGA_DATE[7..0]
|
||||
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
|
||||
|
||||
INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
|
||||
END;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user