diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc
index 9e7ee65..5e526e2 100644
--- a/FPGA_Quartus_13.1/firebee1.sdc
+++ b/FPGA_Quartus_13.1/firebee1.sdc
@@ -132,7 +132,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}]  -min 1.500 {nFB_TA}
 set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}]  -max 1.500 [get_ports {FB*}]
 set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}]  -max 1.500 {nFB_TA}
 
-# the video RAM access
+# video RAM access
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}]
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}]
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}]
@@ -141,7 +141,7 @@ set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|a
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}]
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}]
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}]
-set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
+set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
 set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}