ragnar/FPGA_Config
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Sync with Fredi's source tree 18/04/2017

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Blitter work.
This commit is contained in:
David Gálvez
2018-04-09 17:23:44 +02:00
parent b2d17efff1
commit 343ede8328
55 changed files with 2659 additions and 4429 deletions
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140
FPGA_by_Fredi/blitter.tdf
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@@ -70,8 +70,11 @@ SUBDESIGN BLITTER
)
VARIABLE
FB_B[3..0] :NODE;
BYT :NODE;
LONGLINE :NODE;
W_ADR[18..0] :NODE;
FB_16B[1..0] :NODE;
W_A1 :DFFE;
BLITTER_CS :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_BE[1..0] :NODE;
@@ -160,30 +163,27 @@ VARIABLE
ENDMASK23_IN[143..0] :NODE;
ENDMASK23_OUT[143..0] :NODE;
ENDMASK123[127..0] :NODE;
DDR_RAM_FREE :NODE;
ENDMASKEND[15..0] :NODE;
SRC_DDR_ADR[31..0] :NODE;
DST_DDR_ADR[31..0] :NODE;
BLITTER_REQ :DFF;
-- MAIN STATE MACHINE
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- wenn ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- or NOT BYT
-- BYT UND WORD SELECT 16 BIT
BYT = !FB_SIZE1 & FB_SIZE0;
LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE
W_A1.CLK = MAIN_CLK;
W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZ<48>HLEN BEI LONG UND LINE WEGEN BURST
W_ADR[18..1] = FB_ADR[19..2];
W_ADR0 = W_A1;
FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0
FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F
BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
@@ -192,114 +192,114 @@ BEGIN
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
WREN_B = B"0";
LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24.w
BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26.w
BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
SRC_IADR[].CLK = DDRCLK0;
SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521"; -- $F8A42.w
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28.w
BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519"; -- $F8A32.w
BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A"; -- $F8A34.w
BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
DST_IADR[].CLK = DDRCLK0;
DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523"; -- $F8A46.w
DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36.w
BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524"; -- $F8A48.w
X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR;
X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w
BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
BL_HOP[] = FB_AD[31..24];
BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w
BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
-- OP LOGIC
BL_OP[].CLK = MAIN_CLK;
@@ -309,7 +309,7 @@ BEGIN
BL_LN[].CLK = MAIN_CLK;
BL_LN[6..0] = FB_AD[30..24];
BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C.w
BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w
BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C
BL_LN7.ENA = LN7CLR;
-- SKEW BYT
@@ -340,8 +340,8 @@ BEGIN
# DST_IADRL_CS & DST_IADR[15..0]
# X_INDEX_CS & X_INDEX[]
# Y_INDEX_CS & Y_INDEX[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
-----------------------------------------
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
--------------------------------------------------------------------------------------
-- SRC BUFFER LADEN
BL_SRC_BUF1[].CLK = DDRCLK0;
BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
@@ -400,7 +400,7 @@ BEGIN
BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
else
BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; -- LPM SHIFT LEFT
BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT
SHIFT_DIR = GND; -- DIR = LEFT
end if;
-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
@@ -471,15 +471,16 @@ BEGIN
END CASE;
------------ ENDMASKEN SETZEN ******************************************************************************
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[]==0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));
ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
@@ -490,7 +491,8 @@ BEGIN
ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];
ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
@@ -503,13 +505,14 @@ BEGIN
ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
-- STATE MACHINE ****************************************************************************************************
NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012
BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA!
DDR_RAM_FREE = BLITTER_DACK[]==H"0"; -- 0 WENN FREI
BLITTER_ADR[3..0] = H"0"; -- IMMER LINE
SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS SRC
DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS DST
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
-- BLITTER MAIN STATE MACHINE -----------------------------------------------
BL_SM.CLK = DDRCLK0;
CASE BL_SM IS
@@ -521,11 +524,24 @@ BEGIN
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR = VCC; -- L<>SCHEN
BL_SM = RDSRC1;
BL_SM = RDSRC0;
WHEN RDSRC0 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
ELSE
BL_SM = RDDST;
END IF;
WHEN RDSRC1 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
@@ -539,7 +555,7 @@ BEGIN
WHEN RDSRC2 => ------------------------ READ SRC2
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
@@ -552,21 +568,23 @@ BEGIN
END IF;
WHEN RDDST => ----------------------- READ DEST
IF NOT_DST_READ THEN
BL_SM = WRDST;
BL_SM = WRDSTW1;
ELSE
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BLITTER_REQ = VCC;
BL_READ_DST = VCC;
IF BLITTER_DACK0 THEN
BL_SM = WRDST;
BL_SM = WRDSTW1;
ELSE
BL_SM = RDDST;
END IF;
END IF;
WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS
BL_SM = WRDST;
WHEN WRDST => ------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_WR = DDR_RAM_FREE;
BLITTER_SIG = DDR_RAM_FREE;
BLITTER_WR = VCC;
BLITTER_REQ = VCC;
IF BLITTER_DACK0 THEN
XIINC = VCC; -- INC X_INDEX
DIINC = VCC; -- INC DEST ADR
@@ -575,7 +593,7 @@ BEGIN
BL_SM = WRDST;
END IF;
WHEN TESTZEILENENDE => ----------------- ZEILENDE?
IF BL_X_CNT[]<=(X_CNT_NODE[]) THEN -- SCHON ZEILENENDE?
IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
BL_SM = TESTFERTIG; -- ->
ELSE
@@ -583,7 +601,7 @@ BEGIN
END IF;
WHEN TESTFERTIG => --------------------- TEST AUF FERTIG
ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH
IF Y_INDEX[]>=BL_Y_CNT[] THEN -- LETZTE ZEILE?
IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA -->
ELSE
ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE