FPGA_Quartus_13.1/DSP/DSP.vhd

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+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:57 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY DSP IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nRSTO : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		nSRCS : INOUT STD_LOGIC;
+		nSRBLE : OUT STD_LOGIC;
+		nSRBHE : OUT STD_LOGIC;
+		nSRWE : OUT STD_LOGIC;
+		nSROE : OUT STD_LOGIC;
+		DSP_INT : OUT STD_LOGIC;
+		DSP_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END DSP;
+
+
+--  Architecture Body
+
+ARCHITECTURE DSP_architecture OF DSP IS
+
+	
+BEGIN
+	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	DSP_INT <= '0';
+	DSP_TA <= '0';
+	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	
+	
+END DSP_architecture;