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reformat

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This commit is contained in:
Markus Fröschle
2015-10-18 19:27:57 +00:00
parent 56adcdd218
commit 13032a8635
1 changed files with 121 additions and 117 deletions
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236
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
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@@ -59,121 +59,122 @@
-- Introduced a minor RTSn correction. -- Introduced a minor RTSn correction.
-- --
library ieee; LIBRARY ieee;
use ieee.std_logic_1164.all; USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all; USE ieee.std_logic_unsigned.ALL;
entity WF6850IP_TOP_SOC is ENTITY WF6850IP_TOP_SOC IS
port ( PORT (
CLK : in bit; CLK : IN bit;
RESETn : in bit; RESETn : in bit;
CS2n, CS1, CS0 : in bit; CS2n, CS1, CS0 : IN bit;
E : in bit; E : IN bit;
RWn : in bit; RWn : IN bit;
RS : in bit; RS : in bit;
DATA_IN : in std_logic_vector(7 downto 0); DATA_IN : IN std_logic_vector(7 DOWNTO 0);
DATA_OUT : out std_logic_vector(7 downto 0); DATA_OUT : OUT std_logic_vector(7 DOWNTO 0);
DATA_EN : out bit; DATA_EN : OUT bit;
TXCLK : in bit; TXCLK : IN bit;
RXCLK : in bit; RXCLK : IN bit;
RXDATA : in bit; RXDATA : IN bit;
CTSn : in bit; CTSn : IN bit;
DCDn : in bit; DCDn : IN bit;
IRQn : out bit; IRQn : OUT bit;
TXDATA : out bit; TXDATA : OUT bit;
RTSn : out bit RTSn : OUT bit
); );
end entity WF6850IP_TOP_SOC; END ENTITY WF6850IP_TOP_SOC;
architecture STRUCTURE of WF6850IP_TOP_SOC is ARCHITECTURE structure OF WF6850IP_TOP_SOC IS
component WF6850IP_CTRL_STATUS COMPONENT WF6850IP_CTRL_STATUS
port ( PORT (
CLK : in bit; CLK : IN bit;
RESETn : in bit; RESETn : IN bit;
CS : in bit_vector(2 downto 0); CS : IN bit_vector(2 DOWNTO 0);
E : in bit; E : IN bit;
RWn : in bit; RWn : IN bit;
RS : in bit; RS : IN bit;
DATA_IN : in bit_vector(7 downto 0); DATA_IN : IN bit_vector(7 DOWNTO 0);
DATA_OUT : out bit_vector(7 downto 0); DATA_OUT : OUT bit_vector(7 DOWNTO 0);
DATA_EN : out bit; DATA_EN : OUT bit;
RDRF : in bit; RDRF : IN bit;
TDRE : in bit; TDRE : IN bit;
DCDn : in bit; DCDn : IN bit;
CTSn : in bit; CTSn : IN bit;
FE : in bit; FE : IN bit;
OVR : in bit; OVR : IN bit;
PE : in bit; PE : IN bit;
MCLR : out bit; MCLR : OUT bit;
RTSn : out bit; RTSn : OUT bit;
CDS : out bit_vector(1 downto 0); CDS : OUT bit_vector(1 DOWNTO 0);
WS : out bit_vector(2 downto 0); WS : OUT bit_vector(2 DOWNTO 0);
TC : out bit_vector(1 downto 0); TC : OUT bit_vector(1 DOWNTO 0);
IRQn : out bit IRQn : OUT bit
); );
end component; END COMPONENT;
component WF6850IP_RECEIVE COMPONENT WF6850IP_RECEIVE
port ( PORT (
CLK : in bit; CLK : IN bit;
RESETn : in bit; RESETn : IN bit;
MCLR : in bit; MCLR : IN bit;
CS : in bit_vector(2 downto 0); CS : IN bit_vector(2 DOWNTO 0);
E : in bit; E : IN bit;
RWn : in bit; RWn : IN bit;
RS : in bit; RS : IN bit;
DATA_OUT : out bit_vector(7 downto 0); DATA_OUT : OUT bit_vector(7 DOWNTO 0);
DATA_EN : out bit; DATA_EN : OUT bit;
WS : in bit_vector(2 downto 0); WS : IN bit_vector(2 DOWNTO 0);
CDS : in bit_vector(1 downto 0); CDS : IN bit_vector(1 DOWNTO 0);
RXCLK : in bit; RXCLK : IN bit;
RXDATA : in bit; RXDATA : IN bit;
RDRF : out bit; RDRF : OUT bit;
OVR : out bit; OVR : OUT bit;
PE : out bit; PE : OUT bit;
FE : out bit FE : OUT bit
); );
end component; END COMPONENT;
component WF6850IP_TRANSMIT COMPONENT WF6850IP_TRANSMIT
port ( PORT (
CLK : in bit; CLK : IN bit;
RESETn : in bit; RESETn : IN bit;
MCLR : in bit; MCLR : IN bit;
CS : in bit_vector(2 downto 0); CS : IN bit_vector(2 DOWNTO 0);
E : in bit; E : IN bit;
RWn : in bit; RWn : IN bit;
RS : in bit; RS : IN bit;
DATA_IN : in bit_vector(7 downto 0); DATA_IN : IN bit_vector(7 DOWNTO 0);
CTSn : in bit; CTSn : IN bit;
TC : in bit_vector(1 downto 0); TC : IN bit_vector(1 DOWNTO 0);
WS : in bit_vector(2 downto 0); WS : IN bit_vector(2 DOWNTO 0);
CDS : in bit_vector(1 downto 0); CDS : IN bit_vector(1 DOWNTO 0);
TXCLK : in bit; TXCLK : IN bit;
TDRE : out bit; TDRE : OUT bit;
TXDATA : out bit TXDATA : OUT bit
); );
end component; END COMPONENT;
signal DATA_IN_I : bit_vector(7 downto 0);
signal DATA_RX : bit_vector(7 downto 0); SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0);
signal DATA_RX_EN : bit; SIGNAL DATA_RX : bit_vector(7 DOWNTO 0);
signal DATA_CTRL : bit_vector(7 downto 0); SIGNAL DATA_RX_EN : bit;
signal DATA_CTRL_EN : bit; SIGNAL DATA_CTRL : bit_vector(7 DOWNTO 0);
signal RDRF_I : bit; SIGNAL DATA_CTRL_EN : bit;
signal TDRE_I : bit; SIGNAL RDRF_I : bit;
signal FE_I : bit; SIGNAL TDRE_I : bit;
signal OVR_I : bit; SIGNAL FE_I : bit;
signal PE_I : bit; SIGNAL OVR_I : bit;
signal MCLR_I : bit; SIGNAL PE_I : bit;
signal CDS_I : bit_vector(1 downto 0); SIGNAL MCLR_I : bit;
signal WS_I : bit_vector(2 downto 0); SIGNAL CDS_I : bit_vector(1 DOWNTO 0);
signal TC_I : bit_vector(1 downto 0); SIGNAL WS_I : bit_vector(2 DOWNTO 0);
signal IRQ_In : bit; SIGNAL TC_I : bit_vector(1 DOWNTO 0);
begin SIGNAL IRQ_In : bit;
BEGIN
DATA_IN_I <= To_BitVector(DATA_IN); DATA_IN_I <= To_BitVector(DATA_IN);
DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
@@ -182,13 +183,14 @@ begin
IRQn <= '0' when IRQ_In = '0' else '1'; IRQn <= '0' when IRQ_In = '0' else '1';
I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
port map( PORT MAP
CLK => CLK, (
RESETn => RESETn, CLK => CLK,
CS(2) => CS2n, RESETn => RESETn,
CS(1) => CS1, CS(2) => CS2n,
CS(0) => CS0, CS(1) => CS1,
E => E, CS(0) => CS0,
E => E,
RWn => RWn, RWn => RWn,
RS => RS, RS => RS,
DATA_IN => DATA_IN_I, DATA_IN => DATA_IN_I,
@@ -207,10 +209,11 @@ begin
WS => WS_I, WS => WS_I,
TC => TC_I, TC => TC_I,
IRQn => IRQ_In IRQn => IRQ_In
); );
I_UART_RECEIVE: WF6850IP_RECEIVE I_UART_RECEIVE: WF6850IP_RECEIVE
port map ( PORT MAP
(
CLK => CLK, CLK => CLK,
RESETn => RESETn, RESETn => RESETn,
MCLR => MCLR_I, MCLR => MCLR_I,
@@ -230,10 +233,11 @@ begin
OVR => OVR_I, OVR => OVR_I,
PE => PE_I, PE => PE_I,
FE => FE_I FE => FE_I
); );
I_UART_TRANSMIT: WF6850IP_TRANSMIT I_UART_TRANSMIT: WF6850IP_TRANSMIT
port map ( PORT MAP
(
CLK => CLK, CLK => CLK,
RESETn => RESETn, RESETn => RESETn,
MCLR => MCLR_I, MCLR => MCLR_I,
@@ -251,5 +255,5 @@ begin
TDRE => TDRE_I, TDRE => TDRE_I,
TXCLK => TXCLK, TXCLK => TXCLK,
TXDATA => TXDATA TXDATA => TXDATA
); );
end architecture STRUCTURE; END ARCHITECTURE structure;