###########################################################################
#
# Generated by : Version 9.1 Build 222 10/21/2009 SJ Full Version
#
# Project      : firebee1
# Revision     : firebee1
#
# Date         : Sat Mar 01 15:22:38 CET 2014
#
###########################################################################
 
 
# WARNING: Ignored QSF Variable: Global TSU_REQUIREMENT = 1 ns
# WARNING: Ignored QSF Variable: Global TH_REQUIREMENT = 1 ns
# WARNING: Ignored QSF Variable: Global TPD_REQUIREMENT = 1 ns
# WARNING: Ignored QSF Variable: Global TCO_REQUIREMENT = 1 ns
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
#
# ------------------------------------------
#
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
#
# ------------------------------------------
# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical
if {![info exist ::qsta_message_posted]} {
    post_message -type warning "Original Global Fmax translated from QSF using derive_clocks"
    set ::qsta_message_posted 1
}
derive_clocks -period "30.303 ns"
#


# Original Clock Setting Name: CLK33M
create_clock -period "30.303 ns" \
             -name {CLK33M} {CLK33M}
# ---------------------------------------------

# ** Clock Latency
#    -------------

# ** Clock Uncertainty
#    -----------------

derive_clock_uncertainty

# ** Multicycles
#    -----------

# ** Cuts
#    ----

# ** Input/Output Delays
#    -------------------
# QSF: -name INPUT_MAX_DELAY 4 ns -from * -to FB_ALE
# Command requires a unique clock. Expand clock
#foreach_in_collection clk [get_clocks * ] {
#    set_input_delay -add_delay -max 4 -clock [get_object_info -name $clk] [get_ports {FB_ALE}]
#}
#set_input_delay -add_delay -max 4 -clock {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]} [get_ports {FB_ALE}]

# ** Tpd requirements
#    ----------------

# ** Setup/Hold Relationships
#    ------------------------

# ** Tsu/Th requirements
#    -------------------


# ** Tco/MinTco requirements
#    -----------------------

#
# Entity Specific Timing Assignments found in
# the Timing Analyzer Settings report panel
#
set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]

set_clock_groups -asynchronous -group { \
altpll4:b2v_inst22|altpll:altpll_component|altpll_qfk2:auto_generated|clk[0] \
} \
-group { \
altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[3] \
} \
-group { \
altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2] \
} \
-group { \
altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[1] \
} \
-group { \
altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[0] \
} \
-group { \
altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4] \
altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3] \
altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2] \
altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1] \
altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0] \
CLK33M \
} \
-group { \
altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[2] \
altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[1] \
} \
-group { \
altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[0] \
} \


set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -hold -end 1

set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -hold -end 1

set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -hold -end 1

set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -hold -end 1

set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -hold -end 1

set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -hold -end 1

# ---------------------------------------------

# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from VD -to FB_AD
# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to VA
# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to nVRAS
# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to BA
#set_max_delay -from [get_ports {VD[*]}] -to [get_ports {FB_AD[*]}] 5.000
#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {VA[*]}] 5.000
#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {nVRAS}] 5.000
#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {BA[*]}] 5.000

# Constrain the input I/O path
set_input_delay -clock CLK33M -max 5 [all_inputs]
#set_input_delay -clock CLK33M -min 4 [all_inputs]

# Constrain the output I/O path
set_output_delay -clock CLK33M -max 5 [all_outputs]
