TITLE "VIDEO MODUSE UND CLUT CONTROL";

-- CREATED BY FREDI ASCHWANDEN

INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "lpm_bustri_BYT.inc";

-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!

SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
(
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	nRSTO : INPUT;
	MAIN_CLK : INPUT;
	nFB_CS1 : INPUT;
	nFB_CS2 : INPUT;
	nFB_CS3 : INPUT;
	nFB_WR : INPUT;
	nFB_OE : INPUT;
	FB_SIZE0 : INPUT;
	FB_SIZE1 : INPUT;
	nFB_BURST : INPUT;
	FB_ADR[31..0] : INPUT;
	CLK33M : INPUT;
	CLK25M : INPUT;
	BLITTER_RUN : INPUT;
	CLK_VIDEO : INPUT;
	VR_D[8..0] : INPUT;
	VR_BUSY : INPUT;
	COLOR8 : OUTPUT;
	ACP_CLUT_RD : OUTPUT;
	COLOR1 : OUTPUT;
	FALCON_CLUT_RDH : OUTPUT;
	FALCON_CLUT_RDL : OUTPUT;
	FALCON_CLUT_WR[3..0] : OUTPUT;
	ST_CLUT_RD : OUTPUT;
	ST_CLUT_WR[1..0] : OUTPUT;
	CLUT_MUX_ADR[3..0] : OUTPUT;
	HSYNC : OUTPUT;
	VSYNC : OUTPUT;
	nBLANK : OUTPUT;
	nSYNC : OUTPUT;
	nPD_VGA : OUTPUT;
	FIFO_RDE : OUTPUT;
	COLOR2 : OUTPUT;
	COLOR4 : OUTPUT;
	PIXEL_CLK : OUTPUT;
	CLUT_OFF[3..0] : OUTPUT;
	BLITTER_ON : OUTPUT;
	VIDEO_RAM_CTR[15..0] : OUTPUT;
	VIDEO_MOD_TA : OUTPUT;
	CCR[23..0] : OUTPUT;
	CCSEL[2..0] : OUTPUT;
	ACP_CLUT_WR[3..0] : OUTPUT;
	INTER_ZEI : OUTPUT;
	DOP_FIFO_CLR : OUTPUT;
	VIDEO_RECONFIG : OUTPUT;
	VR_WR : OUTPUT;
	VR_RD : OUTPUT;
	CLR_FIFO : OUTPUT;
	DPZF_CLKENA: OUTPUT;
	FB_AD[31..0] : BIDIR;
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)

VARIABLE
	CLK17M						:DFF;
	CLK13M						:DFF;
	ACP_CLUT_CS					:NODE;
	ACP_CLUT					:NODE;
	VIDEO_PLL_CONFIG_CS			:NODE;
	VR_WR						:DFF;
	VR_DOUT[8..0]				:DFFE;
	VR_FRQ[7..0]				:DFFE;
	VIDEO_PLL_RECONFIG_CS		:NODE;
	VIDEO_RECONFIG				:DFF;
	FALCON_CLUT_CS				:NODE;
	FALCON_CLUT					:NODE;
	ST_CLUT_CS					:NODE;
	ST_CLUT						:NODE;
	FB_B[3..0]					:NODE;
	FB_16B[1..0]				:NODE;
	ST_SHIFT_MODE[2..0]			:DFFE;
	ST_SHIFT_MODE_CS			:NODE;
	FALCON_SHIFT_MODE[10..0]	:DFFE;
	FALCON_SHIFT_MODE_CS		:NODE;
	CLUT_MUX_ADR[3..0]			:DFF;
	CLUT_MUX_AV[1..0][3..0]		:DFF;
	ACP_VCTR_CS					:NODE;
	ACP_VCTR[31..0]				:DFFE;
	CCR_CS						:NODE;
	CCR[23..0]					:DFFE;
	ACP_VIDEO_ON				:NODE;
	SYS_CTR[6..0]				:DFFE;
	SYS_CTR_CS					:NODE;
	VDL_LOF[15..0]				:DFFE;
	VDL_LOF_CS					:NODE;
	VDL_LWD[15..0]				:DFFE;
	VDL_LWD_CS					:NODE;
-- DIV. CONTROL REGISTER
	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
	HSYNC						:DFF;
	HSYNC_I[7..0]				:DFF;
	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
	HSYNC_START					:DFF;
	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
	VSYNC						:DFF;
	VSYNC_I[2..0]				:DFF;
	nBLANK						:DFF;
	DISP_ON						:DFF;
	DPO_ZL						:DFF;
	DPO_ON						:DFF;
	DPO_OFF						:DFF;
	VDTRON						:DFF;
	VDO_ZL						:DFF;
	VDO_ON						:DFF;
	VDO_OFF						:DFF;
	VHCNT[12..0]				:DFF;
	SUB_PIXEL_CNT[6..0]			:DFFE;
	VVCNT[12..0]				:DFFE;
	VERZ[2..0][9..0]			:DFF;
	RAND[6..0]					:DFF;
	RAND_ON						:NODE;
	FIFO_RDE					:DFF;
	CLR_FIFO					:DFFE;
	START_ZEILE					:DFFE;
	SYNC_PIX					:DFF;
	SYNC_PIX1					:DFF;
	SYNC_PIX2					:DFF;
	CCSEL[2..0]					:DFF;
	COLOR16						:NODE;
	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
	TE							:NODE;
-- HORIZONTAL
	RAND_LINKS[12..0]			:NODE;
	HDIS_START[12..0]			:NODE;
	STARTP[12..0]				:NODE; 
	HDIS_END[12..0]				:NODE;  
	RAND_RECHTS[12..0]			:NODE;
	MULF[12..0]					:NODE;
	HS_START[12..0]				:NODE;
	H_TOTAL[12..0]				:NODE;
	HDIS_LEN[12..0]				:NODE;
	WPL[15..0]					:NODE;
	VDL_HHT[12..0]				:DFFE;
	VDL_HHT_CS					:NODE;
	VDL_HBE[12..0]				:DFFE;
	VDL_HBE_CS					:NODE;
	VDL_HDB[12..0]				:DFFE;
	VDL_HDB_CS					:NODE;
	VDL_HDE[12..0]				:DFFE;
	VDL_HDE_CS					:NODE;
	VDL_HBB[12..0]				:DFFE;
	VDL_HBB_CS					:NODE;
	VDL_HSS[12..0]				:DFFE;
	VDL_HSS_CS					:NODE;
-- VERTIKAL
	RAND_OBEN[12..0]			:NODE; 
	VDIS_START[12..0]			:NODE; 
	VDIS_END[12..0]				:NODE; 
	RAND_UNTEN[12..0]			:NODE; 
	VS_START[12..0]				:NODE; 
	V_TOTAL[12..0]				:NODE;  
	FALCON_VIDEO				:NODE;
	ST_VIDEO					:NODE;
	INTER_ZEI					:DFF;
	DOP_FIFO_CLR				:DFF;
	
	VIDEL_CS					:NODE;
	VDL_VBE[12..0]				:DFFE;
	VDL_VBE_CS					:NODE;
	VDL_VDB[12..0]				:DFFE;
	VDL_VDB_CS					:NODE;
	VDL_VDE[12..0]				:DFFE;
	VDL_VDE_CS					:NODE;
	VDL_VBB[12..0]				:DFFE;
	VDL_VBB_CS					:NODE;
	VDL_VSS[12..0]				:DFFE;
	VDL_VSS_CS					:NODE;
	VDL_VFT[12..0]				:DFFE;
	VDL_VFT_CS					:NODE;
	VDL_VCT[12..0]				:DFFE;
	VDL_VCT_CS					:NODE;
	VDL_VMD[3..0]				:DFFE;
	VDL_VMD_CS					:NODE;
	VDL_BPP_CS					:NODE;
	VDL_PH_CS					:NODE;
	VDL_PV_CS					:NODE;

BEGIN
-- BYT SELECT 32 BIT
	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-- BYT SELECT 16 BIT
	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
	FB_16B1 = FB_ADR[0]==1									-- ADR==1
		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
-- VIDEL CS
	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
-- ACP CLUT --
	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
	CLUT_TA.CLK = MAIN_CLK;
	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
	ST_SHIFT_MODE[].CLK = MAIN_CLK;
	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
	ST_SHIFT_MODE[] = FB_AD[26..24];
	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
-- FALCON SHIFT MODE
	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
	FALCON_SHIFT_MODE[] = FB_AD[26..16];
	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
	ACP_VCTR[].CLK = MAIN_CLK;
	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
	ACP_VCTR[31..8] = FB_AD[31..8];
	ACP_VCTR[5..0] = FB_AD[5..0];
	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
	ACP_VIDEO_ON = ACP_VCTR0;
	nPD_VGA = ACP_VCTR1;
-- VIDEO PLL CONFIG
	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
	VR_WR.CLK = MAIN_CLK;
	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
	VR_DOUT[].CLK = MAIN_CLK;
	VR_DOUT[].ENA = !VR_BUSY;
	VR_DOUT[] = VR_D[];
	VR_FRQ[].CLK = MAIN_CLK;
	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
	VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
	VIDEO_RECONFIG.CLK = MAIN_CLK;
	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN	
	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
	FALCON_VIDEO	   = ACP_VCTR7;
	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
	CCSEL[].CLK = PIXEL_CLK;
	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
			# B"001" & FALCON_CLUT
			# B"100" & ACP_CLUT
			# B"101" & COLOR16
			# B"110" & COLOR24
			# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
	CCR[].CLK = MAIN_CLK;
	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
	CCR[] = FB_AD[23..0];
	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
	SYS_CTR[].CLK = MAIN_CLK;
	SYS_CTR[6..0] = FB_AD[22..16];
	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
	BLITTER_ON = SYS_CTR3;
--VDL_LOF
	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
	VDL_LOF[].CLK = MAIN_CLK;
	VDL_LOF[] = FB_AD[31..16];
	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
	VDL_LWD[].CLK = MAIN_CLK;
	VDL_LWD[] = FB_AD[31..16];
	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
-- DATEN AUFLÖSUNG
	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
-- HORIZONTAL
-- VDL_HHT
	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
	VDL_HHT[].CLK = MAIN_CLK;
	VDL_HHT[] = FB_AD[28..16];
	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
	VDL_HBE[].CLK = MAIN_CLK;
	VDL_HBE[] = FB_AD[28..16];
	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
	VDL_HDB[].CLK = MAIN_CLK;
	VDL_HDB[] = FB_AD[28..16];
	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
	VDL_HDE[].CLK = MAIN_CLK;
	VDL_HDE[] = FB_AD[28..16];
	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
	VDL_HBB[].CLK = MAIN_CLK;
	VDL_HBB[] = FB_AD[28..16];
	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
	VDL_HSS[].CLK = MAIN_CLK;
	VDL_HSS[] = FB_AD[28..16];
	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
	VDL_VBE[].CLK = MAIN_CLK;
	VDL_VBE[] = FB_AD[28..16];
	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
	VDL_VDB[].CLK = MAIN_CLK;
	VDL_VDB[] = FB_AD[28..16];
	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
	VDL_VDE[].CLK = MAIN_CLK;
	VDL_VDE[] = FB_AD[28..16];
	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
	VDL_VBB[].CLK = MAIN_CLK;
	VDL_VBB[] = FB_AD[28..16];
	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
	VDL_VSS[].CLK = MAIN_CLK;
	VDL_VSS[] = FB_AD[28..16];
	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
	VDL_VFT[].CLK = MAIN_CLK;
	VDL_VFT[] = FB_AD[28..16];
	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
	VDL_VCT[].CLK = MAIN_CLK;
	VDL_VCT[] = FB_AD[28..16];
	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
	VDL_VMD[].CLK = MAIN_CLK;
	VDL_VMD[] = FB_AD[19..16];
	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
	FB_AD[31..16] = lpm_bustri_WORD(
						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
					  # VDL_LOF_CS 				& VDL_LOF[]
					  # VDL_LWD_CS 				& WPL[]
					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
					  # VDL_PH_CS  				& (0,HDIS_LEN[])
					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
 					  #	CCR_CS 					& (0,CCR[23..16])
 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
 	FB_AD[15..0] = lpm_bustri_WORD(
 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
 					  #	CCR_CS 					& CCR[15..0]
 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
	CLK17M.CLK = CLK33M;
	CLK17M = !CLK17M;
	CLK13M.CLK = CLK25M;
	CLK13M = !CLK13M;
	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9]
			#	CLK33M    & !ACP_VIDEO_ON & !FALCON_VIDEO & !ST_VIDEO;
-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -----------------------------------------------------
	HSY_LEN[].CLK = MAIN_CLK;		
	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
-- MULTIPLIKATIONS FAKTOR ----------------------------------------
 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
 -- BREITE IN PIXELN ------------------------------------------------	 	
	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
			   #  640 & !TE							& !ACP_VIDEO_ON
			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
-- DOPPELZEILENMODUS ---------------------------------------------
	INTER_ZEI.CLK = PIXEL_CLK;
	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
	DOP_FIFO_CLR.CLK = PIXEL_CLK;
	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER UNGERADEN ZEILEN
	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN FÜR DOP.ZEI.FIFO
-- TIMING HORIZONTAL				
	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
					# ((VDL_HHT[] + 2 + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
					# ((VDL_HHT[] + 2 + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
-- TIMING VERTICAL 					
	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-- ZÄHLER ---------------------------------------------------------------------------
	LAST.CLK = PIXEL_CLK;
	LAST = VHCNT[]==(H_TOTAL[] - 1);
	VHCNT[].CLK = PIXEL_CLK;
	VHCNT[] = (VHCNT[] + 1) & !LAST;
	VVCNT[].CLK = PIXEL_CLK;
	VVCNT[].ENA = LAST;
	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
-- DISPLAY ON OFF
	DPO_ZL.CLK = PIXEL_CLK;
	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
	DPO_ON.CLK = PIXEL_CLK;
	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
	DPO_OFF.CLK = PIXEL_CLK;
	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
	DISP_ON.CLK = PIXEL_CLK;
	DISP_ON = DISP_ON & !DPO_OFF 
			# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
	VDO_ON.CLK = PIXEL_CLK;
	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
	VDO_OFF.CLK = PIXEL_CLK;
	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
	VDO_ZL.CLK = PIXEL_CLK;
	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
	VDTRON.CLK = PIXEL_CLK;
	VDTRON = VDTRON & !VDO_OFF
		   # VDO_ON & VDO_ZL;
-- VERZÖGERUNG UND SYNC	
	HSYNC_START.CLK = PIXEL_CLK;
	HSYNC_START = VHCNT[]==HS_START[] - 2;
	HSYNC_I[].CLK = PIXEL_CLK;
	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
	VSYNC_I[].CLK = PIXEL_CLK;
	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
	VSYNC_I[].CLK = PIXEL_CLK;
	VERZ[][].CLK = PIXEL_CLK;
	VERZ[][1] = VERZ[][0];
	VERZ[][2] = VERZ[][1];
	VERZ[][3] = VERZ[][2];
	VERZ[][4] = VERZ[][3];
	VERZ[][5] = VERZ[][4];
	VERZ[][6] = VERZ[][5];
	VERZ[][7] = VERZ[][6];
	VERZ[][8] = VERZ[][7];
	VERZ[][9] = VERZ[][8];
	VERZ[0][0] = DISP_ON;
	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
				# VDL_VCT6 & HSYNC_I[]==0; -- positive sync
	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
				# VDL_VCT5 & VSYNC_I[]==0; -- positive sync	
	nBLANK.CLK = PIXEL_CLK;
	nBLANK =  VERZ[0][8];
	HSYNC.CLK = PIXEL_CLK;
	HSYNC  =  VERZ[1][9];
	VSYNC.CLK = PIXEL_CLK;
	VSYNC  =  VERZ[2][9];
	nSYNC  = GND;
-- RANDFARBE MACHEN ------------------------------------
	RAND[].CLK = PIXEL_CLK;
	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
	RAND[1] = RAND[0];
	RAND[2] = RAND[1];
	RAND[3] = RAND[2];
	RAND[4] = RAND[3];
	RAND[5] = RAND[4];
	RAND[6] = RAND[5];
	RAND_ON = RAND[6];
----------------------------------------------------------
	CLR_FIFO.CLK = PIXEL_CLK;
	CLR_FIFO.ENA = LAST;
	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE LÖSCHEN (GENUG FRÜH DAMIT ES GEFÜLLT WERDEN KANN BIS ZUR NEUEN ÜBERTRAGUNG) 
	START_ZEILE.CLK = PIXEL_CLK;
	START_ZEILE.ENA = LAST;
	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
	SYNC_PIX.CLK = PIXEL_CLK;
	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
	SYNC_PIX1.CLK = PIXEL_CLK;
	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
	SYNC_PIX2.CLK = PIXEL_CLK;
	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
	FIFO_RDE.CLK = PIXEL_CLK;	
	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
	
	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
END;
