-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:20 2009

library work;
use work.FalconIO_SDCard_IDE_CF_pkg.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


--  Entity Declaration


--  Entity Declaration

ENTITY FalconIO_SDCard_IDE_CF IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CLK33M : IN STD_LOGIC;
		MAIN_CLK : IN STD_LOGIC;
		CLK2M : IN STD_LOGIC;
		CLK500k : IN STD_LOGIC;
		nFB_CS1 : IN STD_LOGIC;
		FB_SIZE0 : IN STD_LOGIC;
		FB_SIZE1 : IN STD_LOGIC;
		nFB_BURST : IN STD_LOGIC;
		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
		LP_BUSY : IN STD_LOGIC;
		nACSI_DRQ : IN STD_LOGIC;
		nACSI_INT : IN STD_LOGIC;
		nSCSI_DRQ : IN STD_LOGIC;
		nSCSI_MSG : IN STD_LOGIC;
		MIDI_IN : IN STD_LOGIC;
		RxD : IN STD_LOGIC;
		CTS : IN STD_LOGIC;
		RI : IN STD_LOGIC;
		DCD : IN STD_LOGIC;
		AMKB_RX : IN STD_LOGIC;
		PIC_AMKB_RX : IN STD_LOGIC;
		IDE_RDY : IN STD_LOGIC;
		IDE_INT : IN STD_LOGIC;
		WP_CS_CARD : IN STD_LOGIC;
		nINDEX : IN STD_LOGIC;
		TRACK00 : IN STD_LOGIC;
		nRD_DATA : IN STD_LOGIC;
		nDCHG : IN STD_LOGIC;
		SD_DATA0 : IN STD_LOGIC;
		SD_DATA1 : IN STD_LOGIC;
		SD_DATA2 : IN STD_LOGIC;
		SD_CARD_DEDECT : IN STD_LOGIC;
		SD_WP : IN STD_LOGIC;
		nDACK0 : IN STD_LOGIC;
		nFB_WR : INOUT STD_LOGIC;
		WP_CF_CARD : IN STD_LOGIC;
		nWP : IN STD_LOGIC;
		nFB_CS2 : IN STD_LOGIC;
		nRSTO : IN STD_LOGIC;
		HD_DD : IN STD_LOGIC;
		nSCSI_C_D : IN STD_LOGIC;
		nSCSI_I_O : IN STD_LOGIC;
		CLK2M4576 : IN STD_LOGIC;
		nFB_OE : IN STD_LOGIC;
		VSYNC : IN STD_LOGIC;
		HSYNC : IN STD_LOGIC;
		DSP_INT : IN STD_LOGIC;
		nBLANK : IN STD_LOGIC;
		FDC_CLK : IN STD_LOGIC;
		FB_ALE : IN STD_LOGIC;
		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
		nIDE_CS1 : OUT STD_LOGIC;
		nIDE_CS0 : OUT STD_LOGIC;
		LP_STR : OUT STD_LOGIC;
		LP_DIR : OUT STD_LOGIC;
		nACSI_ACK : OUT STD_LOGIC;
		nACSI_RESET : OUT STD_LOGIC;
		nACSI_CS : OUT STD_LOGIC;
		ACSI_DIR : OUT STD_LOGIC;
		ACSI_A1 : OUT STD_LOGIC;
		nSCSI_ACK : OUT STD_LOGIC;
		nSCSI_ATN : OUT STD_LOGIC;
		SCSI_DIR : OUT STD_LOGIC;
		SD_CLK : OUT STD_LOGIC;
		YM_QA : OUT STD_LOGIC;
		YM_QC : OUT STD_LOGIC;
		YM_QB : OUT STD_LOGIC;
		nSDSEL : OUT STD_LOGIC;
		STEP : OUT STD_LOGIC;
		MOT_ON : OUT STD_LOGIC;
		nRP_LDS : OUT STD_LOGIC;
		nRP_UDS : OUT STD_LOGIC;
		nROM4 : OUT STD_LOGIC;
		nROM3 : OUT STD_LOGIC;
		nCF_CS1 : OUT STD_LOGIC;
		nCF_CS0 : OUT STD_LOGIC;
		nIDE_RD : INOUT STD_LOGIC;
		nIDE_WR : INOUT STD_LOGIC;
		AMKB_TX : buffer STD_LOGIC;
		IDE_RES : OUT STD_LOGIC;
		DTR : OUT STD_LOGIC;
		RTS : OUT STD_LOGIC;
		TxD : OUT STD_LOGIC;
		MIDI_OLR : OUT STD_LOGIC;
		MIDI_TLR : OUT STD_LOGIC;
		nDREQ0 : OUT STD_LOGIC;
		DSA_D : OUT STD_LOGIC;
		nMFP_INT : OUT STD_LOGIC;
		FALCON_IO_TA : OUT STD_LOGIC;
		STEP_DIR : OUT STD_LOGIC;
		WR_DATA : OUT STD_LOGIC;
		WR_GATE : OUT STD_LOGIC;
		DMA_DRQ : OUT STD_LOGIC;
		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
		SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
		SCSI_PAR : INOUT STD_LOGIC;
		nSCSI_SEL : INOUT STD_LOGIC;
		nSCSI_BUSY : INOUT STD_LOGIC;
		nSCSI_RST : INOUT STD_LOGIC;
		SD_CD_DATA3 : INOUT STD_LOGIC;
		SD_CDM_D1 : INOUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END FalconIO_SDCard_IDE_CF;


--  Architecture Body

ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
-- system
signal SYS_CLK					: STD_LOGIC;
signal RESETn					: STD_LOGIC;
signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
signal LONG						: STD_LOGIC;	-- WENN  -> 1
signal FB_ADI					: STD_LOGIC_VECTOR(15 downto 0);	-- gespeicherte writedaten
signal nResetatio				: STD_LOGIC;	-- reset atari bausteine
-- KEYBOARD MIDI
signal ACIA_CS_I				: STD_LOGIC;
signal IRQ_KEYBDn				: STD_LOGIC;
signal IRQ_MIDIn				: STD_LOGIC;
signal KEYB_RxD					: STD_LOGIC;
signal AMKB_REG					: STD_LOGIC_VECTOR(3 downto 0);
signal AMKB_TX_sync				: std_logic;
signal MIDI_OUT					: STD_LOGIC;
signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
-- MFP
signal MFP_CS					: STD_LOGIC;
signal MFP_INTACK				: STD_LOGIC;
signal LDS						: STD_LOGIC;
signal acia_irq					: STD_LOGIC;
signal DTACK_OUT_MFPn			: STD_LOGIC;
signal DINTn					: STD_LOGIC;
signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
signal TDO						: STD_LOGIC;
-- SOUND
signal SNDCS					: STD_LOGIC;
signal SNDCS_I					: STD_LOGIC;
signal SNDIR_I					: STD_LOGIC;
signal LP_DIR_X					: STD_LOGIC;
signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
signal SND_A_X					: STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
signal nLP_STR					: STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs				: STD_LOGIC;
signal sndmactl					: STD_LOGIC_VECTOR(7 downto 0);
signal sndbashi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndbasmi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndbaslo					: STD_LOGIC_VECTOR(7 downto 0);
signal sndadrhi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndadrmi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndadrlo					: STD_LOGIC_VECTOR(7 downto 0);
signal sndendhi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndendmi					: STD_LOGIC_VECTOR(7 downto 0);
signal sndendlo					: STD_LOGIC_VECTOR(7 downto 0);
signal sndmode					: STD_LOGIC_VECTOR(7 downto 0);
-- DIV
signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
signal ROM_CS					: STD_LOGIC;
-- DMA UND FLOPPY
signal DMA_DATEN_CS				: STD_LOGIC;
signal DMA_MODUS_CS				: STD_LOGIC;
signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
signal WDC_BSL_CS				: STD_LOGIC;
signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
signal HD_DD_OUT				: STD_LOGIC;
signal FDCS_In					: STD_LOGIC;
signal CA0						: STD_LOGIC;
signal CA1						: STD_LOGIC;
signal CA2						: STD_LOGIC;
signal FDINT					: STD_LOGIC;
signal FDRQ						: STD_LOGIC;
signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
signal DMA_TOP_CS				: STD_LOGIC;
signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
signal DMA_HIGH_CS				: STD_LOGIC;
signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
signal DMA_MID_CS				: STD_LOGIC;
signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
signal DMA_LOW_CS				: STD_LOGIC;
signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
signal DMA_DIRM_CS				: STD_LOGIC;
signal DMA_ADR_CS				: STD_LOGIC;
signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
signal DMA_DIR_OLD				: STD_LOGIC;
signal DMA_BYT_CNT_CS			: STD_LOGIC;
signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
signal CLR_FIFO					: STD_LOGIC;
signal DMA_DRQ_I				: STD_LOGIC;
signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
signal DMA_DRQQ					: STD_LOGIC;
signal DMA_DRQ_Q				: STD_LOGIC;
signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
signal RDF_RDE					: STD_LOGIC;
signal RDF_WRE					: STD_LOGIC;
signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
signal WRF_RDE					: STD_LOGIC;
signal WRF_WRE					: STD_LOGIC;
signal nFDC_WR					: STD_LOGIC;
type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
signal FCF_STATE				: FCF_STATES;
signal NEXT_FCF_STATE			: FCF_STATES;
signal DMA_REQ					: STD_LOGIC;
signal FDC_CS					: STD_LOGIC;
signal FCF_CS					: STD_LOGIC;
signal FCF_APH					: STD_LOGIC;
signal DMA_AZ_CS				: STD_LOGIC;
signal DMA_ACTIV				: STD_LOGIC;
signal DMA_ACTIV_NEW			: STD_LOGIC;
signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
-- SCSI
signal SCSI_CS					: STD_LOGIC;
signal SCSI_CSn					: STD_LOGIC;
signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
signal nSCSI_DACK				: STD_LOGIC;
signal SCSI_DRQ					: STD_LOGIC;
signal SCSI_INT					: STD_LOGIC;
signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
signal DB_EN					: STD_LOGIC;
signal DBP_OUTn					: STD_LOGIC;
signal DBP_EN					: STD_LOGIC;
signal RST_OUTn					: STD_LOGIC;
signal RST_EN					: STD_LOGIC;
signal BSY_OUTn					: STD_LOGIC;
signal BSY_EN					: STD_LOGIC;
signal SEL_OUTn					: STD_LOGIC;
signal SEL_EN					: STD_LOGIC;
-- IDE
signal nnIDE_RES				: STD_LOGIC;
signal IDE_CF_CS				: STD_LOGIC;
signal IDE_CF_TA				: STD_LOGIC;
signal NEXT_nIDE_RD				: STD_LOGIC;
signal NEXT_nIDE_WR				: STD_LOGIC;
type CMD_STATES is(	IDLE, T1, T6, T7);
signal CMD_STATE				: CMD_STATES;
signal NEXT_CMD_STATE			: CMD_STATES;
-- Paddle
signal paddle_cs				: STD_LOGIC;

BEGIN
LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';

FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or 
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; 
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; 
nDREQ0 <= '0';
-- input daten halten
process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
	begin
		if rising_edge(MAIN_CLK) then
			IF nFB_WR = '0' THEN
				FB_ADI <= FB_AD(31 downto 16); 
			ELSE
				FB_ADI <= FB_ADI; 
			end if;
		ELSE
			FB_ADI <= FB_ADI; 
		end if;
	END PROCESS;
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
	begin
		if nRSTO = '0' then
			CMD_STATE <= IDLE;
		elsif rising_edge(MAIN_CLK) then
				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
			else
				CMD_STATE <= CMD_STATE; 		-- halten
				nIDE_RD   <= nIDE_RD;			-- halten
				nIDE_WR   <= nIDE_WR;			-- halten
			end if;
	end process CMD_REG;

	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
	begin
		case CMD_STATE is
			when IDLE =>
				IDE_CF_TA <= '0';
				if  IDE_CF_CS = '1' then
					NEXT_nIDE_RD <= not nFB_WR;
					NEXT_nIDE_WR <=     nFB_WR;
					NEXT_CMD_STATE <= T1;
				else
					NEXT_nIDE_RD <= '1';
					NEXT_nIDE_WR <= '1';
					NEXT_CMD_STATE <= IDLE; 		 
				end if;
			when T1 =>
				IDE_CF_TA <= '0';
				NEXT_nIDE_RD <= not nFB_WR;
				NEXT_nIDE_WR <=     nFB_WR;
				NEXT_CMD_STATE <= T6;
			when T6 =>
				IF IDE_RDY = '1' then
					IDE_CF_TA <= '1';
					NEXT_nIDE_RD <= '1';
					NEXT_nIDE_WR <= '1';
					NEXT_CMD_STATE <= T7;
				else
					IDE_CF_TA <= '0';
					NEXT_nIDE_RD <= not nFB_WR;
					NEXT_nIDE_WR <=     nFB_WR;
					NEXT_CMD_STATE <= T6;
				end if;
			when T7 => 
				IDE_CF_TA <= '0';
				NEXT_nIDE_RD <= '1';
				NEXT_nIDE_WR <= '1';
				NEXT_CMD_STATE <= IDLE;
		end case;
	end process CMD_DECODER;
	
IDE_RES <= not nnIDE_RES and nRSTO;
IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772 
-------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo
	RDF: dcfifo0
		port map(
			aclr				=> CLR_FIFO,
			data				=> RDF_DIN,
			rdclk				=> MAIN_CLK,
			rdreq				=> RDF_RDE,
			wrclk				=> FDC_CLK,
			wrreq				=> RDF_WRE,
			q					=> RDF_DOUT,
			wrusedw				=> RDF_AZ
	);
FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
-- daten write fifo
	WRF: dcfifo1
		port map(
			aclr				=> CLR_FIFO,
			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
			rdclk				=> FDC_CLK,
			rdreq				=> WRF_RDE,
			wrclk				=> MAIN_CLK,
			wrreq				=> WRF_WRE,
			q					=> WRF_DOUT,
			rdusedw				=> WRF_AZ
	);
CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); 							-- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
	begin
		if nRSTO = '0' THEN
			WRF_WRE <= '0';
		elsif rising_edge(MAIN_CLK) then
				IF FCF_APH = '1' and nFB_WR = '0' then
					WRF_WRE <= '1';
				else
					WRF_WRE <= '0';
				end if;
			else
				WRF_WRE <= WRF_WRE;
			end if;
	END PROCESS;
 
FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
	begin
		if nRSTO = '0' then
			FCF_STATE <= FCF_IDLE;
			DMA_ACTIV <= '0';
		elsif rising_edge(FDC_CLK) then
				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
				DMA_ACTIV <= DMA_ACTIV_NEW;
			else
				FCF_STATE <= FCF_STATE; 					-- halten
				DMA_ACTIV <= DMA_ACTIV;
			end if;
	end process FCF_REG;

FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
	begin
		if nRSTO = '0' then
			FDC_OUT <= x"00";
		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
				FDC_OUT <= CD_OUT_FDC; 						-- set
			else
				FDC_OUT <= FDC_OUT; 						-- halten
			end if;
	end process FDC_REG;

DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';

	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
	begin
		case FCF_STATE is
			when FCF_IDLE =>
				SCSI_CSn <= '1';
				FDCS_In <= '1';
				RDF_WRE <= '0';
				WRF_RDE <= '0';
				nSCSI_DACK <= '1';
				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
					DMA_ACTIV_NEW <= DMA_REQ;
					NEXT_FCF_STATE <= FCF_T0;
				else
					DMA_ACTIV_NEW <= '0';
					NEXT_FCF_STATE <= FCF_IDLE; 		 
				end if;
			when FCF_T0 =>
				SCSI_CSn <= '1';
				FDCS_In <= '1';
				RDF_WRE <= '0';
				nSCSI_DACK <= '1';
				DMA_ACTIV_NEW <= DMA_REQ;
				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
				else
					NEXT_FCF_STATE <= FCF_T1;
				end if;
			when FCF_T1 =>
				RDF_WRE <= '0';
				WRF_RDE <= '0';
				DMA_ACTIV_NEW <= DMA_ACTIV;
				SCSI_CSn <= not SCSI_CS;
				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
				NEXT_FCF_STATE <= FCF_T2;
			when FCF_T2 =>
				RDF_WRE <= '0';
				WRF_RDE <= '0';
				DMA_ACTIV_NEW <= DMA_ACTIV;
				SCSI_CSn <= not SCSI_CS;
				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
				NEXT_FCF_STATE <= FCF_T3;
			when FCF_T3 =>
				RDF_WRE <= '0';
				WRF_RDE <= '0';
				DMA_ACTIV_NEW <= DMA_ACTIV;
				SCSI_CSn <= not SCSI_CS;
				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
				NEXT_FCF_STATE <= FCF_T6;
			when FCF_T6 =>
				WRF_RDE <= '0';
				DMA_ACTIV_NEW <= DMA_ACTIV;
				SCSI_CSn <= not SCSI_CS;
				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
				NEXT_FCF_STATE <= FCF_T7;
			when FCF_T7 =>
				SCSI_CSn <= '1';
				FDCS_In <= '1';
				RDF_WRE <= '0';
				WRF_RDE <= '0';
				nSCSI_DACK <= '1';
				DMA_ACTIV_NEW <= '0';
				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
					NEXT_FCF_STATE <= FCF_T7;
				else
					NEXT_FCF_STATE <= FCF_IDLE; 		 
				end if;
		end case;
	end process FCF_DECODER;

	I_FDC: WF1772IP_TOP_SOC
		port map(
            CLK					=> FDC_CLK,
			RESETn				=> nResetatio,
			CSn					=> FDCS_In,
			RWn					=> nFDC_WR,
			A1					=> CA2,
			A0					=> CA1,
			DATA_IN				=> CD_IN_FDC,
			DATA_OUT			=> CD_OUT_FDC,
--			DATA_EN				=> CD_EN_FDC,
			RDn					=> nRD_DATA,
			TR00n				=> TRACK00,
			IPn					=> nINDEX,
			WPRTn				=> nWP,
			DDEn				=> '0', -- Fixed to MFM.
			HDTYPE				=> HD_DD_OUT,  
			MO					=> MOT_ON,
			WG					=> WR_GATE,
			WD					=> WR_DATA,
			STEP				=> STEP,
			DIRC				=> STEP_DIR,
			DRQ					=> DMA_DRQ_I,
			INTRQ				=> FDINT 
		);
DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
	begin
		if nRSTO = '0' THEN
			WDC_BSL <= "00";
		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
			IF FB_B0 = '1' THEN
				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
			else
				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
			end if;
		end if;
	END PROCESS;
--- DMA MODUS REGISTER -------------------------------------------------------
	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
	begin
		if nRSTO = '0' THEN
			DMA_MODUS <= x"0000";
		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
			IF FB_B0 = '1' THEN
				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
			else
				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
			end if;
			IF FB_B1 = '1' THEN
				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
			else
				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
			end if;
		else
			DMA_MODUS <= DMA_MODUS;
		end if;
	END PROCESS;
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
	begin
		if nRSTO = '0' or CLR_FIFO = '1' THEN
			DMA_BYT_CNT <= x"00000000";													 
		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
				DMA_BYT_CNT(8 downto 0) <= "000000000";
			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
					DMA_BYT_CNT <= FB_AD;
				else
					DMA_BYT_CNT <= DMA_BYT_CNT;
				end if;
	END PROCESS;
--------------------------------------------------------------------
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1';													-- DMA OK
DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
-- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
	begin
		if nRSTO = '0' THEN
			DMA_DRQ_REG <= "00";
		elsif rising_edge(FDC_CLK) then
				DMA_DRQ_REG(0) <= DMA_DRQQ;
				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
			else
				DMA_DRQ_REG <= DMA_DRQ_REG;
			end if;
	END PROCESS;
-- DMA ADRESSE ------------------------------------------------------
	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
	begin
		if nRSTO = '0' THEN
			DMA_TOP <= x"00";
		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
				DMA_TOP <= FB_AD(31 downto 24);
			else 
				DMA_TOP <= DMA_TOP;
			end if;
	END PROCESS;
	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
	begin
		if nRSTO = '0' THEN
			DMA_HIGH <= x"00";
		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
				DMA_HIGH <= FB_AD(23 downto 16);
			else
				DMA_HIGH <= DMA_HIGH;
			end if;
	END PROCESS;
	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
	begin
		DMA_MID <= DMA_MID;
		if nRSTO = '0' THEN
			DMA_MID <= x"00";
		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
				if DMA_MID_CS = '1' then
					DMA_MID <= FB_AD(23 downto 16);
				elsif DMA_ADR_CS = '1' then
						DMA_MID <= FB_AD(15 downto 8);
					end if;
			end if;
	END PROCESS;
	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
	begin
		DMA_LOW <= DMA_LOW;
		if nRSTO = '0' THEN
			DMA_LOW <= x"00";
		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
				if DMA_LOW_CS = '1'then
					DMA_LOW <= FB_AD(23 downto 16);
				elsif DMA_ADR_CS = '1' then
						DMA_LOW <= FB_AD(7 downto 0);
					end if;
			end if;
	END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
	begin
		if nRSTO = '0' THEN
			DMA_DIR_OLD <= '0';
		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
				DMA_DIR_OLD <= DMA_MODUS(8);
			else
				DMA_DIR_OLD <= DMA_DIR_OLD;
			end if;
	END PROCESS;
CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
-- SCSI ----------------------------------------------------------------------------------
    I_SCSI: WF5380_TOP_SOC
        port map(
            CLK					=> FDC_CLK,
            RESETn				=> nResetatio,
			ADR			        => CA2 & CA1 & CA0,
			DATA_IN		        => CD_IN_FDC,	
			DATA_OUT			=> SCSI_DOUT,
			--DATA_EN			: out bit;
            -- Bus and DMA controls:
			CSn			        => SCSI_CSn,
			RDn		            => (not nFDC_WR) or (not SCSI_CS),
			WRn	                =>      nFDC_WR  or (not SCSI_CS),
            EOPn                => '1',
			DACKn	            => nSCSI_DACK,
			DRQ		            => SCSI_DRQ,
			INT		            => SCSI_INT,
--            READY                	=> 
            -- SCSI bus:
            DB_INn		        => SCSI_D,
            DB_OUTn		        => DB_OUTn,
            DB_EN               => DB_EN,
            DBP_INn		        => SCSI_PAR,
            DBP_OUTn	        => DBP_OUTn,
            DBP_EN              => DBP_EN,				-- wenn 1 dann output
            RST_INn             => nSCSI_RST,
            RST_OUTn            => RST_OUTn,
            RST_EN              => RST_EN,
            BSY_INn             => nSCSI_BUSY,
            BSY_OUTn            => BSY_OUTn,
            BSY_EN              => BSY_EN,
            SEL_INn             => nSCSI_SEL,
            SEL_OUTn            => SEL_OUTn,
            SEL_EN              => SEL_EN,
            ACK_INn             => '1',
            ACK_OUTn            => nSCSI_ACK,
--            ACK_EN              => ACK_EN,
            ATN_INn             => '1',
            ATN_OUTn            => nSCSI_ATN,
--            ATN_EN              => ATN_EN,
            REQ_INn             => nSCSI_DRQ,
--            REQ_OUTn            => REQ_OUTn,
--            REQ_EN              => REQ_EN,
            IOn_IN              => nSCSI_I_O,
--            IOn_OUT             => IOn_OUT,
--            IO_EN               => IO_EN,
            CDn_IN              => nSCSI_C_D,
--            CDn_OUT             => CDn_OUT,
--            CD_EN               => CD_EN,
            MSG_INn             => nSCSI_MSG
--            MSG_OUTn            => MSG_OUTn,
--            MSG_EN              => MSG_EN
        );              
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1';-- when DB_EN = '1' else '1';	 
SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
----------------------------------------------------------------------------
-- ACIA KEYBOARD
----------------------------------------------------------------------------
	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
	  port map(
			CLK					=> MAIN_CLK,
			RESETn				=> nResetatio,

			CS2n				=> FB_ADR(2),
			CS1					=> '1',
			CS0					=> ACIA_CS_I,
			E					=> ACIA_CS_I,
			RWn					=> nFB_WR,
			RS					=> FB_ADR(1),

			DATA_IN				=> FB_ADI(15 downto 8),
			DATA_OUT			=> DATA_OUT_ACIA_I,
--			DATA_EN				=> DATA_EN_ACIA_I,

			TXCLK				=> CLK500k,
			RXCLK				=> CLK500k,
			RXDATA				=> KEYB_RxD,

			CTSn				=> '0',
			DCDn				=> '0',
        
			IRQn				=> IRQ_KEYBDn,
			TXDATA				=> AMKB_TX_sync
			--RTSn				=> -- Not used.
		);                                              
ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL  // 
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I  when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else  
					   DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN  und sychronisieren ------------------------------------------
	process(CLK2M, AMKB_RX, AMKB_REG)
	begin
		if rising_edge(CLK500k) then
			AMKB_TX <= AMKB_TX_sync;
			IF AMKB_RX = '0' THEN
				IF AMKB_REG < 8 THEN
					AMKB_REG <= "0000";
				ELSE
					AMKB_REG <= AMKB_REG - 1;
				END IF;
			ELSE
				IF AMKB_REG > 7 THEN
					AMKB_REG <= "1111";
				ELSE
					AMKB_REG <= AMKB_REG + 1;
				END IF;
			END IF;
		ELSE
			AMKB_TX <= AMKB_TX;
			AMKB_REG <= AMKB_REG;
		end if;
	END PROCESS;
-- acia interrupt  ------------------------------------------
acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
	I_ACIA_MIDI: WF6850IP_TOP_SOC
		port map(
			CLK					=> MAIN_CLK,
			RESETn				=> nResetatio,

			CS2n				=> '0',
			CS1					=> FB_ADR(2),
			CS0					=> ACIA_CS_I,
            E					=> ACIA_CS_I,
			RWn					=> nFB_WR,
			RS					=> FB_ADR(1),

			DATA_IN				=> FB_ADI(15 downto 8),
			DATA_OUT			=> DATA_OUT_ACIA_II,
--			DATA_EN				=> DATA_EN_ACIA_II,

			TXCLK				=> CLK500k,
			RXCLK				=> CLK500k,
			RXDATA				=> MIDI_IN,
			CTSn				=> '0',
			DCDn				=> '0',
        
			IRQn				=> IRQ_MIDIn,
			TXDATA				=> MIDI_OUT
			--RTSn				=> -- Not used.
	    );
MIDI_TLR <= MIDI_IN;
MIDI_OLR <= MIDI_OUT;
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
	I_MFP: WF68901IP_TOP_SOC
		port map(  
			-- System control:
			CLK					=> not MAIN_CLK,
			RESETn				=> nResetatio,
			-- Asynchronous bus control:
			DSn					=> not LDS,
			CSn					=> not MFP_CS,
			RWn					=> nFB_WR,
 			DTACKn				=> DTACK_OUT_MFPn,
			-- Data and Adresses:
			RS					=> FB_ADR(5 downto 1),
			DATA_IN				=> FB_AD(23 downto 16),
			DATA_OUT			=> DATA_OUT_MFP,
--			DATA_EN				=> DATA_EN_MFP,
			GPIP_IN(7)			=> not DMA_DRQ_Q,
			GPIP_IN(6)			=> not RI,
			GPIP_IN(5)			=> DINTn,
			GPIP_IN(4)			=> acia_irq,
			GPIP_IN(3)			=> DSP_INT,
			GPIP_IN(2)			=> not CTS,
			GPIP_IN(1)			=> not DCD,
			GPIP_IN(0)			=> LP_BUSY,
			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
			-- Interrupt control:
			IACKn				=> not MFP_INTACK,
			IEIn				=> '0',
			-- IEOn				=>, -- Not used.
			IRQn				=> nMFP_INT,
			-- Timers and timer control:
			XTAL1				=> CLK2M4576,
            TAI					=> '0',
			TBI				   	=> nBLANK,
            -- TAO				=>,
			-- TBO				=>,
            -- TCO				=>,
			TDO					=> TDO,
			-- Serial I/O control:
			RC					=> TDO,
			TC					=> TDO,
			SI					=> RxD, 
			SO					=> TxD
			-- SO_EN			=> MFP_SO_EN
			-- DMA control:
			-- RRn				=>,
			-- TRn				=>
		);

MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
         '0' when FDINT = '1' else
         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
 ----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
 	I_SOUND: WF2149IP_TOP_SOC
		port map(
			SYS_CLK				=> not MAIN_CLK,
			RESETn				=> nResetatio,

			WAV_CLK				=> CLK2M,
			SELn				=> '1',

			BDIR				=> SNDIR_I,
			BC2					=> '1',
			BC1					=> SNDCS_I,

			A9n					=> '0',
			A8					=> '1',
			DA_IN				=> FB_ADI(15 downto 8),
			DA_OUT 				=> DA_OUT_X,

			IO_A_IN				=> SND_A,	
			IO_A_OUT			=> SND_A_X,
			-- IO_A_EN			=>, -- Not required.
			IO_B_IN				=> LP_D,
			IO_B_OUT			=> LP_D_X,
 --			IO_B_EN				=> IO_B_EN,

			OUT_A				=> YM_QA,
			OUT_B				=> YM_QB,
			OUT_C				=> YM_QC
		);

SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X  <= SND_A_X(6);
LP_STR    <= SND_A_X(5);
DTR       <= SND_A_X(4); 
RTS		  <= SND_A_X(3);
-- FDD_D1SEL   <= SND_A_X(2)
DSA_D	  <= SND_A_X(1);
nSDSEL    <= SND_A_X(0);
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;


----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------

dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';	-- F8900-F893F

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndmactl <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
				sndmactl <= FB_AD(23 downto 16);
			else
				sndmactl <= sndmactl;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndbashi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
				sndbashi <= FB_AD(23 downto 16);
			else
				sndbashi <= sndbashi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndbasmi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
				sndbasmi <= FB_AD(23downto 16);
			else
				sndbasmi <= sndbasmi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndbaslo <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
				sndbaslo <= FB_AD(23 downto 16);
			else
				sndbaslo <= sndbaslo;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndadrhi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
				sndadrhi <= FB_AD(23 downto 16);
			else
				sndadrhi <= sndadrhi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndadrmi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
				sndadrmi <= FB_AD(23 downto 16);
			else
				sndadrmi <= sndadrmi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndadrlo <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
				sndadrlo <= FB_AD(23 downto 16);
			else
				sndadrlo <= sndadrlo;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndendhi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
				sndendhi <= FB_AD(23 downto 16);
			else
				sndendhi <= sndendhi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndendmi <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
				sndendmi <= FB_AD(23 downto 16);
			else
				sndendmi <= sndendmi;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndendlo <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
				sndendlo <= FB_AD(23 downto 16);
			else
				sndendlo <= sndendlo;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";

	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
	begin
		if nRSTO = '0' THEN
			sndmode <= x"00";
		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
				sndmode <= FB_AD(23 downto 16);
			else
				sndmode <= sndmode;
			end if;
	END PROCESS;
FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";

----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------

paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0';	-- F9200-F923F

FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";

END FalconIO_SDCard_IDE_CF_architecture;
