-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";

CONSTANT	BL_SKEW_LF = 255;

--  Title Statement (optional)
TITLE "Blitter";


--  Parameters Statement (optional)

-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!


--  Subdesign Section

SUBDESIGN BLITTER
(
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	nRSTO : INPUT;
	MAIN_CLK : INPUT;
	FB_ALE : INPUT;
	nFB_WR : INPUT;
	nFB_OE : INPUT;
	FB_SIZE0 : INPUT;
	FB_SIZE1 : INPUT;
	VIDEO_RAM_CTR[15..0] : INPUT;
	BLITTER_ON : INPUT;
	FB_ADR[31..0] : INPUT;
	nFB_CS1 : INPUT;
	nFB_CS2 : INPUT;
	nFB_CS3 : INPUT;
	DDRCLK0 : INPUT;
	BLITTER_DIN[127..0] : INPUT;
	BLITTER_DACK[4..0] : INPUT;
	SR_BLITTER_DACK : INPUT;
	BLITTER_RUN : OUTPUT;
	BLITTER_DOUT[127..0] : OUTPUT;
	BLITTER_ADR[31..0] : OUTPUT;
	BLITTER_SIG : OUTPUT;
	BLITTER_WR : OUTPUT;
	BLITTER_TA : OUTPUT;
	FB_AD[31..0] : BIDIR;
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)

VARIABLE
	FB_B[3..0]					:NODE;
	FB_16B[1..0]				:NODE;
	BLITTER_CS					:NODE;
	BL_HRAM0_CS					:NODE;
	BL_HRAM0[15..0]				:DFFE;
	BL_HRAM1_CS					:NODE;
	BL_HRAM1[15..0]				:DFFE;
	BL_HRAM2_CS					:NODE;
	BL_HRAM2[15..0]				:DFFE;
	BL_HRAM3_CS					:NODE;
	BL_HRAM3[15..0]				:DFFE;
	BL_HRAM4_CS					:NODE;
	BL_HRAM4[15..0]				:DFFE;
	BL_HRAM5_CS					:NODE;
	BL_HRAM5[15..0]				:DFFE;
	BL_HRAM6_CS					:NODE;
	BL_HRAM6[15..0]				:DFFE;
	BL_HRAM7_CS					:NODE;
	BL_HRAM7[15..0]				:DFFE;
	BL_HRAM8_CS					:NODE;
	BL_HRAM8[15..0]				:DFFE;
	BL_HRAM9_CS					:NODE;
	BL_HRAM9[15..0]				:DFFE;
	BL_HRAMA_CS					:NODE;
	BL_HRAMA[15..0]				:DFFE;
	BL_HRAMB_CS					:NODE;
	BL_HRAMB[15..0]				:DFFE;
	BL_HRAMC_CS					:NODE;
	BL_HRAMC[15..0]				:DFFE;
	BL_HRAMD_CS					:NODE;
	BL_HRAMD[15..0]				:DFFE;
	BL_HRAME_CS					:NODE;
	BL_HRAME[15..0]				:DFFE;
	BL_HRAMF_CS					:NODE;
	BL_HRAMF[15..0]				:DFFE;
	BL_SRC_X_INC_CS				:NODE;
	BL_SRC_X_INC[15..0]			:DFFE;
	BL_SRC_Y_INC_CS				:NODE;
	BL_SRC_Y_INC[15..0]			:DFFE;
	BL_ENDMASK1_CS				:NODE;
	BL_ENDMASK1[15..0]			:DFFE;
	BL_ENDMASK2_CS				:NODE;
	BL_ENDMASK2[15..0]			:DFFE;
	BL_ENDMASK3_CS				:NODE;
	BL_ENDMASK3[15..0]			:DFFE;
	BL_SRC_ADRH_CS				:NODE;
	BL_SRC_ADRL_CS				:NODE;
	BL_SRC_ADR[31..0]			:DFFE;
	BL_DST_X_INC_CS				:NODE;
	BL_DST_X_INC[15..0]			:DFFE;
	BL_DST_Y_INC_CS				:NODE;
	BL_DST_Y_INC[15..0]			:DFFE;
	BL_DST_ADRH_CS				:NODE;
	BL_DST_ADRL_CS				:NODE;
	BL_DST_ADR[31..0]			:DFFE;
	BL_X_CNT_CS					:NODE;
	BL_X_CNT[15..0]				:DFFE;
	BL_Y_CNT_CS					:NODE;
	BL_Y_CNT[15..0]				:DFFE;
	BL_HT_OP_CS					:NODE;
	BL_HT_OP[7..0]				:DFFE;
	BL_LC_OP[7..0]				:DFFE;
	BL_LN_CS					:NODE;
	BL_LN[7..0]					:DFFE;
	BL_SKEW[7..0]				:DFFE;
	
	BL_SKEW_EXT[6..0]			:NODE;
	BL_SKEW_IN[255..0]			:DFFE;
	BL_SKEW_OUT[255..0]			:DFFE;
	
	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
	BL_READ_SRC					:DFFE;
	BL_DST_BUFFER[127..0]		:DFFE;
	BL_READ_DST					:DFFE;
	
	COUNT[18..0]				:DFF;
	
BEGIN
-- BYT SELECT 32 BIT
	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-- BYT SELECT 16 BIT
	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
	FB_16B1 = FB_ADR[0]==1									-- ADR==1
		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
-- BLITTER CS
	BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40
	BLITTER_TA = BLITTER_CS;
-- REGISTER
	-- HALFTON RAM 0
	BL_HRAM0[].CLK = MAIN_CLK;
	BL_HRAM0[15..0] = FB_AD[31..16];
	BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500";						-- $F8A00/2
	BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
	BL_HRAM0[7..0].ENA  = BL_HRAM0_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 1
	BL_HRAM1[].CLK = MAIN_CLK;
	BL_HRAM1[15..0] = FB_AD[31..16];
	BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501";						-- $F8A02/2
	BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
	BL_HRAM1[7..0].ENA  = BL_HRAM1_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 2
	BL_HRAM2[].CLK = MAIN_CLK;
	BL_HRAM2[15..0] = FB_AD[31..16];
	BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502";						-- $F8A04/2
	BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
	BL_HRAM2[7..0].ENA  = BL_HRAM2_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 3
	BL_HRAM3[].CLK = MAIN_CLK;
	BL_HRAM3[15..0] = FB_AD[31..16];
	BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503";						-- $F8A06/2
	BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
	BL_HRAM3[7..0].ENA  = BL_HRAM3_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 4
	BL_HRAM4[].CLK = MAIN_CLK;
	BL_HRAM4[15..0] = FB_AD[31..16];
	BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504";						-- $F8A08/2
	BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
	BL_HRAM4[7..0].ENA  = BL_HRAM4_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 5
	BL_HRAM5[].CLK = MAIN_CLK;
	BL_HRAM5[15..0] = FB_AD[31..16];
	BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505";						-- $F8A08/2
	BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
	BL_HRAM5[7..0].ENA  = BL_HRAM5_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 6
	BL_HRAM6[].CLK = MAIN_CLK;
	BL_HRAM6[15..0] = FB_AD[31..16];
	BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506";						-- $F8A08/2
	BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
	BL_HRAM6[7..0].ENA  = BL_HRAM6_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 7
	BL_HRAM7[].CLK = MAIN_CLK;
	BL_HRAM7[15..0] = FB_AD[31..16];
	BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507";						-- $F8A08/2
	BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
	BL_HRAM7[7..0].ENA  = BL_HRAM7_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 8
	BL_HRAM8[].CLK = MAIN_CLK;
	BL_HRAM8[15..0] = FB_AD[31..16];
	BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508";						-- $F8A10/2
	BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
	BL_HRAM8[7..0].ENA  = BL_HRAM8_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 9
	BL_HRAM9[].CLK = MAIN_CLK;
	BL_HRAM9[15..0] = FB_AD[31..16];
	BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509";						-- $F8A12/2
	BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
	BL_HRAM9[7..0].ENA  = BL_HRAM9_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 10
	BL_HRAMA[].CLK = MAIN_CLK;
	BL_HRAMA[15..0] = FB_AD[31..16];
	BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A";						-- $F8A4/2
	BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
	BL_HRAMA[7..0].ENA  = BL_HRAMA_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 11
	BL_HRAMB[].CLK = MAIN_CLK;
	BL_HRAMB[15..0] = FB_AD[31..16];
	BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B";						-- $F8A16/2
	BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
	BL_HRAMB[7..0].ENA  = BL_HRAMB_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 12
	BL_HRAMC[].CLK = MAIN_CLK;
	BL_HRAMC[15..0] = FB_AD[31..16];
	BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C";						-- $F8A18/2
	BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
	BL_HRAMC[7..0].ENA  = BL_HRAMC_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 13
	BL_HRAMD[].CLK = MAIN_CLK;
	BL_HRAMD[15..0] = FB_AD[31..16];
	BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D";						-- $F8A1A/2
	BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
	BL_HRAMD[7..0].ENA  = BL_HRAMD_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 14
	BL_HRAME[].CLK = MAIN_CLK;
	BL_HRAME[15..0] = FB_AD[31..16];
	BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E";						-- $F8A1C/2
	BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
	BL_HRAME[7..0].ENA  = BL_HRAME_CS & !nFB_WR & FB_16B1;
	-- HALFTON RAM 15
	BL_HRAMF[].CLK = MAIN_CLK;
	BL_HRAMF[15..0] = FB_AD[31..16];
	BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F";						-- $F8A1E/2
	BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
	BL_HRAMF[7..0].ENA  = BL_HRAMF_CS & !nFB_WR & FB_16B1;
	-- SRC X INC
	BL_SRC_X_INC[].CLK = MAIN_CLK;
	BL_SRC_X_INC[] = FB_AD[31..16];
	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20/2
	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
	-- SRC Y INC
	BL_SRC_Y_INC[].CLK = MAIN_CLK;
	BL_SRC_Y_INC[] = FB_AD[31..16];
	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22/2
	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
	-- SRC ADR HIGH
	BL_SRC_ADR[].CLK = MAIN_CLK;
	BL_SRC_ADR[31..16] = FB_AD[31..16];
	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
	-- SRC ADR LOW
	BL_SRC_ADR[].CLK = MAIN_CLK;
	BL_SRC_ADR[15..0] = FB_AD[31..16];
	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
	-- ENDMASK 1
	BL_ENDMASK1[].CLK = MAIN_CLK;
	BL_ENDMASK1[] = FB_AD[31..16];
	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";					-- $F8A28/2
	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
	-- ENDMASK 2
	BL_ENDMASK2[].CLK = MAIN_CLK;
	BL_ENDMASK2[] = FB_AD[31..16];
	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";					-- $F8A2A/2
	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
	-- ENDMASK 3
	BL_ENDMASK3[].CLK = MAIN_CLK;
	BL_ENDMASK3[] = FB_AD[31..16];
	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";					-- $F8A2C/2
	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
	-- DST X INC
	BL_DST_X_INC[].CLK = MAIN_CLK;
	BL_DST_X_INC[] = FB_AD[31..16];
	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";					-- $F8A2E/2
	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
	-- DST Y INC
	BL_DST_Y_INC[].CLK = MAIN_CLK;
	BL_DST_Y_INC[] = FB_AD[31..16];
	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";					-- $F8A30/2
	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
	-- DST ADR HIGH
	BL_DST_ADR[].CLK = MAIN_CLK;
	BL_DST_ADR[31..16] = FB_AD[31..16];
	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
	-- DST ADR LOW
	BL_DST_ADR[].CLK = MAIN_CLK;
	BL_DST_ADR[15..0] = FB_AD[31..16];
	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
	-- X COUNT
	BL_X_CNT[].CLK = MAIN_CLK;
	BL_X_CNT[] = FB_AD[31..16];
	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";						-- $F8A36/2
	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
	-- Y COUNT
	BL_Y_CNT[].CLK = MAIN_CLK;
	BL_Y_CNT[] = FB_AD[31..16];
	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";						-- $F8A38/2
	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
	-- HALFTONE OP BYT
	BL_HT_OP[].CLK = MAIN_CLK;
	BL_HT_OP[] = FB_AD[31..24];
	BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A/2
	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
	-- LOGIC OP BYT
	BL_LC_OP[].CLK = MAIN_CLK;
	BL_LC_OP[] = FB_AD[23..16];
	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
	-- LINE NUMBER BYT
	BL_LN[].CLK = MAIN_CLK;
	BL_LN[] = FB_AD[31..24];
	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";							-- $F8A3C/2
	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
	-- SKEW BYT
	BL_SKEW[].CLK = MAIN_CLK;
	BL_SKEW[] = FB_AD[31..24];
	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
--- REGISTER OUT
	FB_AD[31..16] = lpm_bustri_WORD(
						BL_HRAM0_CS	& BL_HRAM0[15..0]
					  #	BL_HRAM1_CS	& BL_HRAM1[15..0]
					  #	BL_HRAM2_CS	& BL_HRAM2[15..0]
					  #	BL_HRAM3_CS	& BL_HRAM3[15..0]
					  #	BL_HRAM4_CS	& BL_HRAM4[15..0]
					  #	BL_HRAM5_CS	& BL_HRAM5[15..0]
					  #	BL_HRAM6_CS	& BL_HRAM6[15..0]
					  #	BL_HRAM7_CS	& BL_HRAM7[15..0]
					  #	BL_HRAM8_CS	& BL_HRAM8[15..0]
					  #	BL_HRAM9_CS	& BL_HRAM9[15..0]
					  #	BL_HRAMA_CS	& BL_HRAMA[15..0]
					  #	BL_HRAMB_CS	& BL_HRAMB[15..0]
					  #	BL_HRAMC_CS	& BL_HRAMC[15..0]
					  #	BL_HRAMD_CS	& BL_HRAMD[15..0]
					  #	BL_HRAME_CS	& BL_HRAME[15..0]
					  #	BL_HRAMF_CS	& BL_HRAMF[15..0]
					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
					  # BL_X_CNT_CS 	& BL_X_CNT[]
					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
					  ,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); 				-- FFFF8A00-3F/40
-----------------------------------------
--  
	BL_READ_SRC.CLK = DDRCLK0;
	BL_READ_DST.CLK = DDRCLK0;

	
	BLITTER_RUN = VCC;
	BLITTER_SIG = VCC;
	BLITTER_WR = VCC;
-- READY SIGNAL 1 CLOCK SPÄTER
	BL_DATA_DDR_READY.CLK	= DDRCLK0;
	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
	BL_SKEW_IN[].CLK = DDRCLK0;
	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
	BL_SKEW_IN[255..128] = BLITTER_DIN[];
	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN	
	BL_DST_BUFFER[].CLK = DDRCLK0;
	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
	BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
	BL_SKEW_OUT[].CLK = DDRCLK0;
	BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
	
	COUNT[] = COUNT[] + 16;
	COUNT[].CLK = BLITTER_DACK0;
	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
	BLITTER_ADR[] = (0, COUNT[]) + 400000;
	
END;

