247 lines
8.0 KiB
C
247 lines
8.0 KiB
C
#ifndef _BDMOPS_H_
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#define _BDMOPS_H_
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/*
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* bdm abstraction for coldfire processors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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typedef enum CF_REGS {
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/* user registers */
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REG_D0,
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REG_D1,
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REG_D2,
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REG_D3,
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REG_D4,
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REG_D5,
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REG_D6,
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REG_D7,
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REG_A0,
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REG_A1,
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REG_A2,
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REG_A3,
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REG_A4,
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REG_A5,
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REG_A6,
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REG_A7,
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MAX_USER_REGS=REG_A7,
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/* RCREG/WCREG */
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REG_CACR,
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REG_ACR0,
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REG_ACR1,
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REG_VBR,
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REG_SR,
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REG_RPC,
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REG_RAMBAR,
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REG_MBAR,
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MAX_CONFIG_REGS=REG_MBAR,
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/* RDMREG/WDMREG */
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REG_CSR,
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REG_AATR,
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REG_TDR,
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REG_PBR,
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REG_PBMR,
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REG_ABHR,
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REG_ABLR,
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REG_DBR,
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REG_DBMR,
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MAX_DEBUG_REGS=REG_DBMR,
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MAX_REGS
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} CF_REGS;
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#ifdef REG_NAMES
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struct reg_names {
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CF_REGS id;
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const char name[8];
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} reg_names[]={
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/* user registers */
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{ REG_D0, "D0"},
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{ REG_D1, "D1"},
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{ REG_D2, "D2"},
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{ REG_D3, "D3"},
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{ REG_D4, "D4"},
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{ REG_D5, "D5"},
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{ REG_D6, "D6"},
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{ REG_D7, "D7"},
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{ REG_A0, "A0"},
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{ REG_A1, "A1"},
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{ REG_A2, "A2"},
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{ REG_A3, "A3"},
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{ REG_A4, "A4"},
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{ REG_A5, "A5"},
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{ REG_A6, "A6"},
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{ REG_A7, "A7"},
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/* RCREG/WCREG */
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{ REG_CACR, "CACR"},
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{ REG_ACR0, "ACR0"},
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{ REG_ACR1, "ACR1"},
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{ REG_VBR, "VBR"},
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{ REG_SR, "SR"},
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{ REG_RPC, "RPC"},
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{ REG_RAMBAR, "RAMBAR"},
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{ REG_MBAR, "MBAR"},
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/* RDMREG/WDMREG */
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{ REG_CSR, "CSR"},
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{ REG_AATR, "AATR"},
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{ REG_TDR, "TDR"},
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{ REG_PBR, "PBR"},
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{ REG_PBMR, "PBMR"},
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{ REG_ABHR, "ABHR"},
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{ REG_ABLR, "ABLR"},
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{ REG_DBR, "DBR"},
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{ REG_DBMR, "DBMR"},
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{ 0xffff, ""}
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};
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#endif
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/* debug module register definitions */
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/* AATR */
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#define AATR_RM (1<<15) /* Read/Write mask */
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#define AATR_SZM (3<<13) /* SiZe Mask */
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#define AATR_TTM (3<<11) /* Transfer Type Mask */
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#define AATR_TMM (7<<8) /* Transfer Modifier Mask */
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#define AATR_R (1<<7) /* Read/write */
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#define AATR_SZ (3<<5) /* SiZe */
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#define AATR_TT (3<<3) /* Tranfer Type */
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#define AATR_TM (7<<0) /* Transfer Modifier */
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/* TDR */
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#define TDR_TRC (3<<30) /* Trigger Response Control */
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#define TDR_EBL2 (1<<29) /* Enable Breakpoint Level */
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#define TDR_EDLW2 (1<<28) /* Enable Data BP for LongWord */
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#define TDR_EDWL2 (1<<27) /* Enable Data BP for Word (Upper) */
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#define TDR_EDWU2 (1<<26) /* Enable Data BP for Word (Lower) */
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#define TDR_EDLL2 (1<<25) /* Enable Data BP for byte (LL) */
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#define TDR_EDLM2 (1<<24) /* Enable Data BP for byte (LM) */
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#define TDR_EDUM2 (1<<23) /* Enable Data BP for byte (UM) */
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#define TDR_EDUU2 (1<<22) /* Enable Data BP for byte (UU) */
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#define TDR_DI2 (1<<21) /* Data breakpoint invert */
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#define TDR_EAI2 (1<<20) /* Enable Address breakpoint inverted */
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#define TDR_EAR2 (1<<19) /* Enable Address breakpoint Range */
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#define TDR_EAL2 (1<<18) /* Enable Address breakpoint Low */
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#define TDR_EPC2 (1<<17) /* Enable PC breakpoint */
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#define TDR_PCI2 (1<<16) /* PC breakpoint Invert */
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#define TDR_EBL1 (1<<13) /* Enable Breakpoint Level */
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#define TDR_EDLW1 (1<<12) /* Enable Data BP for LongWord */
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#define TDR_EDWL1 (1<<11) /* Enable Data BP for Word (Upper) */
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#define TDR_EDWU1 (1<<10) /* Enable Data BP for Word (Lower) */
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#define TDR_EDLL1 (1<<9) /* Enable Data BP for byte (LL) */
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#define TDR_EDLM1 (1<<8) /* Enable Data BP for byte (LM) */
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#define TDR_EDUM1 (1<<7) /* Enable Data BP for byte (UM) */
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#define TDR_EDUU1 (1<<6) /* Enable Data BP for byte (UU) */
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#define TDR_DI1 (1<<5) /* Data breakpoint invert */
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#define TDR_EAI1 (1<<4) /* Enable Address breakpoint inverted */
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#define TDR_EAR1 (1<<3) /* Enable Address breakpoint Range */
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#define TDR_EAL1 (1<<2) /* Enable Address breakpoint Low */
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#define TDR_EPC1 (1<<1) /* Enable PC breakpoint */
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#define TDR_PCI1 (1<<0) /* PC breakpoint Invert */
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/* CSR */
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#define CSR_STATUS (15<<28) /* breakpoint status */
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# define CSR_STAT_NOBP 0
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# define CSR_STAT_WAIT1 1
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# define CSR_STAT_TRIG1 2
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# define CSR_STAT_WAIT2 5
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# define CSR_STAT_TRIG2 6
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#define CSR_FOF (1<<27) /* Fault-On-Fault */
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#define CSR_TRG (1<<26) /* hardware breakpoint TRiGger */
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#define CSR_HALT (1<<25) /* processor HALT */
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#define CSR_BKPT (1<<24) /* BreaKPoinT assert */
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#define CSR_IPW (1<<16) /* Inhibit Processor Writes to dbg reg. */
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#define CSR_MAP (1<<15) /* MAP processor accesses in emu mode */
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#define CSR_TRC (1<<14) /* emulation mode on TRaCe exception */
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#define CSR_EMU (1<<13) /* force EMUlation mode */
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#define CSR_DDC (3<<11) /* Debug Data Control */
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#define CSR_UHE (1<<10) /* User Halt Enable */
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#define CSR_BTB (3<<8) /* Branch Target Bytes */
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#define CSR_NPL (1<<6) /* NonPipelined Mode */
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#define CSR_IPI (1<<5) /* Ignore Pending Interrupts */
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#define CSR_SSM (1<<4) /* Single Step Mode */
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/*
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* this is an abstraction layer to have a general target programming interface
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* so the programmer doesn't have to bother with motorola's bdm commands.
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*
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* applications only include bdmops.h and call the functions below
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*/
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/* open bdm-driver */
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int /* <0 if error, BDMHandle otherwise */
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bdm_init(const char *path);
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/* close driver */
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void bdm_release(int port);
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/* bring chip to running state */
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void bdm_run(void);
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/* bring chip to stopped state */
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void bdm_stop(void);
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/* step chip on instruction */
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void bdm_step(void);
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/* reset chip and hold in reset state */
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void bdm_reset(void);
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/* restart from reset to running state */
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void bdm_restart(void);
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/* read a register from the chip */
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int bdm_read_reg(CF_REGS which, unsigned long *value);
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/* write a register in the chip */
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int bdm_write_reg(CF_REGS which, unsigned long *value);
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/* read a block of memory, alignment doesn't matter anymore */
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int bdm_read_mem(unsigned int addr, unsigned char *mem, int count);
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/* write a block of memory, alignment doesn't matter anymore */
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int bdm_write_mem(unsigned int addr, unsigned char *mem, int count);
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/* set program counter break point */
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int bdm_set_pc_bp(unsigned long addr, unsigned long mask);
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int bdm_clear_pc_bp(void);
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/* set program counter break point */
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int bdm_set_addr_bp(unsigned long from_addr, unsigned long to_addr);
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int bdm_clear_addr_bp(void);
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/* set program counter break point */
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int bdm_set_data_bp(unsigned long value, unsigned long mask);
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int bdm_clear_daat_bp(void);
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/* bdm query status */
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void bdm_clear_status(void);
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int bdm_query_status(void);
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#define BDM_STAT_BKPT (1<<0)
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#define BDM_STAT_HALT (1<<1)
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#define BDM_STAT_TRG (1<<2)
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#define BDM_STAT_FOF (1<<3)
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#define BDM_STAT_SSM (1<<4)
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#define BDM_STAT_WAIT1 (1<<5)
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#define BDM_STAT_TRIG1 (1<<6)
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#define BDM_STAT_WAIT2 (1<<7)
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#define BDM_STAT_TRIG2 (1<<8)
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#define BDM_STAT_RESET (1<<9)
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#define BDM_STAT_NOPWR (1<<10)
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#define BDM_STAT_PSTHALT (1<<11)
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#define BDM_STAT_NC (1<<12)
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/* bdm wait for stopped target */
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int bdm_wait(void);
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#ifdef _COMPILING_
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# ifdef USERMODE
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int bdm_open(int minor, int flags);
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int bdm_ioctl(int minor, unsigned int request, unsigned long arg);
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int bdm_read(int minor, unsigned char *p, int count);
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int bdm_write(int minor, const unsigned char *p, int count);
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void bdm_close(int minor);
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# else
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# define bdm_open open
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# define bdm_ioctl ioctl
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# define bdm_read read
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# define bdm_write write
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# define bdm_close close
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# endif
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#endif
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#endif
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