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This commit is contained in:
Bernd Mueller
268
m68k/driver/bdm.h
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268
m68k/driver/bdm.h
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/*
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* Motorola Background Debug Mode Driver
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* Copyright (C) 1995 W. Eric Norum
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* Copyright (C) 1998 Chris Johns
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*
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* Based on:
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* 1. `A Background Debug Mode Driver Package for Motorola's
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* 16- and 32-Bit Microcontrollers', Scott Howard, Motorola
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* Canada, 1993.
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* 2. `Linux device driver for public domain BDM Interface',
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* M. Schraut, Technische Universitaet Muenchen, Lehrstuhl
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* fuer Prozessrechner, 1995.
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*
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* Extended to support the ColdFire BDM interface using the P&E
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* module which comes with the EVB. Currently only tested with the
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* 5206 (5V) device.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* W. Eric Norum
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* Saskatchewan Accelerator Laboratory
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* University of Saskatchewan
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* 107 North Road
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* Saskatoon, Saskatchewan, CANADA
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* S7N 5C6
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*
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* eric@skatter.usask.ca
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*
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* Coldfire support by:
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* Chris Johns
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* chris@contemporary.net.au
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*
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*/
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#ifndef _BDM_H_
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#define _BDM_H_
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/*
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* Version of the driver.
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*/
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#define BDM_DRV_VERSION 0x020d
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/*
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* Hook for Linux kernel
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*/
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#define BDM_MAJOR_NUMBER 34
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/*
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* Allocation of the minor numbers. The number of minors per interface
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* must be a factor of 2.
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*/
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#define BDM_MINORS_PER_IFACE 4
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#define BDM_IFACE_MINOR(m) (m & (BDM_MINORS_PER_IFACE - 1))
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#define BDM_IFACE(m) (m / BDM_MINORS_PER_IFACE)
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#define BDM_NUM_OF_MINORS (BDM_NUM_OF_IFACES * BDM_MINORS_PER_IFACE)
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/*
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* Processors
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*/
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#define BDM_CPU32 0
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#define BDM_COLDFIRE 1
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/*
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* Interfaces, used of offset the major number.
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*/
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#define BDM_CPU32_ERIC 0
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#define BDM_CPU32_PD BDM_CPU32_ERIC
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#define BDM_COLDFIRE_PE 1
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#define BDM_CPU32_ICD 2
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#define BDM_COLDFIRE_TBLCF 3
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#define BDM_NUM_OF_IFACES 4 /* last */
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/*
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* Error codes
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*/
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#define BDM_FAULT_UNKNOWN 210
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#define BDM_FAULT_POWER 211
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#define BDM_FAULT_CABLE 212
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#define BDM_FAULT_RESPONSE 213
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#define BDM_FAULT_RESET 214
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#define BDM_FAULT_PORT 215
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#define BDM_FAULT_BERR 216
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#define BDM_FAULT_NVC 217
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#define BDM_FAULT_TIMEOUT 218
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#define BDM_FAULT_FORCED_TA 219
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/*
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* Structure for I/O requests
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* Address and value are in host-endian order
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*/
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struct BDMioctl {
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unsigned long int address;
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unsigned long int value;
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};
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/*
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* The ioctl codes. If these change insure the remote client and server
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* interfaces are kept in sync. Assumes Cygwin does not define Win32.
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*/
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#if !defined (_IO)
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#if defined (__WIN32__)
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#include <winsock2.h>
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#else
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#include <sys/ioctl.h>
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#endif
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#endif
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/*
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* If the OS does not provide any ioctl support as found on
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* some Unix systems then provide something.
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*/
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#if !defined (_IO)
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#undef _IOR
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#undef _IOW
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#undef _IOWR
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#define _IO(x,y) ((x<<8)|y|0x00000)
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#define _IOR(x,y,t) ((x<<8)|y|0x10000)
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#define _IOW(x,y,t) ((x<<8)|y|0x20000)
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#define _IOWR(x,y,t) ((x<<8)|y|0x30000)
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#endif
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#if !defined (_IOWR)
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#if !defined (IOC_OUTIN)
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#define IOC_OUTIN 0x10000000 /* copy in parameters */
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#endif
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#define _IOWR(x,y,t) (IOC_OUTIN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|(x<<8)|y)
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#endif
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#define BDM_INIT _IO('B', 0)
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#define BDM_RESET_CHIP _IO('B', 1)
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#define BDM_RESTART_CHIP _IO('B', 2)
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#define BDM_STOP_CHIP _IO('B', 3)
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#define BDM_STEP_CHIP _IO('B', 4)
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#define BDM_GET_STATUS _IOR('B', 5, int)
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#define BDM_SPEED _IOW('B', 6, int)
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#define BDM_DEBUG _IOW('B', 7, int)
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#define BDM_RELEASE_CHIP _IO('B', 8)
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#define BDM_GO _IO('B', 9)
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/*
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* Input/output requests
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*/
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/*
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* Addition for general register access.
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*
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* Note, the control and debug registers has been added at the start
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* so the other allocated number do not change.
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*/
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#define BDM_READ_CTLREG _IOWR('B', 16, struct BDMioctl)
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#define BDM_WRITE_CTLREG _IOW('B', 17, struct BDMioctl)
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#define BDM_READ_DBREG _IOWR('B', 18, struct BDMioctl)
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#define BDM_WRITE_DBREG _IOW('B', 19, struct BDMioctl)
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#define BDM_READ_REG _IOWR('B', 20, struct BDMioctl)
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#define BDM_READ_SYSREG _IOWR('B', 21, struct BDMioctl)
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#define BDM_READ_LONGWORD _IOWR('B', 22, struct BDMioctl)
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#define BDM_READ_WORD _IOWR('B', 23, struct BDMioctl)
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#define BDM_READ_BYTE _IOWR('B', 24, struct BDMioctl)
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#define BDM_WRITE_REG _IOW('B', 25, struct BDMioctl)
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#define BDM_WRITE_SYSREG _IOW('B', 26, struct BDMioctl)
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#define BDM_WRITE_LONGWORD _IOW('B', 27, struct BDMioctl)
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#define BDM_WRITE_WORD _IOW('B', 28, struct BDMioctl)
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#define BDM_WRITE_BYTE _IOW('B', 29, struct BDMioctl)
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/*
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* Detect the driver version, processor or interface type
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*/
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#define BDM_GET_DRV_VER _IOR('B', 30, int)
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#define BDM_GET_CPU_TYPE _IOR('B', 31, int)
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#define BDM_GET_IF_TYPE _IOR('B', 32, int)
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/*
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* Coldfire specific call to control the use of the
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* PST signals. This is only needed on 5206e targets that
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* use the PST signals for IO.
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*/
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#define BDM_GET_CF_PST _IOR('B', 33, int)
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#define BDM_SET_CF_PST _IOR('B', 34, int)
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/*
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* bits in status word returned by BDM_GET_STATUS ioctl
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*/
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#define BDM_TARGETRESET (1 << 0) /* Target reset */
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#define BDM_TARGETHALT (1 << 1) /* Target halt */
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#define BDM_TARGETSTOPPED (1 << 2) /* Target stopped */
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#define BDM_TARGETPOWER (1 << 3) /* Power failed */
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#define BDM_TARGETNC (1 << 4) /* Target not connected */
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/*
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* Register codes for BDM_READ_SYSREG/BDM_WRITE_SYSREG ioctls
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*
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* These are the control and debug registers for the CPU32 and
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* Coldfire processor.
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*
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* These are ony logical numbers not the actual registers values used
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* on the BDM port. The driver maps these to the correct command and
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* register pair .
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*
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* Using only the one call keeps the changes to Eric's library and gdb
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* code to a minimum.
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*
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* The WR only registers are shadowed in the driver.
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*/
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#define BDM_REG_RPC 0x0 /* CPU32, Coldfire */
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#define BDM_REG_PCC 0x1 /* CPU32 */
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#define BDM_REG_SR 0x2 /* CPU32, Coldfire */
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#define BDM_REG_USP 0x3 /* CPU32 */
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#define BDM_REG_SSP 0x4 /* CPU32 */
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#define BDM_REG_SFC 0x5 /* CPU32 */
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#define BDM_REG_DFC 0x6 /* CPU32 */
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#define BDM_REG_ATEMP 0x7 /* CPU32 */
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#define BDM_REG_FAR 0x8 /* CPU32 */
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#define BDM_REG_VBR 0x9 /* CPU32, Coldfire */
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#define BDM_REG_CACR 0xa /* Coldfire */
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#define BDM_REG_ACR0 0xb /* Coldfire */
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#define BDM_REG_ACR1 0xc /* Coldfire */
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#define BDM_REG_RAMBAR 0xd /* Coldfire */
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#define BDM_REG_MBAR 0xe /* Coldfire */
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#define BDM_REG_CSR 0xf /* Coldfire */
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#define BDM_REG_AATR 0x10 /* WR only, Coldfire */
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#define BDM_REG_TDR 0x11 /* WR only, Coldfire */
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#define BDM_REG_PBR 0x12 /* WR only, Coldfire */
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#define BDM_REG_PBMR 0x13 /* WR only, Coldfire */
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#define BDM_REG_ABHR 0x14 /* WR only, Coldfire */
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#define BDM_REG_ABLR 0x15 /* WR only, Coldfire */
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#define BDM_REG_DBR 0x16 /* WR only, Coldfire */
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#define BDM_REG_DBMR 0x17 /* WR only, Coldfire */
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#define BDM_MAX_SYSREG (BDM_REG_DBMR + 1)
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/*
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* Register codes for BDM_READ_REG/BDM_WRITE_REG ioctls
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*/
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#define BDM_REG_D0 0x0
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#define BDM_REG_D1 0x1
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#define BDM_REG_D2 0x2
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#define BDM_REG_D3 0x3
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#define BDM_REG_D4 0x4
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#define BDM_REG_D5 0x5
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#define BDM_REG_D6 0x6
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#define BDM_REG_D7 0x7
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#define BDM_REG_A0 0x8
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#define BDM_REG_A1 0x9
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#define BDM_REG_A2 0xa
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#define BDM_REG_A3 0xb
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#define BDM_REG_A4 0xc
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#define BDM_REG_A5 0xd
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#define BDM_REG_A6 0xe
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#define BDM_REG_A7 0xf /* use this for the stack pointer */
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#endif /* _BDM_H_ */
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