initial push
This commit is contained in:
Bernd Mueller
335
m683xx/scripts/run332.gdb
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335
m683xx/scripts/run332.gdb
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# invoke by "source run376.gdb"
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echo Setting bdm\n
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#set prompt (gdb68)
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file tst
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target bdm /dev/bdm
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#target bdm /dev/icd_bdm0
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#target bdm /dev/pd_bdm0
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#===========================================================
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# sets chipselects and configuration
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define bdm_hw_init
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echo bdm_hw_init ...\n
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set remotecache off
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bdm_timetocomeup 0
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bdm_autoreset off
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bdm_setdelay 100
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bdm_reset
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bdm_setdelay 0
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set $sfc=5
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set $dfc=5
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# system configuration
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# 0xFFFA00 - SIMCR - SIM Configuration Register
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# 15 14 13 12 11 10 9 8 7 6 5 4 3 0
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# EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB
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# 0 0 0 0 DATA11 0 0 0 1 1 0 0 1 1 1 1
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set *(short *)0xfffa00=0x42cf
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# 0xFFFA21 - SYPCR - System Protection Control Register
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# 7 6 5 4 3 2 1 0
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# SWE SWP SWT HME BME BMT
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# 1 MODCLK 0 0 0 0 0 0
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set *(char *)0xfffa21=0x06
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# 0xYFFA27 - SWSR - Software Service Register
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# write 0x55 0xAA for watchdog
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# 0xFFFA04 - SYNCR Clock Synthesizer Control Register
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# 15 14 13 8 7 6 5 4 3 2 1 0
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# W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT
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# 0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0
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set *(short *)0xfffa04=0x7f00
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# $YFFA17 - PEPAR - Port E Pin Assignment Register
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# 7 6 5 4 3 2 1 0
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# PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
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# SIZ1 SIZ0 AS DS RMC AVEC DSACK1 DSACK0
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# 1 .. control signal, 0 .. port F
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# after reset determined by DATA8
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set *(char*)0xfffa17=0xf4
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# 0xFFFA1F - PFPAR - Port F Pin Assignment Register
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# 7 6 5 4 3 2 1 0
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# PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0
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# INT7 INT6 INT5 INT4 INT3 INT2 INT1 MODCLK
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# 1 .. control signal, 0 .. port F
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# after reset determined by DATA9
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set *(char*)0xfffa1f=0
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# Setup internal RAM
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# setup TPU RAM at 0x8000
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# TRAMMCR
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set *(short *)0xFFFB00=0x8000
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# TRAMBAR
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set *(short *)0xFFFB04=0xFFE000>>8
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# TRAMMCR
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set *(short *)0xFFFB00=0
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# 0xYFFA44 - CSPAR0 - Chip Select Pin Assignment Register 0
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# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 0 0 CSPA0[6] CSPA0[5] CSPA0[4] CSPA0[3] CSPA0[2] CSPA0[1] CSBOOT
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# 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATA0
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# CS5 CS4 CS3 CS2 CS1 CS0 CSBOOT
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# FC2 PC2 FC1 PC1 FC0 PC0 BGACK BG BR
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#
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# 00 Discrete Output
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# 01 Alternate Function
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# 10 Chip Select (8-Bit Port)
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# 11 Chip Select (16-Bit Port)
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#
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set *(short *)0xfffa44=0x3fff
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# 0xFFFA46 - CSPAR1 - Chip Select Pin Assignment Register 1
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# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 0 0 0 0 0 0 CSPA1[4] CSPA1[3] CSPA1[2] CSPA1[1] CSPA1[0]
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# 0 0 0 0 0 0 DATA7 1 DATA76 1 DATA75 1 DATA74 1 DATA73 1
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# CS10 CS9 CS8 CS7 CS6
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# A23 ECLK A22 PC6 A21 PC5 A20 PC4 A19 PC3
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#
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set *(short *)0xfffa46=0x03ff
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#
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# Chip selects configuration
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#
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# 0xFFFA48 - CSBARBT - Chip-Select Base Address Register Boot ROM
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# 0xFFFA4C..0xFFFA74 - CSBAR[10:0] - Chip-Select Base Address Registers
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# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
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# A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 BLKSZ
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# reset 0x0003 for CSBARBT and 0x0000 for CSBAR[10:0]
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#
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# BLKSZ Size Address Lines Compared
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# 000 2k ADDR[23:11]
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# 001 8k ADDR[23:13]
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# 010 16k ADDR[23:14]
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# 011 64k ADDR[23:16]
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# 100 128k ADDR[23:17]
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# 101 256k ADDR[23:18]
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# 110 512k ADDR[23:19]
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# 111 1M ADDR[23:20]
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#
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#
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# 0xFFFA4A - CSORBT - Chip-Select Option Register Boot ROM
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# 0xFFFA4E..0xFFFA76 - CSOR[10:0] - Chip-Select Option Registers
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# 15 14 13 12 11 10 9 6 5 4 3 1 0
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# MODE BYTE R/W STRB DSACK SPACE IPL AVEC
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# 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 - for CSORBT
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#
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# BYTE 00 Disable, 01 Lower Byte, 10 Upper Byte, 11 Both Bytes
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# R/W 00 Reserved,01 Read Only, 10 Write Only, 11 Read/Write
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# SPACE 00 CPU, 01 User, 10 Supervisor, 11 Supervisor/User
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#
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set *(long *)0xfffa48=0x0e0468b0
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# BOOT ROM 0x0e0000 128k RO UL
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set *(long *)0xfffa4c=0x0003503e
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# CS0 RAM 0x000000 64k WR U
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set *(long *)0xfffa50=0x0003303e
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# CS1 RAM 0x000000 64k WR L
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set *(long *)0xfffa54=0x0003683e
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# CS2 RAM 0x000000 64k RO UL
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set *(long *)0xfffa58=0x00000000
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# CS3
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set *(long *)0xfffa5C=0xfff8680f
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# CS4
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set *(long *)0xfffa60=0xffe8783f
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# CS5
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set *(long *)0xfffa64=0x100438f0
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# CS6 R/R 0x100000 128k RW L
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set *(long *)0xfffa68=0x100458f0
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# CS7 R/R 0x100000 128k RW U
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set *(long *)0xfffa6c=0x01036870
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# CS8 RAM 0x010000 64k RO UL
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set *(long *)0xfffa70=0x01033030
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# CS9 RAM 0x010000 64k WR L
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set *(long *)0xfffa74=0x01035030
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# CS10 RAM 0x010000 64k WR U
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#
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# My change
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#
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set *(long *)0xfffa58=0x02036870
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# CS3 RAM 0x020000 64k RO UL
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set *(long *)0xfffa64=0x02033030
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# CS6 RAM 0x020000 64k WR L
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set *(long *)0xfffa68=0x02035030
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# CS7 RAM 0x020000 64k WR U
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# CPU registers
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# SR=PS Status Register
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# 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
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# T1 T0 S 0 0 IP___ 0 0 0 X N Z V C
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# 0 0 1 0 0 1 1 1 0 0 0 U U U U U
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bdm_status
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end
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#===========================================================
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# sets well defined values into VBR
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define vbr_set_all
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set $vec_num=0
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set $vbr_val=(unsigned)$vbr
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while $vec_num<256
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set *(unsigned*)($vbr_val+$vec_num*4)=($vec_num*16)+0xf0000
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set $vec_num++
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end
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end
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# Test writability of RAM location
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define bdm_test_ram_acc
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echo testing ...
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p /x $arg0
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set $ram_addr=(unsigned int)$arg0
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set $old_ram_val=*(int*)$ram_addr
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set *(int*)$ram_addr=0x12345678
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if *(int*)$ram_addr!=0x12345678
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printf "Error1 %08X\n",*(int*)$ram_addr
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end
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set *(char*)$ram_addr=0xab
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if *(int*)$ram_addr!=0xab345678
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printf "Error2 %08X\n",*(int*)$ram_addr
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end
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set *(char*)($ram_addr+1)=0xcd
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if *(int*)$ram_addr!=0xabcd5678
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printf "Error3 %08X\n",*(int*)$ram_addr
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end
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set *(char*)($ram_addr+3)=0x01
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if *(int*)$ram_addr!=0xabcd5601
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printf "Error4 %08X\n",*(int*)$ram_addr
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end
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set *(char*)($ram_addr+2)=0xef
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if *(int*)$ram_addr!=0xabcdef01
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printf "Error5 %08X\n",*(int*)$ram_addr
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end
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set *(int*)$ram_addr=$old_ram_val
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end
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# Read flash identification
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define bdm_read_flash_id
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set $flash_base=(int)$arg0&~0xffff
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output /x $flash_base
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echo \n
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set *(char*)($flash_base+0x555*2+1)=0xf0
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set *(char*)($flash_base+0x555*2+1)=0xaa
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set *(char*)($flash_base+0x2aa*2+1)=0x55
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set *(char*)($flash_base+0x555*2+1)=0x90
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p /x *(char*)($flash_base+0x00*2+1)
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set *(char*)($flash_base+0x555*2+1)=0xf0
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set *(char*)($flash_base+0x555*2+1)=0xaa
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set *(char*)($flash_base+0x2aa*2+1)=0x55
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set *(char*)($flash_base+0x555*2+1)=0x90
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p /x *(char*)($flash_base+0x01*2+1)
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end
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define bdm_read_flash1_id
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bdm_read_flash_id 0x800000
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end
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define bdm_read_flash2_id
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bdm_read_flash_id 0x900000
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end
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define bdm_test_flash_write
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set $flash_base=(int)$arg0 & ~0xffff
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output /x $flash_base
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echo \n
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set *(char*)($flash_base+0x555*2+1)=0xf0
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set *(char*)($flash_base+0x555*2+1)=0xaa
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set *(char*)($flash_base+0x2aa*2+1)=0x55
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set *(char*)($flash_base+0x555*2+1)=0xA0
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set *(char*)($arg0)=$arg1
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end
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define bdm_test_pwm0
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#BIUMCR - BIU Module Configuration Register $YFF400
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set *(short*)0xfff400=*(short*)0xfff400&~0x8000
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#CPCR - CPSM Control Register $YFF408
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set *(short*)0xfff408=*(short*)0xfff408|8
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#PWM5SIC - PWM5 Status/Interrupt/Control Register $YFF428
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set *(short*)0xfff428=0x18
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#PWM5A1 - PWM5 Period Register $YFF42A
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set *(short*)0xfff42a=512
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#PWM5B1 - PWM5 Pulse Width Register $YFF42C
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set *(short*)0xfff42c=0
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if $arg0==0
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set *(short*)0xf87000=0
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set $pwm_val=0
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else
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if $arg0>0
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set *(char*)0xf87000=1
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set $pwm_val=$arg0
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else
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set *(char*)0xf87000=2
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set $pwm_val=-($arg0)
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end
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end
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#DDRQA
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set *(short*)0xfff208=0x8000
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#PORTQA
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set *(short*)0xfff206=~0x8000
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#PWM5B1 - PWM5 Pulse Width Register $YFF42C
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set *(short*)0xfff42c=$pwm_val
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end
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define bdm_test_usd_irc
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set $usd_irc_d=0xf88000
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set $usd_irc_c=0xf88001
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if $arg0!=0
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# Load Gate
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set *(unsigned char*)0xf88020=0
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# CMR
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set *(unsigned char*)$usd_irc_c=0x38
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# IOR
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set *(unsigned char*)$usd_irc_c=0x49
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# IDR
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set *(unsigned char*)$usd_irc_c=0x61
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# RLD - Reset BP, BT CT CPT S
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set *(unsigned char*)$usd_irc_c=0x05
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# DATA - PSC
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set *(unsigned char*)$usd_irc_d=0x02
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# RLD - Reset BP, PR0 -> PSC
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set *(unsigned char*)$usd_irc_c=0x1B
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end
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# RLD - Reset BP, CNTR -> OL
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set *(unsigned char*)$usd_irc_c=0x11
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set $usd_irc_val=((int)(*(unsigned char*)$usd_irc_d))
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set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<8
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set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<16
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print /x $usd_irc_val
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end
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bdm_hw_init
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#b main
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#run
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