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august 2013 v8.1
Extended 'Output preamble' to 5 lines (all optional via button).
NB! a * is no longer added in front.
Fixed a strcpy error in the 'minmiconsole'.
(destination pointer vs array).
Window dialogues;
On some environments the mouse could disappear
when clicking a button.
Not fixed, but a workarond (v_hide_c(hl, 1) added.
New config keyword (and field in configure window):
copr= comment prefix.
Fixed a bug where Digger crashed on long labels and not
'labels on separate lines' configured.
In operands: a scale factor of 1 is silently accepted and
ognored for all CPU types.

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(c) 1996-2011 by H. Robbers @ Amsterdam the Netherlands
For those familiar with MC68000 family processors who desparately want
to go around any other way but cant.
SZ=00:B, 01:W, 10:L defenitely NOT 11
column 1:
' ' = 68000 family
* = higher than 68000
- = Coldfire v4e ISA_C as extension or restriction
C = Coldfire v4e ISA_C ONLY
# = NOT Coldfire if otherwise family
1=68010/12, 2=68020, 3=68030, 4=68040, 6=68060, 5=68551, 8=68881,
S=privileged
A Coldfire instruction can never be longer than 6 bytes.
Any combination of operands resulting in more than 2 extension words
are invalid. This occurs mostly with the move instruction and floating
point instructions.
Coldfire does NOT implement base and outer displacement.
Coldfire DOES implement scale facter for Xn.
<.....> = effective address:
..... = restrictions on addressing mode:
x: one octal digit for a register number
cntr control 2x 5x 6x 70 71 72 73
c_alt control alterable 2x 5x 6x 70 71
c_add control addressable 2x 5x 6x 70 71 72 73 74
m_alt memory alterable 2x 3x 4x 5x 6x 70 71
d_alt data alterable 0x 2x 3x 4x 5x 6x 70 71
d_add data addressable 0x 2x 3x 4x 5x 6x 70 71 72 73 74
m_add memory addresing 2x 3x 4x 5x 6x 70 71 72 73 74
alter all alterable 0x 1xWL 2x 3x 4x 5x 6x 70 71
all 0x 1xWL 2x 3x 4x 5x 6x 70 71 72 73 74
+ includes (An)+
- includes -(An)
D includes Dn direct
addressing modes for <.....>
m0/m1 r0/r1
0 x Dn
1 x An
2 x (An)
3 x (An)+
4 x -(An)+
5 x d(An)
6 x d(An,Xn)
7 0 nnnnn.W
1 nnnnn.L
2 d(PC)
3 d(PC,Xn)
4 #data
--- line 0 --------------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
# ori -> ccr 0000 000 000 111 100 00000000 ######## B
#S ori -> sr 0000 000 001 111 100 ######## ######## W
ori 0000 000 0SZ <d_alt> #data B,W,L
- ori.l 0000 000 010 000 ddd #data L
C bitrev 0000 000 011 000 ddd #data L
# andi -> ccr 0000 001 000 111 100 00000000 ######## B
#S andi -> sr 0000 001 001 111 100 ######## ######## W
andi 0000 001 0SZ <d_alt> #data B,W,L
- andi.l 0000 001 010 000 ddd #data L
C byterev 0000 001 011 000 ddd #data L
* cmp2 0000 0SZ 011 <c_add> Txxx0000 00000000
* chk2 0000 0SZ 011 <c_add> Txxx1000 00000000
subi 0000 010 0SZ <d_alt> #data B,W,L
- subi.l 0000 010 010 000 ddd #data L
C ff1 0000 010 011 000 ddd #data L
addi 0000 011 0SZ <d_alt> #data B,W,L
- addi.l 0000 011 010 000 ddd #data L
2 callm 0000 011 011 <c_add> 00000000 ########
btst #n,ea 0000 100 000 <d_add> 00000000 ########
bchg #n,ea 0000 100 001 <d_alt> 00000000 ########
bclr #n,ea 0000 100 010 <d_alt> 00000000 ########
bset #n,ea 0000 100 011 <d_alt> 00000000 ########
# eori -> ccr 0000 101 000 111 100 00000000 ######## B
#S eori -> sr 0000 101 001 111 100 ######## ######## W
eori 0000 101 0SZ <d_alt> #data B,W,L
- eori.l 0000 101 010 000 ddd #data L
cmpi 0000 110 0SZ <d_add> #data B,W,L
- cmpi 0000 110 0SZ 000 ddd #data B,W,L
*S moves 0000 111 0SZ <m_alt> txxxr000 00000000
* cas 0000 1ss 011 <m_alt> 0000000u uu000ccc
ss=01:B, 10:W, 11:L
* cas2 0000 1ss 011 111 100 zie boek
ss= 10:W, 11:L
# movep 0000 xxx 1rm 001 aaa
btst Dn,ea 0000 xxx 100 <d_add>
bchg Dn,ea 0000 xxx 101 <d_alt>
bclr Dn,ea 0000 xxx 110 <d_alt>
bset Dn,ea 0000 xxx 111 <d_alt>
--- line 1,2,3-----------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
move 00ss <d_alt> < all > ss=01: B, 11:W, 10:L
movea 00ss aaa 001 < all > ss= 11:W, 10:L
--- line 4 --------------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
negx 0100 000 0SZ <d_alt>
- negx.l 0100 000 010 000 ddd
S move <- sr 0100 000 011 <d_alt>
-S move <- sr 0100 000 011 000 ddd
C stldsr 0100 000 011 100 111
0100 011 011 111 100 ######## ########
clr 0100 001 0SZ <d_alt>
* move <- ccr 0100 001 011 <d_alt>
- move <- ccr 0100 001 011 000 ddd
neg 0100 010 0SZ <d_alt>
- neg.l 0100 010 010 000 ddd
move -> ccr 0100 010 011 <d_add>
not 0100 011 0SZ <d_alt>
- not.l 0100 011 010 000 ddd
S move -> sr 0100 011 011 <d_add>
* link.l 0100 100 000 001 aaa 32 bit displ
nbcd 0100 100 000 <d_alt>
swap 0100 100 001 000 ddd
* bkpt 0100 100 001 001 ###
pea 0100 100 001 <contr>
ext 0100 100 0ss 000 ddd ss=10:W, 11:L
movem ->mem 0100 100 01s <-c_alt> mmmmmmmm mmmmmmmm s=0:W,1:L
- movem ->mem 0100 100 01s <c_alt> mmmmmmmm mmmmmmmm
-* extb.l 0100 100 111 000 ddd (lea Dn,A4 :-)
tst 0100 101 0SZ <d_alt>
* tst 0100 101 0SZ < all >
C halt 0100 101 011 001 000
C pulse 0100 101 011 001 100
tas 0100 101 011 <d_alt>
illegal 0100 101 011 111 100
D D
- mulu.l 0100 110 000 <d_add> 0lll0000 00000000 32bit to lll
* mulu.l 0100 110 000 <d_add> 0lll0s00 00000hhh s=0:32bit to lll, s=1:64bit to hhh:lll
- muls.l 0100 110 000 <d_add> 0lll1000 00000000
* muls.l 0100 110 000 <d_add> 0lll1s00 00000hhh
- divu.l 0100 110 001 <d_add> 0qqq0000 00000qqq
* divul.l 0100 110 001 <d_add> 0qqq0000 00000rrr
C remu.l 0100 110 001 <d_add> 0qqq0000 00000rrr
* divu.l 0100 110 001 <d_add> 0qqq0100 00000rrr
- divs.l 0100 110 001 <d_add> 0qqq1000 00000qqq
* divsl.l 0100 110 001 <d_add> 0qqq1000 00000rrr
C rems.l 0100 110 001 <d_add> 0qqq1000 00000rrr
* divs.l 0100 110 001 <d_add> 0qqq1100 00000rrr
C sats 0100 110 010 000 ddd
movem ->reg 0100 110 01s <c_add+> mmmmmmmm mmmmmmmm s=0:W,1:L
- movem ->reg 0100 110 01s <c_add> mmmmmmmm mmmmmmmm
trap 0100 111 001 00# ###
link 0100 111 001 010 aaa dddddddd dddddddd
unlk 0100 111 001 011 aaa
S move An,usp 0100 111 001 100 aaa
S move usp,An 0100 111 001 101 aaa
S reset 0100 111 001 110 000
nop 0100 111 001 110 001
S stop 0100 111 001 110 010 ######## ########
S rte 0100 111 001 110 011
* rtd 0100 111 001 110 100 dddddddd dddddddd
rts 0100 111 001 110 101
# trapv 0100 111 001 110 110
# rtr 0100 111 001 110 111
2 rtm Dn 0100 111 001 110 ddd
*S movec Rc,Rn 0100 111 001 111 010 txxxcccc cccccccc
-*S movec Rn,Rc 0100 111 001 111 011 txxxcccc cccccccc
2 rtm An 0100 111 001 111 aaa
jsr 0100 111 010 <c_add>
jmp 0100 111 011 <c_add>
* chk.l 0100 xxx 100 <d_add>
# chk.w 0100 xxx 110 <d_add>
lea 0100 aaa 111 <contr>
--- line 5 --------------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
addq 0101 ### 0SZ <alter>
- addq.l 0101 ### 010 <alter>
subq 0101 ### 1SZ <alter>
- subq.l 0101 ### 110 <alter>
# dbcc 0101 cccc 11 001 ddd dddddddd dddddddd
scc 0101 cccc 11 <d_alt>
- scc 0101 cccc 11 000 ddd
C tpf 0101 0001 11 111 mmm #data B?,W,L
* trapcc.w # 0101 cccc 11 111 010 ######## ########
* trapcc.l # 0101 cccc 11 111 011 32 bit data
* trapcc 0101 cccc 11 111 100
1 0 1 0
--- line 6 --------------------------------------------------------------------
5432 1098 7654 3210 54321098 76543210
bra.b 0110 0000 dddd dddd
bra.w 0110 0000 0000 0000 dddddddd dddddddd
-* bra.l 0110 0000 1111 1111 32 bits displ
bsr.b 0110 0001 dddd dddd
bsr.w 0110 0001 0000 0000 dddddddd dddddddd
-* bsr.l 0110 0001 1111 1111 32 bits displ
bcc.b 0110 cccc dddd dddd
bcc.w 0110 cccc 0000 0000 dddddddd dddddddd
-* bcc.l 0110 cccc 1111 1111 32 bits displ
--- line 7 --------------------------------------------------------------------
moveq 0111 ddd0 #### ####
C mvs 0111 ddd 10s <d_add> s= word, s= long
C mvz 0111 ddd 11s <d_add> s= word, s= long
--- line 8 --------------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
or ea,Dn 1000 ddd 0SZ <d_add>
- or.l ea,Dn 1000 ddd 010 <d_add>
divu 1000 ddd 011 <d_add>
# sbcd Dx,Dy 1000 yyy 100 000 ddd
# sbcd -(Ax),-(Ay)1000 yyy 100 001 aaa
* pack Dx,Dy 1000 yyy 101 000 ddd jjjjjjjj jjjjjjjj
* pack -(Ax),-(Ay)1000 yyy 101 001 aaa jjjjjjjj jjjjjjjj
* unpk Dx,Dy 1000 yyy 110 000 ddd jjjjjjjj jjjjjjjj
* unpk -(Ax),-(Ay)1000 yyy 110 001 aaa jjjjjjjj jjjjjjjj
or Dn,ea 1000 ddd 1SZ <m_alt>
- or.l Dn,ea 1000 ddd 110 <m_alt>
divs 1000 ddd 111 <d_add>
--- line 9 --------------------------------------------------------------------
r1 m1 m0 r0
sub ea,Dn 1001 ddd 0SZ < all >
- sub.l ea,Dn 1001 ddd 010 < all >
# suba.w 1001 aaa 011 < all >
subx Dx,Dy 1001 yyy 1SZ 000 ddd
- subx.l Dx,Dy 1001 yyy 110 000 ddd
# subx -(Ax),-(Ay)1001 yyy 1SZ 001 aaa
sub Dn,ea 1001 ddd 1SZ <m_alt>
- sub.l Dn,ea 1001 ddd 110 <m_alt>
suba.l 1001 aaa 111 < all >
--- line A --------------------------------------------------------------------
r1 m1 m0 r0
# Linea 1010 ### ### ### ### Line_a emulator
C move3q #d,ea 1010 ### 101 <d_alt>
C MAC... beyond the scope of this document
--- line B --------------------------------------------------------------------
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
cmp ea,Dn 1011 ddd 0SZ < all >
cmpa.w 1011 aaa 011 < all >
cmpm 1011 xxx 1SZ 001 yyy
eor Dn,ea 1011 ddd 1SZ <d_alt> (cmp Dn,ea misused)
- eor.l Dn,ea 1011 ddd 110 <d_alt>
cmpa.l 1011 aaa 111 < all >
--- line C --------------------------------------------------------------------
and ea,Dn 1100 ddd 0SZ <d_add>
- and.l ea,Dn 1100 ddd 010 <d_add>
mulu 1100 ddd 011 <d_add>
# abcd Dx,Dy 1100 yyy 100 000 ddd
# abcd -(Ax),-(Ay)1100 yyy 100 001 aaa
and Dn,ea 1100 ddd 1SZ <m_alt>
and.l Dn,ea 1100 ddd 110 <m_alt>
muls 1100 ddd 111 <d_add>
# exg Dx,Dy 1100 xxx 101 000 yyy
# exg Ax,Ay 1100 xxx 101 001 yyy
# exg Dx,Ay 1100 xxx 110 001 yyy
--- line D --------------------------------------------------------------------
add ea,Dn 1101 ddd 0SZ < all >
- add.l ea,Dn 1101 ddd 010 < all >
# adda.w 1101 aaa 011 < all >
addx Dx,Dy 1101 yyy 1SZ 000 ddd
- addx.l Dx,Dy 1101 yyy 110 000 ddd
# addx -(Ax),-(Ay)1101 yyy 1SZ 001 aaa
add Dn,ea 1101 ddd 1SZ <m_alt>
- add.l Dn,ea 1101 ddd 110 <m_alt>
adda.l 1101 aaa 111 < all >
--- line E --------------------------------------------------------------------
asl,asr #,Dn 1110 ### rSZ 000 ddd shifts: r=0:right,1=left
lsl,lsr 1110 ### rSZ 001 ddd
- asl,asr #,Dn 1110 ### r10 000 ddd
- lsl,lsr 1110 ### r10 001 ddd
# roxl,roxr 1110 ### rSZ 010 ddd
# rol,ror 1110 ### rSZ 011 ddd
asl,asr Dx,Dy 1110 xxx rSZ 100 yyy
lsl,lsr 1110 xxx rSZ 101 yyy
- asl,asr Dx,Dy 1110 xxx r10 100 yyy
- lsl,lsr 1110 xxx r10 101 yyy
# roxl,roxr 1110 xxx rSZ 110 yyy
# rol,ror 1110 xxx rSZ 111 yyy
# asl,asr <ea> 1110 000 r11 <m_alt> B
# lsl,lsr 1110 001 r11 <m_alt> B
# roxl,roxr 1110 010 r11 <m_alt> B
# rol,ror 1110 011 r11 <m_alt> B
* bftst 1110 100 011 <Dc_add> 0000dooo ooDwwwww
* bfextu 1110 100 111 <Dc_add> 0xxxdooo ooDwwwww
* bfchg 1110 101 011 <Dc_alt> 0000dooo ooDwwwww
* bfexts 1110 101 111 <Dc_add> 0xxxdooo ooDwwwww
* bfclr 1110 110 011 <Dc_alt> 0000dooo ooDwwwww
* bfffo 1110 110 111 <Dc_add> 0xxxdooo ooDwwwww
* bfset 1110 111 011 <Dc_alt> 0000dooo ooDwwwww
* bfins 1110 111 111 <Dc_alt> 0xxxdooo ooDwwwww
--- line F --------------------------------------------------------------------
The Coldfire only knows coprocessor 1, the floating point set.
Coldfire floating point doesnt implement size x (12 bytes)
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
35S ploadr 1111 000 000 <c_alt> 00100010 000FFFFF zie boek
35S ploadw 1111 000 000 <c_alt> 00100000 000FFFFF zie boek
5 pvalid VAL,ea 1111 000 000 <c_alt> 00101000 00000000 "
5 pvalid (An),ea 1111 000 000 <c_alt> 00101100 00000rrr "
3S pflush 1111 000 000 <c_alt> 001mmm00 MMMFFFFF "
5S pflush 1111 000 000 <c_alt> 001mmm0M MMMFFFFF "
3S pmove ea,MRn 1111 000 000 <c_alt> 010ppp00 00000000 for srp,crp&tc
3S pmove.. MRn,ea 1111 000 000 <c_alt> 010ppp1f 00000000 "
011000r0 00000000 for mmusr
000010rf 00000000 for TT0
000011rf 00000000 for TT1
f = 1: .. = fd
5S pmove 1111 000 000 < ') > 010pppr0 00000000 for tc,drp,srp,
crp,cal,val,scc,
ac
011pppr0 000num00 for bad,bac
011pppr0 00000000 for psr,pcsr
') r=1: alter, r=0: all
35S ptest 1111 000 000 <c_alt> 100lllra xxxFFFFF
5S pflushr 1111 000 000 <m_add> 10100000 00000000 "
5S pdbcc 1111 000 001 001 ddd 00000000 00cccccc
5S pscc 1111 000 001 <d_alt> 00000000 00cccccc
5S ptrapcc 1111 000 001 111 ooo 00000000 00cccccc
5S pbcc.w 1111 000 010 ccc ccc dddddddd dddddddd
5S pbcc.l 1111 000 011 ccc ccc 32 bit displ
5S psave 1111 000 100 <-c_alt>
5S prestore 1111 000 101 <c_add+>
*8S fsave 1111 001 100 <-c_alt>
*8S frestore 1111 001 101 <c_add+>
very special are:
*8 fmovem ea,m 1111 001 000 <c_add+> 110-0000 mmmmmmmm
*8 fmovem ea,Dn 1111 001 000 <c_add+> 110-1000 0ddd0000
*8 fmovem m,ea 1111 001 000 <-c_alt> 111+0000 mmmmmmmm
*8 fmovem Dn,ea 1111 001 000 <-c_alt> 111+1000 0ddd0000
1 0 1 0
5432 109 876 543 210 54321098 76543210
r1 m1 m0 r0
CS intouch 1111 010 000 101 aaa zie book
46S cinv 1111 010 0cc 0sc aaa "
46S cpush 1111 010 0cc 1sc aaa "
3S pflusha 1111 000 000 <c_alt> 0010 010 000 000 000
3S pflush 1111 000 000 <c_alt> 001m mm0 0xx xff fff
46S pflush 1111 010 100 0oo aaa zie book
4S ptestw 1111 010 101 001 aaa "
4S ptestr 1111 010 101 101 aaa "
6S plpa 1111 010 11r 001 aaa "
46 move16 (Ay)+,L 1111 011 000 000 yyy 32 bit address
46 move16 L,(Ay)+ 1111 011 000 001 yyy 32 bit address
46 move16 (Ay),L 1111 011 000 010 yyy 32 bit address
46 move16 L,(Ay) 1111 011 000 011 yyy 32 bit address
46 move16 Ax+,Ay+ 1111 011 000 100 xxx 1yyy0000 00000000
6S lpstop 1111 100 000 000 000 00000001 11000000 #### #### #### ####
General coprocessor instructions:
23 cpGEN 1111 cpi 000 <.....> command&extensions
23 cpDBcc 1111 cpi 001 001 ddd 00000000 00cccccc
23 cpScc 1111 cpi 001 <d_alt> 00000000 00cccccc
23 cpTRAPcc 1111 cpi 001 111 ooo 00000000 00cccccc + word|long
23 cpBcc.w 1111 cpi 010 ccc ccc
23 cpBcc.l 1111 cpi 011 ccc ccc
23S cpSAVE 1111 cpi 100 <-c_alt>
23S cpRESTORE 1111 cpi 101 <c_add+>
On the 68040, 68060 and Coldfire the following floating point opcodes
have the fs.... and fd.... variants:
s d
fabs 0x18 0x58 0x5c
fadd 0x22 0x62 0x66
fdiv 0x20 0x60 0x64
fmove 0x00 0x40 0x44
fmul 0x23 0x63 0x67
fneg 0x1a 0x5a 0x5e
fsqrt 0x04 0x41 0x45
fsub 0x28 0x68 0x6c

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namW[354]={
$0000=ssp_init
$0004=ev_reset
$0008=ev_buserr
$000c=ev_adrerr
$0010=ev_illegal
$0014=ev_divby0
$0018=ev_chk_ofl
$001c=ev_trapv
$0020=ev_priverr
$0024=ev_trace
$0028=ev_a_line
$002c=ev_f_line
$0034=vec_Nimp_lF
$0060=ev_spurerr
$0064=ev_level1
$0068=ev_HBI
$006c=ev_level3
$0070=ev_VBI
$0074=ev_SCC
$0078=ev_MFP
$007c=ev_level7
$0080=ev_trap0
$0084=ev_gemdos
$0088=ev_xgem
$008c=ev_trap3
$0090=ev_trap4
$0094=ev_trap5
$0098=ev_trap6
$009c=ev_trap7
$00a0=ev_trap8
$00a4=ev_trap9
$00a8=ev_trap10
$00ac=ev_trap11
$00b0=ev_trap12
$00b4=ev_bios
$00b8=ev_xbios
$00bc=ev_trap15
$0100=iv_M1_busy
$0104=iv_M1_dcd_ack
$0108=iv_M1_cts_midi
$010c=iv_M1_blit_dsp
$0110=iv_M1_time_d
$0114=iv_M1_time_c
$0118=iv_M1_kb_midi
$011c=iv_M1_disk
$0120=iv_M1_time_b
$0124=iv_M1_terr
$0128=iv_M1_treq
$012c=iv_M1_rerr
$0130=iv_M1_rreq
$0134=iv_M1_time_a
$0138=iv_M1_ring
$013c=iv_M1_mono_samp
$0140=iv_M2_0
$0144=iv_M2_1
$0148=iv_M2_2
$014c=iv_M2_3
$0150=iv_M2_4
$0154=iv_M2_5
$0158=iv_M2_6
$015c=iv_M2_7
$0160=iv_M2_8
$0164=iv_M2_9
$0168=iv_M2_10
$016c=iv_M2_11
$0170=iv_M2_12
$0174=iv_M2_13
$0178=iv_M2_14
$017c=iv_M2_15
$0180=iv_SCC_0
$0184=iv_SCC_1
$0188=iv_SCC_2
$018c=iv_SCC_3
$0190=iv_SCC_4
$0194=iv_SCC_5
$0198=iv_SCC_6
$019c=iv_SCC_7
$01a0=iv_SCC_8
$01a4=iv_SCC_9
$01a8=iv_SCC_10
$01ac=iv_SCC_11
$01b0=iv_SCC_12
$01b4=iv_SCC_13
$01b8=iv_SCC_14
$01bc=iv_SCC_15
$0380=proc_lives
$0384=proc_dregs
$03a4=proc_aregs
$03c4=proc_enum
$03c8=proc_usp
$03cc=proc_stk
$0400=etv_timer
$0404=etv_critic
$0408=etv_term
$040c=etv_xtra
$0420=memvalid
$0424=memcntrl
$0426=resvalid
$042a=resvector
$042e=phystop
$0432=_membot
$0436=_memtop
$043a=memval2
$043e=flock
$0440=seekrate
$0442=_timr_ms
$0444=_fverify
$0446=_bootdev
$0448=_palmode
$044a=defshiftmd
$044c=sshiftmd
$044e=_v_bas_ad
$044f=_v_bas_2
$0450=_v_bas_1
$0451=_v_bas_0
$0452=vblsem
$0454=nvbls
$0456=_vblqueue
$045a=colorptr
$045e=screenpt
$0462=_vbclock
$0466=_frclock
$046a=hdv_init
$046e=swv_vec
$0472=hdv_bpb
$0476=hdv_rw
$047a=hdv_boot
$047e=hdv_mediach
$0482=_cmdload
$0484=conterm
$0486=trp14ret
$048a=criticret
$048e=themd
$049e=_md
$04a2=savptr
$04a6=_nflops
$04a8=con_state
$04ac=sav_row
$04ae=sav_context
$04b2=_bufl
$04b6=_bufl_2
$04ba=_hz_200
$04be=the_env
$04c2=_drvbits
$04c6=_dskbufp
$04ca=_autopath
$04ce=_vbl_list
$04ee=_prt_cnt
$04f0=_prtabt
$04f2=_sysbase
$04f6=_shell_p
$04fa=end_os
$04fe=exec_os
$0502=scr_dump
$0506=prv_lsto
$050a=prv_lst
$050e=prv_auxo
$0512=prv_aux
$0516=pun_ptr
$051a=memval3
$051e=xconstat
$053e=xconin
$055e=xcostat
$057e=xconout
$059e=_longframe
$05a0=_cookies
$05a4=TT_ramtop
$05a8=TT_ramvalid
$05ac=bell_hook
$05b0=kcl_hook
$8001.w=hw_memconf
$8006.w=hw_f30_mon_mem
$8007.w=hw_f30_comp_div
$8201.w=hw_dbasehigh
$8203.w=hw_dbasemid
$8205.w=hw_vcounthigh
$8207.w=hw_vcountmid
$8209.w=hw_vcountlow
$820a.w=hw_syncmode
$820d.w=hw_dbaselow
$8240.w=hw_pal_00
$8242.w=hw_pal_01
$8244.w=hw_pal_02
$8246.w=hw_pal_03
$8248.w=hw_pal_04
$824a.w=hw_pal_05
$824c.w=hw_pal_06
$824e.w=hw_pal_07
$8250.w=hw_pal_08
$8252.w=hw_pal_09
$8254.w=hw_pal_10
$8256.w=hw_pal_11
$8258.w=hw_pal_12
$825a.w=hw_pal_13
$825c.w=hw_pal_14
$825e.w=hw_pal_15
$8260.w=hw_shiftmd
$8262.w=hw_shift_tt
$8264.w=hw_ste_pixoffH
$8265.w=hw_ste_pixoff
$827e.w=hw_stacydsp
$8400.w=hw_pal_tt
$8604.w=hw_dma_dskctl
$8606.w=hw_dma_fifo
$8609.w=hw_dma_high
$860b.w=hw_dma_mid
$860d.w=hw_dma_low
$8701.w=hw_TT_scsi_dma3
$8703.w=hw_TT_scsi_dma2
$8705.w=hw_TT_scsi_dma1
$8707.w=hw_TT_scsi_dma0
$8709.w=hw_TT_scsi_cnt3
$870b.w=hw_TT_scsi_cnt2
$870d.w=hw_TT_scsi_cnt1
$870f.w=hw_TT_scsi_cnt0
$8710.w=hw_TT_scsi_rsdhigh
$8712.w=hw_TT_scsi_rsdlow
$8714.w=hw_TT_scsi_ctl
$8781.w=hw_scsi_data
$8783.w=hw_scsi_icr
$8785.w=hw_scsi_mode
$8787.w=hw_scsi_tcr
$8789.w=hw_scsi_idcr
$878b.w=hw_scsi_stsr
$878d.w=hw_scsi_trid
$878f.w=hw_scsi_irrs
$8800.w=hw_psg_rd_sel
$8802.w=hw_psg_wr
$8900.w=hw_sdma_cont_w
$ff8901=crippled_hw_sdma_cont
$8901.w=hw_sdma_cont
$8903.w=hw_sdma_beg2
$8905.w=hw_sdma_beg1
$8907.w=hw_sdma_beg0
$8909.w=hw_sdma_loop2
$890b.w=hw_sdma_loop1
$890d.w=hw_sdma_loop0
$890f.w=hw_sdma_end2
$8911.w=hw_sdma_end1
$8913.w=hw_sdma_end0
$8920.w=hw_F_dac_trk
$8921.w=hw_sdma_mode
$8922.w=hw_MW_data
$8924.w=hw_MW_mask
$8930.w=hw_F_xbar_sc
$8932.w=hw_F_xbar_dc
$8960.w=hw_TT_rtc_ar_w
$8961.w=hw_TT_rtc_ar
$8962.w=hw_TT_rtc_dr_w
$8963.w=hw_TT_rtc_dr
$8a00.w=hw_BLIT_htone
$8c01.w=hw_scc_dma3
$8c03.w=hw_scc_dma2
$8c05.w=hw_scc_dma1
$8c07.w=hw_scc_dma0
$8c09.w=hw_scc_cnt3
$8c0b.w=hw_scc_cnt2
$8c0d.w=hw_scc_cnt1
$8c0f.w=hw_scc_cnt0
$8c10.w=hw_scc_drr
$8c14.w=hw_scc_cr_w
$8c15.w=hw_scc_cr
$8c81.w=hw_SCC_a_cr
$8c83.w=hw_SCC_a_dr
$8c85.w=hw_SCC_b_cr
$8c87.w=hw_SCC_b_dr
$8e01.w=hw_TT_sys_im
$8e03.w=hw_TT_sys_is
$8e05.w=hw_TT_sys_ig
$8e07.w=hw_TT_vme_ig
$8e09.w=hw_TT_scu_gpr1
$8e0b.w=hw_TT_scu_gpr2
$8e0d.w=hw_TT_vme_im
$8e0f.w=hw_TT_vme_is
$9200.w=hw_switches
$9201.w=hw_pad_fire
$9202.w=hw_pad_direct
$9211.w=hw_pad_0_y
$9213.w=hw_pad_0_x
$9215.w=hw_pad_1_y
$9217.w=hw_pad_1_x
$9220.w=hw_light_x
$9222.w=hw_light_y
$9800.w=hw_F_pal
$a200.w=hw_dsp_ic
$a201.w=hw_dsp_cv
$a202.w=hw_dsp_is
$a203.w=hw_dsp_iv
$a204.w=hw_dsp_long
$a205.w=hw_dsp_d2
$a206.w=hw_dsp_d1
$a207.w=hw_dsp_d0
$fa01.w=hw_M1_gpip
$fa03.w=hw_M1_aer
$fa05.w=hw_M1_ddr
$fa07.w=hw_M1_iera
$fa09.w=hw_M1_ierb
$fa0b.w=hw_M1_ipra
$fa0d.w=hw_M1_iprb
$fa0f.w=hw_M1_isra
$fa11.w=hw_M1_isrb
$fa13.w=hw_M1_imra
$fa15.w=hw_M1_imrb
$fa17.w=hw_M1_vr
$fa19.w=hw_M1_tacr
$fa1b.w=hw_M1_tbcr
$fa1d.w=hw_M1_tcdcr
$fa1f.w=hw_M1_tadr
$fa21.w=hw_M1_tbdr
$fa23.w=hw_M1_tcdr
$fa25.w=hw_M1_tddr
$fa27.w=hw_M1_scr
$fa29.w=hw_M1_ucr
$fa2b.w=hw_M1_rsr
$fa2d.w=hw_M1_tsr
$fa2f.w=hw_M1_udr
$fa40.w=hw_fpu_stat
$fa42.w=hw_fpu_cont
$fa44.w=hw_fpu_save
$fa46.w=hw_fpu_rest
$fa4a.w=hw_fpu_comm
$fa4e.w=hw_fpu_cond
$fa50.w=hw_fpu_oper
$fa54.w=hw_fpu_rsel
$fa58.w=hw_fpu_iadr
$fa5c.w=hw_fpu_opad
$fa81.w=hw_M2_gpip
$fa83.w=hw_M2_aer
$fa85.w=hw_M2_ddr
$fa87.w=hw_M2_iera
$fa89.w=hw_M2_ierb
$fa8b.w=hw_M2_ipra
$fa8d.w=hw_M2_iprb
$fa8f.w=hw_M2_isra
$fa91.w=hw_M2_isrb
$fa93.w=hw_M2_imra
$fa95.w=hw_M2_imrb
$fa97.w=hw_M2_vr
$fa99.w=hw_M2_tacr
$fa9b.w=hw_M2_tbcr
$fa9d.w=hw_M2_tcdcr
$fa9f.w=hw_M2_tadr
$faa1.w=hw_M2_tbdr
$faa3.w=hw_M2_tcdr
$faa5.w=hw_M2_tddr
$faa7.w=hw_M2_scr
$faa9.w=hw_M2_ucr
$faab.w=hw_M2_rsr
$faad.w=hw_M2_tsr
$faaf.w=hw_M2_udr
$fc00.w=hw_KB_cont
$fc02.w=hw_KB_data
$fc04.w=hw_MIDI_cont
$fc06.w=hw_MIDI_data
}

37
devtools/digger.8_1/tos104.idx Normal file
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@@ -0,0 +1,37 @@
FILE= {
typ =400
spg =0
havo=1
offs=16515072
}
****
labl[1]={
$fd3b34=Is_this_the_desktop
}
data={
1/156 2/153 1/255 1/87 1/85 155/0 1/240 3/255 1/63 25/0 1/64 1/102 1/38 15/0 1/84
3/85 1/1 45/0 1/101 5/102 1/150 32/153 5/0 16/153 61/0 1/255 1/159 1/9 50/0 1/64 6/85
1/1 1298/0 1/64 7/85 1/149 1/153 1/9 16/0 1/240 3/255 1/15 110/0 1/240 3/255 1/15 24/0
1/192 2/255 1/3 9/0 1/100 6/102 1/38 121/0 1/4 3153/0 5/85 14/0 1/85 1/21 23/0 1/64
8/85 1/5 80/0 2/85 45/0 1/84 3/85 1/1 23/0 1/84 3/85 1/1 67/0 1/100 9/102 1/2
122/0 1/80 3/85 1/5 42/0 1/80 5/85 1/21 62/0 1/80 4/85 1/5 68/0 1/84 2/85 1/1
5/0 1/100 9/102 1/2 2388/0 4/85 1/1 41/0 1/252 13/255 91/0 1/64 1/85 1/255 3/85 207/0
1/100 3/102 1/2 86/0 9/85 1/21 94/0 1/192 2/255 4/85 1/1 35/0 1/64 3/85 1/21 369/0
1/144 17/153 1/9 17/0 1/80 7/85 1/5 9/0 4/85 1/1 140/0 1/144 1/153 1/9 25/0 4/85
15/0 1/153 1/9 30/0 1/64 1/21 101/0 1/64 1/85 1/21 196/0 1/80 17/85 1/213 3/255 1/15
801/0 1/144 5/153 1/9 3204/0 1/80 14/85 3415/0 1/100 1/102 1/2 2999/0 1/64 302/102 2/86 11/85
65/255 1/159 3/153 1/249 1/255 1/87 1/85 1/149 22/255 1/103 1/89 1/150 1/101 1/89 1/150 1/101
1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89
1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150
1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101
1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/87 9/153 1/249 5/255 1/127
1060/85 1/253 1/255 1/127 223/85 1/223 1/255 1/103 22/102 1/230 6/255 1/127 8/102 1/230 2/255 1/87
8/85 32/153 2/255 1/103 2/102 1/230 1/255 1/87 1/85 1/149 8/153 1/255 1/127 58/102 1/86 8/85
1/101 11/102 1/254 1/151 18/153 1/249 1/95 6/85 6/102 3/85 22/102 1/254 1/95 17/85 1/101 22/102
1/230 1/255 11/153 6/85 1/149 6/153 1/249 1/253 3/255 5/85 1/213 244/255 1/127 384/85 1/213 539/255
1/95 860/85 67/255 1/95 1/149 133/153
}
jump={
5206/0 1/87 4/85 14/0 1/87 1/21 23/0 1/192 3/85 1/87 4/85 1/5 80/0 1/87 1/85
278/0 1/112 3/85 1/5 3847/0 1/192 1/21 101/0 1/192 1/85 1/21 14998/0
}

BIN
devtools/digger.8_1/ttd_icon.hrd Normal file
View File

Binary file not shown.

BIN
devtools/digger.8_1/ttd_icon.rsc Normal file
View File

Binary file not shown.

247
devtools/digger.8_1/uk_306.idx Normal file
View File

@@ -0,0 +1,247 @@
FILE= {
typ =425
havo=0
offs=14680064
spg =0
PROF= {
titl=TT-Digger@v7
mc00=0
mc20=0
mc30=1
mc40=0
mc60=0
mc51=0
mc81=1
dblf=0
wabx=0
dirw=0
lbnl=1
xooo=1
deci=1
opco=1
hasc=0
oasc=0
stnd=0
lbls=1
syms=0
usys=1
isys=0
tosi=0
v95 =0
vger=0
vfra=0
vlat=0
vsca=0
vmat=0
vall=1
vnon=0
vcus=0
text=.TEXT
data=.DATA
bss =.BSS
xdef=.XDEF
xref=.XREF
comm=.COMM
modu=.MODULE
equa=equ
sbra=.s
wbra=@@
lbra=.l
wabs=@@
labs=.l
word=.w
lsep=:
kpre=BM_
ille=illegal
exts=.s
exth=.dmp
extx=.asx
hexa=$
namA=SYSVARS.RA
incA=sysvars
inct=include@!N
gnco=*sys_vars
gnce=*end
lnco=*loc_vars
lnce=*end
invi=@
cvi0=01111111111111111111111111111111
cvi1=11111111111111111111111111111111
cvi2=11111111111111111111111111111111
cvi3=11111111111111111111111111111111
cvi4=11111111111111111111111111111111
cvi5=11111111111111111111111111111111
cvi6=11111111111111111111111111111111
cvi7=11111111111111111111111111111111
diag=0
}
}
****
labl[114]={
$e00030=tos_start
$e00058=RTN_DIAG
$e00096=A6_1
$e0009e=A6_2
$e000ba=COLD
$e000e0=_0
$e000e1=_1
$e000e4=p_1
$e000e8=_2
$e000f0=_3
$e0010c=A6_3
$e00bee=RTS
$e00c06=WARM
$e00c24=LOW_palet
$e00c44=autoint_2
$e00c5a=V_blank
$e00d78=RTE
$e00d7a=Vsync
$e00d98=critic_err
$e00d9c=XBIOS
$e00da2=BIOS
$e00dfa=bios_tab
$e00e2c=xbios_tab
$e00fd0=Supexec
$e00fd6=Bconstat
$e00fde=Bconin
$e00fe6=Bcostat
$e00fee=Bconout
$e010a4=Drvmap
$e010aa=Kbshift
$e010bc=Getmpb
$e01124=Setexc
$e0113c=Tickcal
$e01144=Physbase
$e01160=Logbase
$e01166=Getrez
$e01172=Setscreen
$e011c8=Setpalette
$e011d0=Setcolor
$e01202=Puntaes
$e01450=Scrdmp
$e0156e=Gettime
$e0157c=Settime
$e015dc=Blitmode
$e01756=EsetShift
$e01786=EgetShift
$e0178e=EsetBank
$e017a6=EsetColor
$e017c8=EsetPalette
$e017f6=EgetPalette
$e01824=EsetGrey
$e01848=EsetSmear
$e0186c=DMAread
$e0187a=DMAwrite
$e0208c=NVMaccess
$e02266=keybd_ostat
$e02276=midi_out
$e0228c=Midiws
$e022a0=midi_stat
$e022ba=midi_in
$e022ee=centronic_out
$e02372=centronic_in
$e02394=centronic_ostat
$e023a4=RS232_stat
$e023ba=RS232_in
$e02406=RS232_ostat
$e0241e=RS232_out
$e02446=midi_ostat
$e02456=keybd_out
$e02474=Ikbdws
$e02488=console_stat
$e0249e=console_in
$e024d2=console_ostat
$e027b0=Mfpint
$e027da=Jdisint
$e02810=Jenabint
$e02a40=Iorec
$e02a60=Rsconf
$e02baa=Bconmap
$e03730=KCLICK
$e03824=Giaccess
$e0385c=Ongibit
$e03884=Offgibit
$e038ac=init_mouse
$e03974=Xbtimer
$e039ae=Keytbl
$e039da=Bioskeys
$e039f4=Dosound
$e03a08=Setprt
$e03a1a=Kbrate
$e03a3c=Kbdvbase
$e03b3e=BELL
$e03bb6=Floprd
$e03cb8=Flopwr
$e03da8=Flopfmt
$e03fa4=Flopver
$e0445c=Floprate
$e0457e=Prtblk
$e05580=HDV_init
$e055f8=Getdsb
$e05602=HDV_bpb
$e05854=HDV_mediach
$e05a3c=HDV_rwabs
$e05cde=Random
$e05d2e=HDV_boot
$e05daa=Protobt
$e07238=raw_out
$e07244=console_out
$e075f2=Cursconf
$e078d2=LINE_A
$e35fe4=zero_tttc
$e36a42=FONT_6X6
$e3d22e=PALET_VDI
$e3d42e=PALET_XBIOS
}
mark[1]={
$e000d8=set default low res palette
}
comm[16]={
$e00002=version
$e00030=supervisor mode no interrupts
$e00042=test diagnostic cartridge
$e0004c=present
$e0004e=return address
$e00052=jump to cartridge code
$e00058=$808 clear caches
$e00064=zero vector base register
$e00086=warm start ?
$e0009e=resmagic :: resvalid
$e000ba=sound chip
$e000be=Port A and B
$e000c2=for output
$e000c8=select port A
$e000cc=deselect floppies
$e000d2=Video ON
}
data={
1/156 1/89 1/153 3/85 69/0 1/64 1/85 1/21 180/0 4/255 1/3 37/0 1/192 4/255 83/0
1/80 3/85 1/5 54/0 1/148 5/153 1/89 47/102 1/38 14/0 1/144 15/153 1/9 70/0 1/64 3/85
1/21 5/0 1/255 1/159 1/9 52/0 1/84 1/213 1/127 3/85 1/21 24/0 1/4 539/0 1/84 7/85
1/101 1/102 1/2 16/0 4/255 84/0 1/144 1/153 25/0 1/252 3/255 1/103 11/102 1/2 41/0 1/64
5/85 1/1 150/0 1/80 3/85 1/149 7/153 1/89 4/85 25/0 2/255 1/15 9/0 1/144 7/153 123/0
1/192 1/3 357/0 1/192 1/3 1003/0 1/252 12/255 1/15 44/0 1/80 63/85 1/5 19/0 1/80 2/85
1/1 96/0 1/80 7/85 1/5 249/0 1/84 4/85 1/1 13/0 1/84 1/85 22/0 1/64 8/85 1/5
79/0 1/80 1/85 1/5 86/0 1/1 7/0 8/153 14/0 1/64 2/102 1/2 60/0 1/255 33/0 1/80
3/85 1/5 44/0 4/85 1/1 14/0 1/64 9/102 1/38 2231/0 1/64 6/102 1/38 118/0 9/85 1/21
350/0 18/153 18/0 8/153 9/0 1/80 3/85 1/21 144/0 1/100 3/102 1/2 34/0 1/64 3/102 1/38
139/0 1/80 1/85 1/5 27/0 2/85 197/0 8/85 15/255 1/15 490/0 16/153 13/0 1/64 15/102 1/38
31/0 1/100 23/102 1/2 24/0 1/144 23/153 1/9 28/0 24/153 28/0 24/153 1438/0 1/144 15/153 1/9
13/0 1/100 15/102 1/2 29/0 1/100 23/102 1/2 25/0 24/153 27/0 1/64 23/102 1/38 27/0 24/153
17779/0 1/153 1/89 234/85 1/245 63/255 1/127 14/85 8/153 6/85 1/101 3/102 1/214 2/255 1/95 216/85
1/253 2/255 1/87 839/85 1/213 3/255 1/127 7/85 4/255 1/87 2374/85 35/102 1/86 22/85 1/101 29/102
4/85 1/253 17/255 1/127 4/85 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150
1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101
1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89
1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/89 1/150
1/101 1/89 1/150 1/101 1/89 1/150 1/101 1/85 9/102 1/254 3/255 61/153 1/249 1/255 2/85 1/101
7/102 1/230 1/255 1/95 5/85 15/153 1/249 1/127 18/102 1/230 1/255 2/153 1/249 3/255 1/103 23/102
1/230 3/255 1/159 8/153 1/255 5/85 15/255 1/95 3/85 18/153 1/249 1/127 11/102 2/85 9/153 5/85
1/101 15/102 1/86 15/85 7/102 1/101 1/102 1/230 4/255 1/103 40/102 1/254 1/127 4/102 1/230 1/87
12/85 1/213 2/255 3/85 1/213 12/255 1/103 49/102 1/230 3/255 1/159 7/153 1/249 16/153 71/255 1/127
9/102 1/86 1/101 2/102 1/86 5/85 243/255 1/127 370/85
}
jump={
3645/0 1/92 4/85 1/1 13/0 1/92 1/85 22/0 1/192 3/85 1/87 4/85 1/5 79/0 1/112
1/85 1/5 3395/0 1/112 1/85 1/5 27/0 1/87 1/85 25561/0
}