240 lines
7.3 KiB
C
240 lines
7.3 KiB
C
/*
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* cache handling
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#include "cache.h"
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void cacr_set(uint32_t value)
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{
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extern uint32_t rt_cacr;
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rt_cacr = value;
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__asm__ __volatile__("movec %0, cacr\n\t"
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: /* output */
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: "r" (rt_cacr)
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: "memory" /* clobbers */);
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}
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uint32_t cacr_get(void)
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{
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extern uint32_t rt_cacr;
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return rt_cacr;
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}
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void disable_data_cache(void)
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{
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flush_and_invalidate_caches();
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cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
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}
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void disable_instruction_cache(void)
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{
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flush_and_invalidate_caches();
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cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
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}
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void enable_data_cache(void)
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{
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cacr_set(cacr_get() & ~CF_CACR_DCINVA);
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}
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void flush_and_invalidate_caches(void)
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{
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__asm__ __volatile__(
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" clr.l d0 \n\t"
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" clr.l d1 \n\t"
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" move.l d0,a0 \n\t"
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"cfa_setloop: \n\t"
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" cpushl bc,(a0) | flush\n\t"
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" lea 0x10(a0),a0 | index+1\n\t"
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" addq.l #1,d1 | index+1\n\t"
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" cmpi.w #512,d1 | all sets?\n\t"
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" bne.s cfa_setloop | no->\n\t"
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" clr.l d1 \n\t"
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" addq.l #1,d0 \n\t"
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" move.l d0,a0 \n\t"
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" cmpi.w #4,d0 | all ways?\n\t"
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" bne.s cfa_setloop | no->\n\t"
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/* input */ :
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/* output */ :
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/* clobber */ : "cc", "d0", "d1", "a0"
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);
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}
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/*
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* flush and invalidate a specific memory region from the instruction cache
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*/
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void flush_icache_range(void *address, size_t size)
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{
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uint32_t set;
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uint32_t start_set;
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uint32_t end_set;
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void *endaddr = address + size;
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start_set = (uint32_t) address & _ICACHE_SET_MASK;
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end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
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if (start_set > end_set) {
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/* from the begining to the lowest address */
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for (set = 0; set <= end_set; set += (0x10 - 3))
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{
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__asm__ __volatile__(
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set]) \n\t"
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: /* output parameters */
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: [set] "a" (set) /* input parameters */
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: "cc" /* clobbered registers */
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);
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}
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/* next loop will finish the cache ie pass the hole */
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end_set = LAST_ICACHE_ADDR;
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}
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for (set = start_set; set <= end_set; set += (0x10 - 3)) {
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__asm__ __volatile__(
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl ic,(%[set])"
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: /* output parameters */
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: [set] "a" (set)
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: "cc"
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);
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}
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}
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/*
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* flush and invalidate a specific region from the data cache
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*/
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void flush_dcache_range(void *address, size_t size)
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{
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unsigned long set;
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unsigned long start_set;
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unsigned long end_set;
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void *endaddr;
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endaddr = address + size;
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start_set = (uint32_t) address & _DCACHE_SET_MASK;
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end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
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if (start_set > end_set) {
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/* from the begining to the lowest address */
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for (set = 0; set <= end_set; set += (0x10 - 3))
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{
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__asm__ __volatile__(
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" cpushl dc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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: /* output parameters */
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: [set] "a" (set)
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: "cc" /* clobbered registers */
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);
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}
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/* next loop will finish the cache ie pass the hole */
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end_set = LAST_DCACHE_ADDR;
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}
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for (set = start_set; set <= end_set; set += (0x10 - 3))
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{
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__asm__ __volatile__(
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" cpushl dc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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" addq%.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl dc,(%[set]) \n\t"
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: /* output parameters */
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: [set] "a" (set)
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: "cc" /* clobbered registers */
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);
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}
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}
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/*
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* flush and invalidate a specific region from the both caches. We do not know if the area is cached
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* at all, we do not know in which of the four ways it is cached, but we know the index where they
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* would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
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* entries, but all four ways.
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*/
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void flush_cache_range(void *address, size_t size)
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{
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unsigned long set;
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unsigned long start_set;
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unsigned long end_set;
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void *endaddr;
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endaddr = address + size;
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start_set = (uint32_t) address & _DCACHE_SET_MASK;
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end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
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if (start_set > end_set) {
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/* from the begining to the lowest address */
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for (set = 0; set <= end_set; set += (0x10 - 3))
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{
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__asm__ __volatile__(
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" cpushl bc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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: /* output parameters */
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: [set] "a" (set)
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: "cc" /* clobbered registers */
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);
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}
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/* next loop will finish the cache ie pass the hole */
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end_set = LAST_DCACHE_ADDR;
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}
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for (set = start_set; set <= end_set; set += (0x10 - 3))
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{
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__asm__ __volatile__(
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" cpushl bc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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" addq%.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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" addq.l #1,%[set] \n\t"
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" cpushl bc,(%[set]) \n\t"
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: /* output parameters */
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: [set] "a" (set)
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: "cc" /* clobbered registers */
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);
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}
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}
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