112 lines
4.1 KiB
Verilog
112 lines
4.1 KiB
Verilog
// megafunction wizard: %LPM_MUX%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_MUX
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// ============================================================
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// File Name: lpm_mux5.v
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// Megafunction Name(s):
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// LPM_MUX
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_mux5 (
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data0x,
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data1x,
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data2x,
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data3x,
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sel,
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result);
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input [63:0] data0x;
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input [63:0] data1x;
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input [63:0] data2x;
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input [63:0] data3x;
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input [1:0] sel;
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output [63:0] result;
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wire [63:0] sub_wire0;
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wire [63:0] sub_wire5 = data3x[63:0];
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wire [63:0] sub_wire4 = data2x[63:0];
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wire [63:0] sub_wire3 = data1x[63:0];
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wire [63:0] result = sub_wire0[63:0];
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wire [63:0] sub_wire1 = data0x[63:0];
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wire [255:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
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lpm_mux LPM_MUX_component (
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.data (sub_wire2),
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.sel (sel),
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.result (sub_wire0)
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// synopsys translate_off
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,
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.aclr (),
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.clken (),
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.clock ()
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// synopsys translate_on
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);
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defparam
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LPM_MUX_component.lpm_size = 4,
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LPM_MUX_component.lpm_type = "LPM_MUX",
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LPM_MUX_component.lpm_width = 64,
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LPM_MUX_component.lpm_widths = 2;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
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// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
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// Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]"
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// Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]"
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// Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]"
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// Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]"
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// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
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// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
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// Retrieval info: CONNECT: @data 0 0 64 0 data0x 0 0 64 0
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// Retrieval info: CONNECT: @data 0 0 64 64 data1x 0 0 64 0
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// Retrieval info: CONNECT: @data 0 0 64 128 data2x 0 0 64 0
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// Retrieval info: CONNECT: @data 0 0 64 192 data3x 0 0 64 0
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// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
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// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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