682 lines
16 KiB
C
682 lines
16 KiB
C
#define RINFO_ONLY
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#include "x86debug.h"
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#include "radeonfb.h"
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#include "bas_printf.h"
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#include "bas_string.h"
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#include "util.h"
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#include "driver_mem.h"
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#include "x86emu.h"
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#include "pci.h"
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#include "pci_ids.h"
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#define USE_SDRAM
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#define DIRECT_ACCESS
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#define MEM_WB(where, what) wrb(where, what)
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#define MEM_WW(where, what) wrw(where, what)
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#define MEM_WL(where, what) wrl(where, what)
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#define MEM_RB(where) rdb(where)
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#define MEM_RW(where) rdw(where)
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#define MEM_RL(where) rdl(where)
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#define PCI_VGA_RAM_IMAGE_START 0xC0000
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#define PCI_RAM_IMAGE_START 0xD0000
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#define SYS_BIOS 0xF0000
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#define SIZE_EMU 0x100000
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typedef struct
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{
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long ident;
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union
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{
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long l;
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short i[2];
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char c[4];
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} v;
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} COOKIE;
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struct rom_header
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{
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uint16_t signature;
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uint8_t size;
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uint8_t init[3];
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uint8_t reserved[0x12];
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uint16_t data;
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};
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struct pci_data
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{
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uint32_t signature;
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uint16_t vendor;
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uint16_t device;
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uint16_t reserved_1;
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uint16_t dlen;
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uint8_t drevision;
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uint8_t class_lo;
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uint16_t class_hi;
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uint16_t ilen;
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uint16_t irevision;
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uint8_t type;
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uint8_t indicator;
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uint16_t reserved_2;
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};
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struct radeonfb_info *rinfo_biosemu;
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uint16_t offset_port;
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uint32_t offset_mem;
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static uint32_t offset_io;
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static uint32_t config_address_reg;
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extern int pcibios_handler();
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extern COOKIE *get_cookie(long id);
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extern short restart, os_magic;
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X86EMU_sysEnv _X86EMU_env;
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/* general software interrupt handler */
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uint32_t getIntVect(int num)
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{
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return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4);
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}
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/* FixME: There is already a push_word() in the emulator */
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void pushw(uint16_t val)
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{
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X86_ESP -= 2;
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MEM_WW(((uint32_t) X86_SS << 4) + X86_SP, val);
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}
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int run_bios_int(int num)
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{
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uint32_t eflags;
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eflags = X86_EFLAGS;
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pushw(eflags);
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pushw(X86_CS);
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pushw(X86_IP);
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X86_CS = MEM_RW((num << 2) + 2);
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X86_IP = MEM_RW(num << 2);
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return 1;
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}
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static uint8_t inb(uint16_t port)
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{
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uint8_t val = 0;
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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dbg("inb(");
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val = *(uint8_t *)(offset_io+(uint32_t)port);
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dbg("0x%x) = 0x%x\r\n", port, val);
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}
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return val;
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}
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static uint16_t inw(uint16_t port)
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{
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uint16_t val = 0;
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if ((port >= offset_port) && (port <= offset_port+0xFF))
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{
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dbg("inw(");
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val = swpw(*(uint16_t *)(offset_io+(uint32_t)port));
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dbg("0x%x) = 0x%x\r\n", port, val);
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}
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return val;
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}
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static uint32_t inl(uint16_t port)
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{
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uint32_t val = 0;
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if ((port >= offset_port) && (port <= offset_port+0xFF))
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{
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dbg("inl(");
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val = swpl(*(uint32_t *)(offset_io+(uint32_t)port));
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dbg("0x%x) = 0x%x\r\n", port, val);
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}
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else if (port == 0xCF8)
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{
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dbg("inl(");
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val = config_address_reg;
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dbg("0x%x) = 0x%x\r\n", port, val);
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}
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else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) != 0))
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{
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switch (config_address_reg & 0xFC)
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{
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case PCIIDR:
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val = ((uint32_t) rinfo_biosemu->chipset << 16) + PCI_VENDOR_ID_ATI;
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break;
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case PCIBAR1:
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val = (uint32_t) offset_port + 1;
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break;
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default:
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val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC);
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break;
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}
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dbg("inl(0x%x) = 0x%x\r\n", port, val);
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}
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return val;
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}
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void outb(uint8_t val, uint16_t port)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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dbg("outb(0x%x, 0x%x)\r\n", port, val);
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*(uint8_t *)(offset_io + (uint32_t) port) = val;
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}
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}
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void outw(uint16_t val, uint16_t port)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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dbg("outw(0x%x, 0x%x)\r\n", port, val);
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*(uint16_t *)(offset_io + (uint32_t) port) = swpw(val);
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}
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}
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void outl(uint32_t val, uint16_t port)
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{
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if ((port >= offset_port) && (port <= offset_port + 0xFF))
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{
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dbg("outl(0x%x, 0x%x)\r\n", port, val);
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*(uint32_t *)(offset_io + (uint32_t) port) = swpl(val);
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}
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else if (port == 0xCF8)
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{
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dbg("outl(0x%x, 0x%x)\r\n", port, val);
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config_address_reg = val;
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}
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else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) !=0))
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{
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if ((config_address_reg & 0xFC) == PCIBAR1)
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offset_port = (uint16_t)val & 0xFFFC;
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else
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{
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dbg("outl(0x%x, 0x%x)\r\n", port, val);
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pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val);
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}
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}
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}
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/* Interrupt multiplexer */
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void do_int(int num)
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{
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int ret = 0;
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switch (num)
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{
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#ifndef _PC
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case 0x10:
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case 0x42:
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case 0x6D:
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if (getIntVect(num) == 0x0000)
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dbg("uninitialised int vector\r\n");
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if (getIntVect(num) == 0xFF065)
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{
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//ret = int42_handler();
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ret = 1;
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}
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break;
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#endif
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case 0x15:
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//ret = int15_handler();
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ret = 1;
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break;
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case 0x16:
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//ret = int16_handler();
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ret = 0;
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break;
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case 0x1A:
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ret = pcibios_handler();
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ret = 1;
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break;
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case 0xe6:
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//ret = intE6_handler();
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ret = 0;
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break;
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default:
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break;
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}
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if (!ret)
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ret = run_bios_int(num);
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}
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#if 0
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void reset_int_vect(void)
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{
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/*
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* This table is normally located at 0xF000:0xF0A4. However, int 0x42,
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* function 0 (Mode Set) expects it (or a copy) somewhere in the bottom
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* 64kB. Note that because this data doesn't survive POST, int 0x42 should
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* only be used during EGA/VGA BIOS initialisation.
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*/
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static const uint8_t VideoParms[] = {
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/* Timing for modes 0x00 & 0x01 */
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0x38, 0x28, 0x2d, 0x0a, 0x1f, 0x06, 0x19, 0x1c,
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0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
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/* Timing for modes 0x02 & 0x03 */
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0x71, 0x50, 0x5a, 0x0a, 0x1f, 0x06, 0x19, 0x1c,
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0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
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/* Timing for modes 0x04, 0x05 & 0x06 */
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0x38, 0x28, 0x2d, 0x0a, 0x7f, 0x06, 0x64, 0x70,
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0x02, 0x01, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
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/* Timing for mode 0x07 */
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0x61, 0x50, 0x52, 0x0f, 0x19, 0x06, 0x19, 0x19,
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0x02, 0x0d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
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/* Display page lengths in little endian order */
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0x00, 0x08, /* Modes 0x00 and 0x01 */
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0x00, 0x10, /* Modes 0x02 and 0x03 */
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0x00, 0x40, /* Modes 0x04 and 0x05 */
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0x00, 0x40, /* Modes 0x06 and 0x07 */
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/* Number of columns for each mode */
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40, 40, 80, 80, 40, 40, 80, 80,
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/* CGA Mode register value for each mode */
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0x2c, 0x28, 0x2d, 0x29, 0x2a, 0x2e, 0x1e, 0x29,
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/* Padding */
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0x00, 0x00, 0x00, 0x00
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};
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int i;
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for(i = 0; i < sizeof(VideoParms); i++)
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MEM_WB(i + (0x1000 - sizeof(VideoParms)), VideoParms[i]);
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MEM_WW(0x1d << 2, 0x1000 - sizeof(VideoParms));
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MEM_WW((0x1d << 2) + 2, 0);
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DPRINT("SETUP INT\r\n");
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MEM_WW(0x10 << 2, 0xf065);
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MEM_WW((0x10 << 2) + 2, SYS_BIOS >> 4);
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MEM_WW(0x42 << 2, 0xf065);
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MEM_WW((0x42 << 2) + 2, SYS_BIOS >> 4);
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MEM_WW(0x6D << 2, 0xf065);
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MEM_WW((0x6D << 2) + 2, SYS_BIOS >> 4);
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}
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/*
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* here we are really paranoid about faking a "real"
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* BIOS. Most of this information was pulled from
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* dosemu.
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*/
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void setup_int_vect(void)
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{
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int i;
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/* let the int vects point to the SYS_BIOS seg */
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for(i = 0; i < 0x80; i++)
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{
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MEM_WW(i << 2, 0);
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MEM_WW((i << 2) + 2, SYS_BIOS >> 4);
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}
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reset_int_vect();
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/* font tables default location (int 1F) */
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MEM_WW(0x1f << 2, 0xfa6e);
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/* int 11 default location (Get Equipment Configuration) */
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MEM_WW(0x11 << 2, 0xf84d);
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/* int 12 default location (Get Conventional Memory Size) */
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MEM_WW(0x12 << 2, 0xf841);
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/* int 15 default location (I/O System Extensions) */
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MEM_WW(0x15 << 2, 0xf859);
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/* int 1A default location (RTC, PCI and others) */
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MEM_WW(0x1a << 2, 0xff6e);
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/* int 05 default location (Bound Exceeded) */
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MEM_WW(0x05 << 2, 0xff54);
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/* int 08 default location (Double Fault) */
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MEM_WW(0x08 << 2, 0xfea5);
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/* int 13 default location (Disk) */
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MEM_WW(0x13 << 2, 0xec59);
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/* int 0E default location (Page Fault) */
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MEM_WW(0x0e << 2, 0xef57);
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/* int 17 default location (Parallel Port) */
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MEM_WW(0x17 << 2, 0xefd2);
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/* fdd table default location (int 1e) */
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MEM_WW(0x1e << 2, 0xefc7);
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/* Set Equipment flag to VGA */
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i = MEM_RB(0x0410) & 0xCF;
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MEM_WB(0x0410, i);
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/* XXX Perhaps setup more of the BDA here. See also int42(0x00). */
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}
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#endif
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static int setup_system_bios(void *base_addr)
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{
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char *base = (char *) base_addr;
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int i;
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/*
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* we trap the "industry standard entry points" to the BIOS
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* and all other locations by filling them with "hlt"
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* TODO: implement hlt-handler for these
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*/
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// for(i=0; i<0x10000; base[i++]=0xF4);
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for(i=0; i<SIZE_EMU; base[i++]=0xF4);
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/* set bios date */
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//strcpy(base + 0x0FFF5, "06/11/99");
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/* set up eisa ident string */
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//strcpy(base + 0x0FFD9, "PCI_ISA");
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/* write system model id for IBM-AT */
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//*((unsigned char *) (base + 0x0FFFE)) = 0xfc;
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return(1);
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}
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#if 0
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static void memsetw(uint32_t addr, uint16_t value, uint16_t count)
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{
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while(--count)
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{
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wrw(addr, value);
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addr += 2;
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}
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}
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static uint8_t find_vga_entry(uint8_t mode)
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{
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uint8_t i,line=0xFF;
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for(i=0;i<=MODE_MAX;i++)
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{
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if (vga_modes[i].svgamode==mode)
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{
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line=i;
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break;
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}
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}
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return(line);
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}
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void biosfn_set_video_mode(uint8_t mode)
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{
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uint8_t line,mmask,*palette=0,vpti;
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uint16_t i,twidth,theightm1,cheight;
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uint8_t modeset_ctl=0;
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uint16_t crtc_addr;
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// find the entry in the video modes
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line=find_vga_entry(mode);
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if (line==0xFF)
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return;
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vpti=line_to_vpti[line];
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twidth=video_param_table[vpti].twidth;
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theightm1=video_param_table[vpti].theightm1;
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cheight=video_param_table[vpti].cheight;
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// if palette loading (bit 3 of modeset ctl = 0)
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if ((modeset_ctl&0x08)==0)
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{
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// Set the PEL mask
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outb(vga_modes[line].pelmask,VGAREG_PEL_MASK);
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// Set the whole dac always, from 0
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outb(0x00,VGAREG_DAC_WRITE_ADDRESS);
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// From which palette
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switch(vga_modes[line].dacmodel)
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{
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case 0: palette=palette0; break;
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case 1: palette=palette1; break;
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case 2: palette=palette2; break;
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case 3: palette=palette3; break;
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}
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// Always 256*3 values
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for(i=0;i<0x0100;i++)
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{
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if (i<=dac_regs[vga_modes[line].dacmodel])
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{
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outb(palette[(i*3)+0],VGAREG_DAC_DATA);
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outb(palette[(i*3)+1],VGAREG_DAC_DATA);
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outb(palette[(i*3)+2],VGAREG_DAC_DATA);
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}
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else
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{
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outb(0,VGAREG_DAC_DATA);
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outb(0,VGAREG_DAC_DATA);
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outb(0,VGAREG_DAC_DATA);
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}
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}
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if ((modeset_ctl&0x02)==0x02)
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{
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uint8_t r,g,b;
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uint16_t i;
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uint16_t index,start=0;
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inb(VGAREG_ACTL_RESET);
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outb(0x00,VGAREG_ACTL_ADDRESS);
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for(index = 0; index < 0x100; index++)
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{
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// set read address and switch to read mode
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outb(start,VGAREG_DAC_READ_ADDRESS);
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// get 6-bit wide RGB data values
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r=inb(VGAREG_DAC_DATA);
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g=inb(VGAREG_DAC_DATA);
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b=inb(VGAREG_DAC_DATA);
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// intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
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i = ((77*r + 151*g + 28*b) + 0x80) >> 8;
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if (i>0x3f)
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i=0x3f;
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// set write address and switch to write mode
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outb(start,VGAREG_DAC_WRITE_ADDRESS);
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// write new intensity value
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outb(i & 0xff,VGAREG_DAC_DATA);
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outb(i & 0xff,VGAREG_DAC_DATA);
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outb(i & 0xff,VGAREG_DAC_DATA);
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start++;
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}
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inb(VGAREG_ACTL_RESET);
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outb(0x20,VGAREG_ACTL_ADDRESS);
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}
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}
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// Reset Attribute Ctl flip-flop
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inb(VGAREG_ACTL_RESET);
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// Set Attribute Ctl
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for(i=0;i<=0x13;i++)
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{
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outb(i,VGAREG_ACTL_ADDRESS);
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outb(video_param_table[vpti].actl_regs[i],VGAREG_ACTL_WRITE_DATA);
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}
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outb(0x14,VGAREG_ACTL_ADDRESS);
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outb(0x00,VGAREG_ACTL_WRITE_DATA);
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// Set Sequencer Ctl
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outb(0,VGAREG_SEQU_ADDRESS);
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outb(0x03,VGAREG_SEQU_DATA);
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for(i=1;i<=4;i++)
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{
|
|
outb(i,VGAREG_SEQU_ADDRESS);
|
|
outb(video_param_table[vpti].sequ_regs[i - 1],VGAREG_SEQU_DATA);
|
|
}
|
|
// Set Grafx Ctl
|
|
for(i=0;i<=8;i++)
|
|
{
|
|
outb(i,VGAREG_GRDC_ADDRESS);
|
|
outb(video_param_table[vpti].grdc_regs[i],VGAREG_GRDC_DATA);
|
|
}
|
|
// Set CRTC address VGA
|
|
crtc_addr=VGAREG_VGA_CRTC_ADDRESS;
|
|
// Disable CRTC write protection
|
|
outw(crtc_addr,0x0011);
|
|
// Set CRTC regs
|
|
for(i=0;i<=0x18;i++)
|
|
{
|
|
outb(i,crtc_addr);
|
|
outb(video_param_table[vpti].crtc_regs[i],crtc_addr+1);
|
|
}
|
|
// Set the misc register
|
|
outb(video_param_table[vpti].miscreg,VGAREG_WRITE_MISC_OUTPUT);
|
|
// Enable video
|
|
outb(0x20,VGAREG_ACTL_ADDRESS);
|
|
inb(VGAREG_ACTL_RESET);
|
|
if (mode<0x0d)
|
|
memsetw(vga_modes[line].sstart,0x0000,0x4000); // 32k
|
|
else
|
|
{
|
|
outb(0x02, VGAREG_SEQU_ADDRESS);
|
|
mmask = inb(VGAREG_SEQU_DATA);
|
|
outb(0x0f, VGAREG_SEQU_DATA); // all planes
|
|
memsetw(vga_modes[line].sstart, 0x0000, 0x8000); // 64k
|
|
outb(mmask, VGAREG_SEQU_DATA);
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
void run_bios(struct radeonfb_info *rinfo)
|
|
{
|
|
long i, j;
|
|
unsigned char *ptr;
|
|
struct rom_header *rom_header;
|
|
struct pci_data *rom_data;
|
|
unsigned long rom_size=0;
|
|
unsigned long image_size=0;
|
|
unsigned long biosmem = 0x01000000; /* when run_bios() is called, SDRAM is valid but not added to the system */
|
|
unsigned long addr;
|
|
unsigned short initialcs;
|
|
unsigned short initialip;
|
|
unsigned short devfn = (unsigned short) rinfo->handle;
|
|
X86EMU_intrFuncs intFuncs[256];
|
|
|
|
if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL))
|
|
{
|
|
dbg("%s: rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", __FUNCTION__);
|
|
return;
|
|
}
|
|
rinfo_biosemu = rinfo;
|
|
config_address_reg = 0;
|
|
offset_port = 0x300;
|
|
#ifdef DIRECT_ACCESS
|
|
offset_io = (uint32_t) rinfo->io_base - (uint32_t) offset_port;
|
|
offset_mem = (uint32_t) rinfo->fb_base - 0xA0000;
|
|
#else
|
|
offset_io = rinfo->io_base_phys -(uint32_t) offset_port;
|
|
offset_mem = rinfo->fb_base_phys - 0xA0000;
|
|
#endif
|
|
rom_header = (struct rom_header *) 0;
|
|
do
|
|
{
|
|
rom_header = (struct rom_header *)((unsigned long)rom_header + image_size); // get next image
|
|
rom_data = (struct pci_data *)((unsigned long)rom_header + (unsigned long)BIOS_IN16((long)&rom_header->data));
|
|
image_size = (unsigned long)BIOS_IN16((long)&rom_data->ilen) * 512;
|
|
} while ((BIOS_IN8((long) &rom_data->type) != 0) && (BIOS_IN8((long) &rom_data->indicator) != 0)); // make sure we got x86 version
|
|
if (BIOS_IN8((long) &rom_data->type) != 0)
|
|
{
|
|
dbg("%s: ROM data type = 0x%x\r\n", __FUNCTION__, BIOS_IN8((long) &rom_data->type));
|
|
return;
|
|
}
|
|
rom_size = (unsigned long) BIOS_IN8((long) &rom_header->size) * 512;
|
|
if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi))
|
|
{
|
|
biosmem = driver_mem_alloc(SIZE_EMU);
|
|
if (biosmem == 0)
|
|
{
|
|
dbg("%s: could not allocate X86 BIOS memory\r\n", __FUNCTION__);
|
|
return;
|
|
}
|
|
memset((char *) biosmem, 0, SIZE_EMU);
|
|
setup_system_bios((char *) biosmem);
|
|
dbg("Copying VGA ROM Image from %p to %p (0x%lx bytes)\r\n", (long) rinfo->bios_seg + (long) rom_header,
|
|
biosmem + PCI_VGA_RAM_IMAGE_START, rom_size);
|
|
{
|
|
long bytes_align = (long) rom_header & 3;
|
|
|
|
ptr = (unsigned char *) biosmem;
|
|
i = (long) rom_header;
|
|
j = PCI_VGA_RAM_IMAGE_START;
|
|
if (bytes_align)
|
|
for(; i < 4 - bytes_align; ptr[j++] = BIOS_IN8(i++));
|
|
for(; i < (long) rom_header + rom_size; *((unsigned long *)&ptr[j]) = swpl(BIOS_IN32(i)), i += 4, j += 4);
|
|
}
|
|
addr = PCI_VGA_RAM_IMAGE_START;
|
|
}
|
|
else
|
|
{
|
|
#ifdef USE_SDRAM
|
|
#if 0
|
|
if (os_magic)
|
|
{
|
|
biosmem = Mxalloc(SIZE_EMU, 3);
|
|
if (biosmem == 0)
|
|
return;
|
|
}
|
|
#endif
|
|
#else
|
|
biosmem = Mxalloc(SIZE_EMU, 0);
|
|
if (biosmem == 0)
|
|
return;
|
|
#endif /* USE_SDRAM */
|
|
setup_system_bios((char *)biosmem);
|
|
memset((char *)biosmem, 0, SIZE_EMU);
|
|
dbg("Copying non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
|
|
(long) rinfo->bios_seg + (long) rom_header,
|
|
biosmem + PCI_RAM_IMAGE_START,
|
|
rom_size);
|
|
ptr = (unsigned char *) biosmem;
|
|
for (i = (long) rom_header, j = PCI_RAM_IMAGE_START; i < (long) rom_header+rom_size; ptr[j++] = BIOS_IN8(i++));
|
|
addr = PCI_RAM_IMAGE_START;
|
|
}
|
|
initialcs = (addr & 0xF0000) >> 4;
|
|
initialip = (addr + 3) & 0xFFFF;
|
|
X86EMU_setMemBase((void *) biosmem, SIZE_EMU);
|
|
for (i = 0; i < 256; i++)
|
|
intFuncs[i] = do_int;
|
|
X86EMU_setupIntrFuncs(intFuncs);
|
|
{
|
|
char *date = "01/01/99";
|
|
for (i = 0; date[i]; i++)
|
|
wrb(0xffff5 + i, date[i]);
|
|
wrb(0xffff7, '/');
|
|
wrb(0xffffa, '/');
|
|
}
|
|
{
|
|
/* FixME: move PIT init to its own file */
|
|
outb(0x36, 0x43);
|
|
outb(0x00, 0x40);
|
|
outb(0x00, 0x40);
|
|
}
|
|
// setup_int_vect();
|
|
|
|
/* cpu setup */
|
|
X86_AX = devfn ? devfn : 0xff;
|
|
X86_DX = 0x80;
|
|
X86_EIP = initialip;
|
|
X86_CS = initialcs;
|
|
/* Initialize stack and data segment */
|
|
X86_SS = initialcs;
|
|
X86_SP = 0xfffe;
|
|
X86_DS = 0x0040;
|
|
X86_ES = 0x0000;
|
|
|
|
/* We need a sane way to return from bios
|
|
* execution. A hlt instruction and a pointer
|
|
* to it, both kept on the stack, will do.
|
|
*/
|
|
pushw(0xf4f4); /* hlt; hlt */
|
|
// pushw(0x10cd); /* int #0x10 */
|
|
// pushw(0x0013); /* 320 x 200 x 256 colors */
|
|
// // pushw(0x000F); /* 640 x 350 x mono */
|
|
// pushw(0xb890); /* nop, mov ax,#0x13 */
|
|
pushw(X86_SS);
|
|
pushw(X86_SP + 2);
|
|
#ifdef DEBUG_X86EMU
|
|
X86EMU_trace_on();
|
|
X86EMU_set_debug(DEBUG_DECODE_F | DEBUG_TRACE_F);
|
|
#endif
|
|
dbg("X86EMU entering emulator\r\n");
|
|
//*vblsem = 0;
|
|
X86EMU_exec();
|
|
//*vblsem = 1;
|
|
dbg("X86EMU halted\r\n");
|
|
// biosfn_set_video_mode(0x13); /* 320 x 200 x 256 colors */
|
|
#ifdef USE_SDRAM
|
|
#if 0
|
|
if (os_magic)
|
|
{
|
|
memset((char *)biosmem, 0, SIZE_EMU);
|
|
Mfree(biosmem);
|
|
}
|
|
#endif
|
|
#else
|
|
memset((char *) biosmem, 0, SIZE_EMU);
|
|
driver_mem_free(biosmem);
|
|
#endif /* USE_SDRAM */
|
|
}
|