676 lines
20 KiB
VHDL
676 lines
20 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera;
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USE altera.altera_primitives_components.all;
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LIBRARY work;
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ENTITY firebee1 IS
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PORT
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(
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FB_ALE : IN std_logic;
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nFB_WR : IN std_logic;
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nFB_CS1 : IN std_logic;
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nFB_CS2 : IN std_logic;
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nFB_CS3 : IN std_logic;
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FB_SIZE0 : IN std_logic;
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FB_SIZE1 : IN std_logic;
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nFB_BURST : IN std_logic;
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LP_BUSY : IN std_logic;
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nACSI_DRQ : IN std_logic;
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nACSI_INT : IN std_logic;
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RxD : IN std_logic;
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CTS : IN std_logic;
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RI : IN std_logic;
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DCD : IN std_logic;
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AMKB_RX : IN std_logic;
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PIC_AMKB_RX : IN std_logic;
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IDE_RDY : IN std_logic;
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IDE_INT : IN std_logic;
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WP_CF_CARD : IN std_logic;
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TRACK00 : IN std_logic;
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nWP : IN std_logic;
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nDCHG : IN std_logic;
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SD_DATA0 : IN std_logic;
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SD_DATA1 : IN std_logic;
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SD_DATA2 : IN std_logic;
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SD_CARD_DEDECT : IN std_logic;
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nSCSI_DRQ : IN std_logic;
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SD_WP : IN std_logic;
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nRD_DATA : IN std_logic;
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nSCSI_C_D : IN std_logic;
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nSCSI_I_O : IN std_logic;
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nSCSI_MSG : IN std_logic;
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nDACK0 : IN std_logic;
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PIC_INT : IN std_logic;
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nFB_OE : IN std_logic;
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TOUT0 : IN std_logic;
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nMASTER : IN std_logic;
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DVI_INT : IN std_logic;
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nDACK1 : IN std_logic;
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nPCI_INTD : IN std_logic;
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nPCI_INTC : IN std_logic;
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nPCI_INTB : IN std_logic;
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nPCI_INTA : IN std_logic;
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E0_INT : IN std_logic;
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nINDEX : IN std_logic;
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HD_DD : IN std_logic;
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MAIN_CLK : IN std_logic;
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nRSTO_MCF : IN std_logic;
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CLK33MDIR : IN std_logic;
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SCSI_PAR : INOUT std_logic;
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nSCSI_RST : INOUT std_logic;
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nSCSI_SEL : INOUT std_logic;
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nSCSI_BUSY : INOUT std_logic;
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SD_CD_DATA3 : INOUT std_logic;
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SD_CMD_D1 : INOUT std_logic;
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MIDI_IN_PIN : INOUT std_logic;
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ACSI_D : INOUT std_logic_vector(7 DOWNTO 0);
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FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
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IO : INOUT std_logic_vector(17 DOWNTO 0);
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LP_D : INOUT std_logic_vector(7 DOWNTO 0);
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SCSI_D : INOUT std_logic_vector(7 DOWNTO 0);
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SRD : INOUT std_logic_vector(15 DOWNTO 0);
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VD : INOUT std_logic_vector(31 DOWNTO 0);
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VDQS : INOUT std_logic_vector(3 DOWNTO 0);
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LP_STR : OUT std_logic;
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nACSI_ACK : OUT std_logic;
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nACSI_RESET : OUT std_logic;
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nACSI_CS : OUT std_logic;
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ACSI_DIR : OUT std_logic;
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ACSI_A1 : OUT std_logic;
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nSCSI_ACK : OUT std_logic;
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nSCSI_ATN : OUT std_logic;
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SCSI_DIR : OUT std_logic;
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MIDI_TLR : OUT std_logic;
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TxD : OUT std_logic;
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RTS : OUT std_logic;
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DTR : OUT std_logic;
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AMKB_TX : OUT std_logic;
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IDE_RES : OUT std_logic;
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nIDE_CS0 : OUT std_logic;
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nIDE_CS1 : OUT std_logic;
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nIDE_WR : OUT std_logic;
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nIDE_RD : OUT std_logic;
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nCF_CS0 : OUT std_logic;
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nCF_CS1 : OUT std_logic;
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nROM3 : OUT std_logic;
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nROM4 : OUT std_logic;
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nRP_UDS : OUT std_logic;
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nRP_LDS : OUT std_logic;
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nSDSEL : OUT std_logic;
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nWR_GATE : OUT std_logic;
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nWR : OUT std_logic;
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YM_QA : OUT std_logic;
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YM_QB : OUT std_logic;
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YM_QC : OUT std_logic;
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SD_CLK : OUT std_logic;
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DSA_D : OUT std_logic;
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nVWE : OUT std_logic;
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nVCAS : OUT std_logic;
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nVRAS : OUT std_logic;
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nVCS : OUT std_logic;
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nPD_VGA : OUT std_logic;
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TIN0 : OUT std_logic;
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nSRCS : OUT std_logic;
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nSRBLE : OUT std_logic;
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nSRBHE : OUT std_logic;
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nSRWE : OUT std_logic;
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nDREQ1 : OUT std_logic;
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LED_FPGA_OK : OUT std_logic;
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nSROE : OUT std_logic;
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VCKE : OUT std_logic;
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nFB_TA : OUT std_logic;
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nDDR_CLK : OUT std_logic;
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DDR_CLK : OUT std_logic;
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VSYNC_PAD : OUT std_logic;
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HSYNC_PAD : OUT std_logic;
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nBLANK_PAD : OUT std_logic;
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PIXEL_CLK_PAD : OUT std_logic;
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nSYNC : OUT std_logic;
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nMOT_ON : OUT std_logic;
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nSTEP_DIR : OUT std_logic;
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nSTEP : OUT std_logic;
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LPDIR : OUT std_logic;
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MIDI_OLR : OUT std_logic;
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CLK25M : OUT std_logic;
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CLKUSB : OUT std_logic;
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CLK24M576 : OUT std_logic;
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BA : OUT std_logic_vector(1 DOWNTO 0);
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nIRQ : OUT std_logic_vector(7 DOWNTO 2);
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VA : OUT std_logic_vector(12 DOWNTO 0);
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VB : OUT std_logic_vector(7 DOWNTO 0);
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VDM : OUT std_logic_vector(3 DOWNTO 0);
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VG : OUT std_logic_vector(7 DOWNTO 0);
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VR : OUT std_logic_vector(7 DOWNTO 0)
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);
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END firebee1;
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ARCHITECTURE rtl OF firebee1 IS
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SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0);
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SIGNAL clk25m_i : std_logic;
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SIGNAL CLK2M : std_logic;
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SIGNAL CLK2M4576 : std_logic;
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SIGNAL CLK33M : std_logic;
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SIGNAL CLK48M : std_logic;
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SIGNAL CLK500k : std_logic;
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SIGNAL CLK_VIDEO : std_logic;
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SIGNAL DDR_SYNC_66M : std_logic;
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SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0);
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SIGNAL DMA_DRQ : std_logic;
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SIGNAL DSP_INT : std_logic;
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SIGNAL DSP_TA : std_logic;
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SIGNAL FALCON_IO_TA : std_logic;
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SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0);
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SIGNAL FDC_CLK : std_logic;
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SIGNAL HSYNC : std_logic;
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SIGNAL INT_HANDLER_TA : std_logic;
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SIGNAL LP_DIR : std_logic;
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SIGNAL MIDI_IN : std_logic;
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SIGNAL MOT_ON : std_logic;
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SIGNAL nBLANK : std_logic;
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SIGNAL nDREQ0 : std_logic;
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SIGNAL nMFP_INT : std_logic;
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SIGNAL nRSTO : std_logic;
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SIGNAL PIXEL_CLK : std_logic;
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SIGNAL SD_CDM_D1 : std_logic;
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SIGNAL STEP : std_logic;
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SIGNAL STEP_DIR : std_logic;
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SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0);
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SIGNAL VIDEO_RECONFIG : std_logic;
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SIGNAL Video_TA : std_logic;
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SIGNAL VR_BUSY : std_logic;
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SIGNAL VR_D : std_logic_vector(8 DOWNTO 0);
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SIGNAL VR_RD : std_logic;
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SIGNAL VR_WR : std_logic;
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SIGNAL VSYNC : std_logic;
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SIGNAL WR_DATA : std_logic;
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SIGNAL WR_GATE : std_logic;
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SIGNAL scandataout : std_logic;
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SIGNAL scandone : std_logic;
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SIGNAL reset : std_logic;
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SIGNAL pll_reset : std_logic;
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SIGNAL scanclk : std_logic;
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SIGNAL scandata : std_logic;
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SIGNAL scan_clkena : std_logic;
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SIGNAL config_update : std_logic;
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SIGNAL pll3_locked : std_logic;
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SIGNAL pll1_locked : std_logic;
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SIGNAL nSRCS_i : std_logic;
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SIGNAL nFB_WR_i : std_logic;
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SIGNAL nIDE_RD_i : std_logic;
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SIGNAL nIDE_WR_i : std_logic;
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COMPONENT altpll_reconfig1
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PORT
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(
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clock : IN std_logic ;
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counter_param : IN std_logic_vector (2 DOWNTO 0);
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counter_type : IN std_logic_vector (3 DOWNTO 0);
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data_in : IN std_logic_vector (8 DOWNTO 0);
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pll_areset_in : IN std_logic := '0';
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pll_scandataout : IN std_logic ;
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pll_scandone : IN std_logic ;
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read_param : IN std_logic ;
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reconfig : IN std_logic ;
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reset : IN std_logic ;
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write_param : IN std_logic ;
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busy : OUT std_logic ;
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data_out : OUT std_logic_vector (8 DOWNTO 0);
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pll_areset : OUT std_logic ;
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pll_configupdate : OUT std_logic ;
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pll_scanclk : OUT std_logic ;
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pll_scanclkena : OUT std_logic ;
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pll_scandata : OUT std_logic
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);
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END COMPONENT altpll_reconfig1;
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COMPONENT altpll4
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PORT
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(
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areset : IN std_logic := '0';
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configupdate : IN std_logic := '0';
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inclk0 : IN std_logic := '0';
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scanclk : IN std_logic := '1';
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scanclkena : IN std_logic := '0';
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scandata : IN std_logic := '0';
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c0 : OUT std_logic ;
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locked : OUT std_logic ;
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scandataout : OUT std_logic ;
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scandone : OUT std_logic
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);
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END COMPONENT altpll4;
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COMPONENT video
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PORT
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(
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FB_ADR : IN std_logic_vector(31 DOWNTO 0);
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MAIN_CLK : IN std_logic;
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nFB_CS1 : IN std_logic;
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nFB_CS2 : IN std_logic;
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nFB_CS3 : IN std_logic;
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nFB_WR : IN std_logic;
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FB_SIZE0 : IN std_logic;
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FB_SIZE1 : IN std_logic;
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nRSTO : IN std_logic;
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nFB_OE : IN std_logic;
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FB_ALE : IN std_logic;
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DDRCLK : IN std_logic_vector(3 DOWNTO 0);
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DDR_SYNC_66M : IN std_logic;
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CLK33M : IN std_logic;
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CLK25M : IN std_logic;
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CLK_VIDEO : IN std_logic;
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VR_D : IN std_logic_vector(8 DOWNTO 0);
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VR_BUSY : IN std_logic;
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VG : OUT std_logic_vector(7 DOWNTO 0);
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VB : OUT std_logic_vector(7 DOWNTO 0);
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VR : OUT std_logic_vector(7 DOWNTO 0);
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nBLANK : OUT std_logic;
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VA : OUT std_logic_vector(12 DOWNTO 0);
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nVWE : OUT std_logic;
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nVCAS : OUT std_logic;
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nVRAS : OUT std_logic;
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nVCS : OUT std_logic;
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VDM : OUT std_logic_vector(3 DOWNTO 0);
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nPD_VGA : OUT std_logic;
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VCKE : OUT std_logic;
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VSYNC : OUT std_logic;
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HSYNC : OUT std_logic;
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nSYNC : OUT std_logic;
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VIDEO_TA : OUT std_logic;
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PIXEL_CLK : OUT std_logic;
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BA : OUT std_logic_vector(1 DOWNTO 0);
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VIDEO_RECONFIG : OUT std_logic;
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VR_WR : OUT std_logic;
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VR_RD : OUT std_logic;
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VDQS : INOUT std_logic_vector(3 DOWNTO 0);
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FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
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VD : INOUT std_logic_vector(31 DOWNTO 0)
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);
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END COMPONENT video;
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BEGIN
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nDREQ1 <= nDACK1;
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i_atari_clk_pll : work.altpll3
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PORT MAP
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(
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inclk0 => MAIN_CLK,
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c0 => clk25m_i,
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c1 => CLK2M,
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c2 => CLK500k,
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c3 => CLK2M4576,
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locked => pll3_locked
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);
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i_ddr_clk_pll : work.altpll2
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PORT MAP
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(
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inclk0 => MAIN_CLK,
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c0 => DDRCLK(0),
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c1 => DDRCLK(1),
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c2 => DDRCLK(2),
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c3 => DDRCLK(3),
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c4 => DDR_SYNC_66M
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);
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i_dsp : work.dsp
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PORT MAP
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(
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CLK33M => CLK33M,
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MAIN_CLK => MAIN_CLK,
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nFB_OE => nFB_OE,
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nFB_WR => nFB_WR,
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nFB_CS1 => nFB_CS1,
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nFB_CS2 => nFB_CS2,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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nFB_BURST => nFB_BURST,
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nRSTO => nRSTO,
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nFB_CS3 => nFB_CS3,
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FB_AD => FB_AD,
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FB_ADR => FB_ADR,
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IO => IO,
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SRD => SRD,
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nSRCS => nSRCS_i,
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nSRBLE => nSRBLE,
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nSRBHE => nSRBHE,
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nSRWE => nSRWE,
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nSROE => nSROE,
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DSP_INT => DSP_INT,
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DSP_TA => DSP_TA
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);
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i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf
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PORT MAP
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(
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CLK33M => CLK33M,
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MAIN_CLK => MAIN_CLK,
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CLK2M => CLK2M,
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CLK500k => CLK500k,
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nFB_CS1 => nFB_CS1,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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nFB_BURST => nFB_BURST,
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LP_BUSY => LP_BUSY,
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nACSI_DRQ => nACSI_DRQ,
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nACSI_INT => nACSI_INT,
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nSCSI_DRQ => nSCSI_DRQ,
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nSCSI_MSG => nSCSI_MSG,
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MIDI_IN => MIDI_IN,
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RxD => RxD,
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CTS => CTS,
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RI => RI,
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DCD => DCD,
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AMKB_RX => AMKB_RX,
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PIC_AMKB_RX => PIC_AMKB_RX,
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IDE_RDY => IDE_RDY,
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IDE_INT => IDE_INT,
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WP_CS_CARD => '0',
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nINDEX => nINDEX,
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TRACK00 => TRACK00,
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nRD_DATA => nRD_DATA,
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nDCHG => nDCHG,
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SD_DATA0 => SD_DATA0,
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SD_DATA1 => SD_DATA1,
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SD_DATA2 => SD_DATA2,
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SD_CARD_DEDECT => SD_CARD_DEDECT,
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SD_WP => SD_WP,
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nDACK0 => nDACK0,
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nFB_WR => nFB_WR,
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WP_CF_CARD => WP_CF_CARD,
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nWP => nWP,
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nFB_CS2 => nFB_CS2,
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nRSTO => nRSTO,
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nSCSI_C_D => nSCSI_C_D,
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nSCSI_I_O => nSCSI_I_O,
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CLK2M4576 => CLK2M4576,
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nFB_OE => nFB_OE,
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VSYNC => VSYNC,
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HSYNC => HSYNC,
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DSP_INT => DSP_INT,
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nBLANK => nBLANK,
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FDC_CLK => FDC_CLK,
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FB_ALE => FB_ALE,
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HD_DD => HD_DD,
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SCSI_PAR => SCSI_PAR,
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nSCSI_SEL => nSCSI_SEL,
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nSCSI_BUSY => nSCSI_BUSY,
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nSCSI_RST => nSCSI_RST,
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SD_CD_DATA3 => SD_CD_DATA3,
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SD_CDM_D1 => SD_CDM_D1,
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ACP_CONF => ACP_CONF(31 DOWNTO 24),
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ACSI_D => ACSI_D,
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FB_AD => FB_AD,
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FB_ADR => FB_ADR,
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LP_D => LP_D,
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SCSI_D => SCSI_D,
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nIDE_CS1 => nIDE_CS1,
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nIDE_CS0 => nIDE_CS0,
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LP_STR => LP_STR,
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LP_DIR => LP_DIR,
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nACSI_ACK => nACSI_ACK,
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nACSI_RESET => nACSI_RESET,
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nACSI_CS => nACSI_CS,
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ACSI_DIR => ACSI_DIR,
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ACSI_A1 => ACSI_A1,
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nSCSI_ACK => nSCSI_ACK,
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nSCSI_ATN => nSCSI_ATN,
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SCSI_DIR => SCSI_DIR,
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SD_CLK => SD_CLK,
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YM_QA => YM_QA,
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YM_QC => YM_QC,
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YM_QB => YM_QB,
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nSDSEL => nSDSEL,
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STEP => STEP,
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MOT_ON => MOT_ON,
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nRP_LDS => nRP_LDS,
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nRP_UDS => nRP_UDS,
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nROM4 => nROM4,
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nROM3 => nROM3,
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nCF_CS1 => nCF_CS1,
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nCF_CS0 => nCF_CS0,
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nIDE_RD => nIDE_RD_i,
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nIDE_WR => nIDE_WR_i,
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AMKB_TX => AMKB_TX,
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IDE_RES => IDE_RES,
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DTR => DTR,
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RTS => RTS,
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TxD => TxD,
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MIDI_OLR => MIDI_OLR,
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DSA_D => DSA_D,
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nMFP_INT => nMFP_INT,
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FALCON_IO_TA => FALCON_IO_TA,
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STEP_DIR => STEP_DIR,
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WR_DATA => WR_DATA,
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WR_GATE => WR_GATE,
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DMA_DRQ => DMA_DRQ,
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MIDI_TLR => MIDI_TLR
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);
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i_interrupt_handler : work.interrupt_handler
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PORT MAP
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(
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MAIN_CLK => MAIN_CLK,
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nFB_WR => nFB_WR,
|
|
nFB_CS1 => nFB_CS1,
|
|
nFB_CS2 => nFB_CS2,
|
|
FB_SIZE0 => FB_SIZE0,
|
|
FB_SIZE1 => FB_SIZE1,
|
|
PIC_INT => PIC_INT,
|
|
E0_INT => E0_INT,
|
|
DVI_INT => DVI_INT,
|
|
nPCI_INTA => nPCI_INTA,
|
|
nPCI_INTB => nPCI_INTB,
|
|
nPCI_INTC => nPCI_INTC,
|
|
nPCI_INTD => nPCI_INTD,
|
|
nMFP_INT => nMFP_INT,
|
|
nFB_OE => nFB_OE,
|
|
DSP_INT => DSP_INT,
|
|
VSYNC => VSYNC,
|
|
HSYNC => HSYNC,
|
|
DMA_DRQ => DMA_DRQ,
|
|
nRSTO => nRSTO,
|
|
FB_AD => FB_AD,
|
|
FB_ADR => FB_ADR,
|
|
INT_HANDLER_TA => INT_HANDLER_TA,
|
|
TIN0 => TIN0,
|
|
ACP_CONF => ACP_CONF,
|
|
nIRQ => nIRQ
|
|
);
|
|
|
|
|
|
i_mfp_acia_clk_pll : work.altpll1
|
|
PORT MAP
|
|
(
|
|
inclk0 => MAIN_CLK,
|
|
c0 => CLK48M,
|
|
c1 => FDC_CLK,
|
|
c2 => CLK24M576,
|
|
locked => pll1_locked
|
|
);
|
|
|
|
|
|
i_pll_reconfig : altpll_reconfig1
|
|
PORT MAP
|
|
(
|
|
reconfig => VIDEO_RECONFIG,
|
|
read_param => VR_RD,
|
|
write_param => VR_WR,
|
|
pll_areset_in => '0',
|
|
pll_scandataout => scandataout,
|
|
pll_scandone => scandone,
|
|
clock => MAIN_CLK,
|
|
reset => reset,
|
|
counter_param => FB_ADR(8 DOWNTO 6),
|
|
counter_type => FB_ADR(5 DOWNTO 2),
|
|
data_in => FB_AD(24 DOWNTO 16),
|
|
busy => VR_BUSY,
|
|
pll_scandata => scandata,
|
|
pll_scanclk => scanclk,
|
|
pll_scanclkena => scan_clkena,
|
|
pll_configupdate => config_update,
|
|
pll_areset => pll_reset,
|
|
data_out => VR_D
|
|
);
|
|
|
|
|
|
i_video : video
|
|
PORT MAP
|
|
(
|
|
MAIN_CLK => MAIN_CLK,
|
|
nFB_CS1 => nFB_CS1,
|
|
nFB_CS2 => nFB_CS2,
|
|
nFB_CS3 => nFB_CS3,
|
|
nFB_WR => nFB_WR,
|
|
FB_SIZE0 => FB_SIZE0,
|
|
FB_SIZE1 => FB_SIZE1,
|
|
nRSTO => nRSTO,
|
|
nFB_OE => nFB_OE,
|
|
FB_ALE => FB_ALE,
|
|
DDR_SYNC_66M => DDR_SYNC_66M,
|
|
CLK33M => CLK33M,
|
|
CLK25M => clk25m_i,
|
|
CLK_VIDEO => CLK_VIDEO,
|
|
VR_BUSY => VR_BUSY,
|
|
DDRCLK => DDRCLK,
|
|
FB_AD => FB_AD,
|
|
FB_ADR => FB_ADR,
|
|
VD => VD,
|
|
VDQS => VDQS,
|
|
VR_D => VR_D,
|
|
VR_RD => VR_RD,
|
|
nBLANK => nBLANK,
|
|
nVWE => nVWE,
|
|
nVCAS => nVCAS,
|
|
nVRAS => nVRAS,
|
|
nVCS => nVCS,
|
|
nPD_VGA => nPD_VGA,
|
|
VCKE => VCKE,
|
|
VSYNC => VSYNC,
|
|
HSYNC => HSYNC,
|
|
nSYNC => nSYNC,
|
|
VIDEO_TA => Video_TA,
|
|
PIXEL_CLK => PIXEL_CLK,
|
|
VIDEO_RECONFIG => VIDEO_RECONFIG,
|
|
VR_WR => VR_WR,
|
|
BA => BA,
|
|
VA => VA,
|
|
VB => VB,
|
|
VDM => VDM,
|
|
VG => VG,
|
|
VR => VR
|
|
);
|
|
|
|
|
|
i_video_clk_pll : altpll4
|
|
PORT MAP
|
|
(
|
|
inclk0 => CLK48M,
|
|
areset => pll_reset,
|
|
scanclk => scanclk,
|
|
scandata => scandata,
|
|
scanclkena => scan_clkena,
|
|
configupdate => config_update,
|
|
c0 => CLK_VIDEO,
|
|
scandataout => scandataout,
|
|
scandone => scandone
|
|
);
|
|
|
|
|
|
inst1 : work.lpm_ff0
|
|
PORT MAP
|
|
(
|
|
clock => DDR_SYNC_66M,
|
|
enable => FB_ALE,
|
|
data => FB_AD,
|
|
q => FB_ADR
|
|
);
|
|
|
|
nMOT_ON <= NOT(MOT_ON);
|
|
nSTEP_DIR <= NOT(STEP_DIR);
|
|
nSTEP <= NOT(STEP);
|
|
nWR <= NOT(WR_DATA);
|
|
|
|
inst18 : work.lpm_counter0
|
|
PORT MAP
|
|
(
|
|
clock => CLK500k,
|
|
q => TIMEBASE
|
|
);
|
|
|
|
|
|
nWR_GATE <= NOT(WR_GATE);
|
|
|
|
nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA);
|
|
|
|
CLK33M <= MAIN_CLK;
|
|
|
|
reset <= NOT(nRSTO);
|
|
nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF;
|
|
|
|
inst29 : alt_iobuf
|
|
PORT MAP
|
|
(
|
|
i => CLK2M,
|
|
oe => CLK2M,
|
|
io => MIDI_IN_PIN,
|
|
o => MIDI_IN
|
|
);
|
|
|
|
LED_FPGA_OK <= TIMEBASE(17);
|
|
|
|
nDDR_CLK <= NOT(DDRCLK(0));
|
|
|
|
inst5 : work.altddio_out3
|
|
PORT MAP
|
|
(
|
|
datain_h => VSYNC,
|
|
datain_l => VSYNC,
|
|
outclock => PIXEL_CLK,
|
|
dataout => VSYNC_PAD
|
|
);
|
|
|
|
|
|
inst6 : work.altddio_out3
|
|
PORT MAP
|
|
(
|
|
datain_h => HSYNC,
|
|
datain_l => HSYNC,
|
|
outclock => PIXEL_CLK,
|
|
dataout => HSYNC_PAD
|
|
);
|
|
|
|
|
|
inst8 : work.altddio_out3
|
|
PORT MAP
|
|
(
|
|
datain_h => nBLANK,
|
|
datain_l => nBLANK,
|
|
outclock => PIXEL_CLK,
|
|
dataout => nBLANK_PAD
|
|
);
|
|
|
|
inst9 : work.altddio_out3
|
|
PORT MAP
|
|
(
|
|
datain_h => '0',
|
|
datain_l => '1',
|
|
outclock => PIXEL_CLK,
|
|
dataout => PIXEL_CLK_PAD
|
|
);
|
|
|
|
SD_CMD_D1 <= SD_CDM_D1;
|
|
DDR_CLK <= DDRCLK(0);
|
|
LPDIR <= LP_DIR;
|
|
CLK25M <= clk25m_i;
|
|
CLKUSB <= CLK48M;
|
|
nSRCS <= nSRCS_i;
|
|
|
|
nIDE_RD <= nIDE_RD_i;
|
|
nIDE_WR <= nIDE_WR_i;
|
|
END rtl; |