440 lines
8.7 KiB
ArmAsm
440 lines
8.7 KiB
ArmAsm
/********************************************************************/
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// sd card
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/********************************************************************/
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#define dspi_dtar0 0x0c
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#define dspi_dsr 0x2c
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#define dspi_dtfr 0x34
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#define dspi_drfr 0x38
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#define LONGASC(a, b, c, d) ((a << 24) | (b << 16) | (c << 8) | (d))
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#define MCF_PAD_PAR_DSPI (__MBAR+0xA50)
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#define MCF_PSC0_PSCTB_8BIT (__MBAR+0x860C)
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#define MCF_DSPI_DMCR (__MBAR+0x8A00)
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#define MCF_SLT0_SCNT (__MBAR + 0x908)
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.text
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warte_10ms:
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move.l d0,-(sp)
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move.l MCF_SLT0_SCNT,d0
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sub.l #1320000,d0
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warte_d6:
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cmp.l MCF_SLT0_SCNT,d0
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bcs warte_d6
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move.l (sp)+,d0
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rts
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warte_1ms:
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move.l d0,-(sp)
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move.l MCF_SLT0_SCNT,d0
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sub.l #132000,d0
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warte_d5:
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cmp.l MCF_SLT0_SCNT,d0
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bcs warte_d5
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move.l (sp)+,d0
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rts
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.global sd_idle
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.global sd_init
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sd_init:
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lea MCF_PSC0_PSCTB_8BIT,a6
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move.l #LONGASC('S', 'D', '-', 'C'),(a6)
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move.l #LONGASC('a', 'r', 'd', ' '),(a6)
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move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!)
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move.l #0x1fffffff,d0 // normal dspi
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move.l d0,MCF_PAD_PAR_DSPI
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lea MCF_DSPI_DMCR,a0
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move.l #0x800d3c00,(a0) // 8 bit cs5 on
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move.l #0x38558897,d0
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move.l d0,dspi_dtar0(a0) // 400kHz
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move.l #0x082000ff,d4 // tx vorbesetzen
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mov3q.l #-1,dspi_dsr(a0)
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bsr.l warte_1ms
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move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off
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bsr.l warte_10ms
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move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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bsr sd_com
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move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
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clr.b d4
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bsr sd_com
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bsr sd_com
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move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
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move.b #0xff,d4
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bsr sd_com
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bsr sd_com
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move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
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bsr.l warte_10ms
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// sd idle
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move.l #100,d6 // 100 versuche
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move.l #10,d3 // 10 versuche
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sd_idle:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x40,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x95,d4
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bsr sd_com
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move.b #0xff,d4 // receive byt
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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bsr sd_com
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cmp.b #0x01,d5
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beq idle_end
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subq.l #1,d6
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beq sd_not
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bra sd_idle
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idle_end:
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// cdm 8
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read_ic:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x48,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x01,d4
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bsr sd_com
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move.b #0xaa,d4
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bsr sd_com
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move.b #0x87,d4
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bsr sd_com
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bsr sd_get_status
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cmp.b #5,d5
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beq sd_v1
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cmp.b #1,d5
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bne read_ic
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move.b #0xff,d4
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bsr sd_com
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move.b d5,d0
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bsr sd_com
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move.b d5,d1
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bsr sd_com
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move.b d5,d2
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bsr sd_com
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cmp.b #0xaa,d5
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bne sd_testd3
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move.l #LONGASC('S', 'D', 'H', 'C'),(a6)
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move.b #' ',(a6)
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sd_v1:
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// cdm 58
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read_ocr:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x7a,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x01,d4
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bsr sd_com
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bsr sd_get_status
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move.l #LONGASC('V', 'e', 'r', '1'),d6
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cmp.b #5,d5
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beq read_ocr
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cmp.b #1,d5
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bne read_ocr
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move.b #0xff,d4
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bsr sd_com
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move.b d5,d0
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bsr sd_com
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move.b d5,d1
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bsr sd_com
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move.b d5,d2
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bsr sd_com
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// acdm 41
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move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen
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wait_of_aktiv:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x77,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x95,d4
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bsr sd_com
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bsr sd_get_status
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cmp.b #0x05,d5
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beq wait_of_aktiv
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wait_of_aktiv2:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x69,d4
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bsr sd_com
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move.b #0x40,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x95,d4
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bsr sd_com
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bsr sd_get_status
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tst.b d5
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beq sd_init_ok
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cmp.b #0x05,d5
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beq wait_of_aktiv2
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subq.l #1,d6
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bne wait_of_aktiv
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sd_testd3:
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subq.l #1,d3
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bne sd_idle
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bra sd_error
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sd_init_ok:
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// cdm 10
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read_cid:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x4a,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x95,d4
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bsr sd_com
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move.l a5,a4 // adresse setzen
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bsr sd_rcv_info
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// name ausgeben
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lea 1(a5),a4
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moveq #7,d7
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sd_nam_loop:
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move.b (a4)+,(a6)
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subq.l #1,d7
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bne sd_nam_loop
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move.b #' ',(a6)
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// cdm 9
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read_csd:
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move.b #0xff,d4 // receive byt
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bsr sd_com
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move.b #0x49,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x00,d4
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bsr sd_com
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move.b #0x01,d4
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bsr sd_com
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move.l a5,a4 // adresse setzen
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bsr sd_rcv_info
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mvz.b (a5),d0
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lsr.l #6,d0
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bne sd_csd2 // format v2
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move.l 6(a5),d1
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moveq #14,d0 // bit 73..62 c_size
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lsr.l d0,d1 // bits extrahieren
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and.l #0xfff,d1 // 12 bits
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addq.l #1,d1
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mvz.w 9(a5),d0
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lsr.l #7,d0 // bits 49..47
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and.l #0x7,d0 // 3 bits
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moveq.l #8,d2 // x256 (dif v1 v2)
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sub.l d0,d2
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lsr.l d2,d1
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bra sd_print_size
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sd_csd2:
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mvz.w 8(a5),d1
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addq.l #1,d1
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sd_print_size:
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swap d1
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lsl.l #1,d1
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bcc sd_16G
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move.l #LONGASC('3', '2', 'G', 'B'),(a6)
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bra sd_ok
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sd_16G:
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lsl.l #1,d1
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bcc sd_8G
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move.l #LONGASC('1', '6', 'G', 'B'),(a6)
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bra sd_ok
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sd_8G:
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lsl.l #1,d1
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bcc sd_4G
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move.l #LONGASC(' ', '4', 'G', 'B'),(a6)
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bra sd_ok
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sd_4G:
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lsl.l #1,d1
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bcc sd_2G
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move.l #LONGASC(' ', '4', 'G', 'B'),(a6)
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bra sd_ok
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sd_2G:
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lsl.l #1,d1
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bcc sd_1G
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move.l #LONGASC(' ', '2', 'G', 'B'),(a6)
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bra sd_ok
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sd_1G:
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lsl.l #1,d1
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bcc sd_512M
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move.l #LONGASC(' ', '1', 'G', 'B'),(a6)
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bra sd_ok
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sd_512M:
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lsl.l #1,d1
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bcc sd_256M
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move.b #'5',(a6)
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move.l #LONGASC('1', '2', 'M', 'B'),(a6)
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bra sd_ok
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sd_256M:
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lsl.l #1,d1
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bcc sd_128M
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move.b #'2',(a6)
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move.l #LONGASC('5', '6', 'M', 'B'),(a6)
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bra sd_ok
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sd_128M:
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lsl.l #1,d1
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bcc sd_64M
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move.b #'1',(a6)
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move.l #LONGASC('2', '8', 'M', 'B'),(a6)
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bra sd_ok
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sd_64M:
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lsl.l #1,d1
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bcc sd_32M
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move.l #LONGASC('6', '4', 'M', 'B'),(a6)
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bra sd_ok
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sd_32M:
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lsl.l #1,d1
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bcc sd_16M
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move.l #LONGASC('3', '2', 'M', 'B'),(a6)
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bra sd_ok
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sd_16M:
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lsl.l #1,d1
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bcc sd_8M
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move.l #LONGASC('1', '6', 'M', 'B'),(a6)
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bra sd_ok
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sd_8M:
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move.l #LONGASC('<', '9', 'M', 'B'),(a6)
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sd_ok:
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move.l #LONGASC(' ', 'O', 'K', '!'),(a6)
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move.l #0x0a0d,(a6)
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halt
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halt
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rts
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// subs ende -------------------------------
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sd_V1:
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move.l #LONGASC('n', 'o', 'n', '!'),(a6)
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move.l #0x0a0d,(a6)
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halt
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halt
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rts
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sd_error:
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move.l #LONGASC('E', 'r', 'r', 'o'),(a0)
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move.l #LONGASC('r', '!', '', ''), (a0)
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move.l #0x0a0d,(a6)
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halt
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halt
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rts
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sd_not:
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move.l #LONGASC('n', 'o', 'n', '!'),(a0)
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move.l #0x0a0d,(a6)
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halt
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halt
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rts
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// status holen -------------------------------
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sd_get_status:
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move.b #0xff,d4
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bsr sd_com
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cmp.b #0xff,d5
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beq sd_get_status
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rts
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// byt senden und holen ---------------------
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sd_com:
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move.l d4,dspi_dtfr(a0)
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wait_auf_complett:
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btst.b #7,dspi_dsr(a0)
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beq wait_auf_complett
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move.l dspi_drfr(a0),d5
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mov3q.l #-1,dspi_dsr(a0) // clr status register
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rts
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// daten holen ----------------------------
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sd_rcv_info:
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moveq #18,d3 // 16 byts + 2 byts crc
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move.b #0xff,d4
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sd_rcv_rb_w:
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bsr sd_get_status
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cmp.b #0xfe,d5 // daten bereit?
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bne sd_rcv_rb_w // nein->
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sd_rcv_rd_rb:
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bsr sd_com
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move.b d5,(a4)+
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subq.l #1,d3
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bne sd_rcv_rd_rb
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rts
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/******************************************/
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.data
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buffer: dc.l 0, 0, 0, 0, 0, 0, 0, 0
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