144 lines
4.0 KiB
Plaintext
144 lines
4.0 KiB
Plaintext
MEMORY
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{
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bas_rom (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
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bas_ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */
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}
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SECTIONS
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{
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/* BaS in ROM */
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.text :
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{
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objs/startcf.o(.text) /* this one is the entry point so it must be the first */
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objs/sysinit.o(.text)
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objs/init_fpga.o(.text)
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objs/wait.o(.text)
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#if (FORMAT == elf32-m68k)
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*(.rodata)
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*(.rodata.*)
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#endif
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} > bas_rom
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/* BaS in RAM */
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.bas :
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/* The BaS is stored in the flash, just after the init part.
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* Then it will be copied to its final location in the RAM.
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* This data must be aligned for optimal copy loop speed.
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*/
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AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
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{
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objs/BaS.o(.text)
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objs/wait.o(.text)
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/* put other routines into the same segment (RAM) as BaS.o */
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objs/unicode.o(.text)
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objs/mmc.o(.text)
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objs/ff.o(.text)
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objs/sd_card.o(.text)
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objs/s19reader.o(.text)
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objs/bas_printf.o(.text)
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objs/bas_string.o(.text)
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objs/printf_helper.o(.text)
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objs/cache.o(.text)
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objs/mmu.o(.text)
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objs/exceptions.o(.text)
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objs/supervisor.o(.text)
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objs/illegal_instruction.o(.text)
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*(.data)
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*(.bss)
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/* The BaS copy routine assumes that tha BaS size
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* is a multiple of the following value.
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*/
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. = ALIGN(16);
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} > bas_ram
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/* The following labels are BaS routines in the flash,
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* before they are copied to their final location in the RAM.
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* This is to allow using them before and after the actual copy.
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* Hence they must contain only pc-relative code (compiled with -mpcrel).
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*/
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#define BAS_LABEL_LMA(x) ((x) + (__BAS_LMA - __BAS_IN_RAM))
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_xprintf_before_copy = BAS_LABEL_LMA(_xprintf);
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_display_progress_before_copy = BAS_LABEL_LMA(_display_progress);
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_flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches);
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/*
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* Global memory map
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*/
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/* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */
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___SDRAM = 0x00000000;
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___SDRAM_SIZE = 0x20000000;
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/* ST-RAM */
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__STRAM = ___SDRAM;
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__STRAM_END = __TOS;
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/* TOS */
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__TOS = 0x00e00000;
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/* FastRAM */
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__FASTRAM = 0x10000000;
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__FASTRAM_END = __BAS_IN_RAM;
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/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
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___BOOT_FLASH = 0xe0000000;
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___BOOT_FLASH_SIZE = 0x00800000;
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/* BaS */
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__BAS_LMA = LOADADDR(.bas);
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__BAS_IN_RAM = ADDR(.bas);
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__BAS_SIZE = SIZEOF(.bas);
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/* Other flash components */
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__FIRETOS = 0xe0400000;
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__EMUTOS = 0xe0600000;
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__EMUTOS_SIZE = 0x00100000;
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/* VIDEO RAM BASIS */
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__VRAM = 0x60000000;
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/* Memory mapped registers */
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__MBAR = 0xFF000000;
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/* 32KB on-chip System SRAM */
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__SYS_SRAM = 0xFF010000;
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__SYS_SRAM_SIZE = 0x00008000;
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/* MMU memory mapped registers */
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__MMUBAR = 0xFF040000;
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/*
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* 4KB on-chip Core SRAM0: -> exception table and exception stack
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*/
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__RAMBAR0 = 0xFF100000;
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__RAMBAR0_SIZE = 0x00001000;
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__SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4;
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/* system variables */
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/* RAMBAR0 0 to 0x7FF -> exception vectors */
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_rt_mod = __RAMBAR0 + 0x800;
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_rt_ssp = __RAMBAR0 + 0x804;
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_rt_usp = __RAMBAR0 + 0x808;
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_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
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_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
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_rt_asid = __RAMBAR0 + 0x814; /* 003 */
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_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
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_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
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_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
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_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
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_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
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_rt_sr = __RAMBAR0 + 0x82c;
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_d0_save = __RAMBAR0 + 0x830;
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_a7_save = __RAMBAR0 + 0x834;
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_video_tlb = __RAMBAR0 + 0x838;
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_video_sbt = __RAMBAR0 + 0x83C;
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_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
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/* 4KB on-chip Core SRAM1: -> modified code */
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__RAMBAR1 = 0xFF101000;
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__RAMBAR1_SIZE = 0x00001000;
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}
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