115 lines
4.9 KiB
Tcl
Executable File
115 lines
4.9 KiB
Tcl
Executable File
## Generated SDC file "firebee.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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## DATE "Fri Aug 8 11:08:03 2014"
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##
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## DEVICE "EP3C40F484C6"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {CLK_MAIN} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK_MAIN}]
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create_clock -name {CLK_33M} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK_33M}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks -create_base_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {CLK_33M}] -to [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {CLK_33M}] -to [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLK_33M}]
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set_false_path -from [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLK_MAIN}]
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# decouple video clock from rest of design
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set_false_path -from [get_clocks] -to [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|*}]
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set_false_path -from [get_clocks {I_PLL4|altpll_component|auto_generated|pll1|*}] -to [get_clocks]
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# decouple ST clocks from rest of design
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set_false_path -from [get_clocks] -to [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|*}]
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set_false_path -from [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|*}] -to [get_clocks]
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# decouple CLK_MAIN and CLK_33M from DDR clocks
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set_false_path -from [get_clocks {CLK_*}] -to [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {I_PLL3|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {CLK_*}]
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set_false_path -from [get_clocks {I_PLL2|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks]
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set_false_path -from [get_clocks] -to [get_clocks {I_PLL2|altpll_component|auto_generated|pll1|clk[4]}]
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# decouple CLK_MAIN from CLK_33M
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set_false_path -from [get_clocks {CLK_MAIN}] -to [get_clocks {CLK_33M}]
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set_false_path -from [get_clocks {CLK_33M}] -to [get_clocks {CLK_MAIN}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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