d860191121
moved more interrupt handlers to generalized handler cleaned up lowlevel interrupt handling fixed wrong assignment of interrupt masks reformatted
149 lines
7.5 KiB
C
149 lines
7.5 KiB
C
/*
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* interrupts.h
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Created on: 08.08.2013
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* Author: Markus Fröschle
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*/
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#ifndef _INTERRUPTS_H_
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#define _INTERRUPTS_H_
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#include <stdbool.h>
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/* interrupt sources */
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#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
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#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
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#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
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#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
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#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
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#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
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#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
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#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
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#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
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#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
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#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
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#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
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#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
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#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
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#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
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#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
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#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
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#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
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#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
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#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
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#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
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#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
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#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
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#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
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#define INT_SOURCE_PSC3 32 // PSC3 interrupt
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#define INT_SOURCE_PSC2 33 // PSC2 interrupt
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#define INT_SOURCE_PSC1 34 // PSC1 interrupt
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#define INT_SOURCE_PSC0 35 // PSC0 interrupt
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#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
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#define INT_SOURCE_SEC 37 // SEC interrupt
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#define INT_SOURCE_FEC1 38 // FEC1 interrupt
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#define INT_SOURCE_FEC0 39 // FEC0 interrupt
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#define INT_SOURCE_I2C 40 // I2C interrupt
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#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
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#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
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#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
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#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
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#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
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#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
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#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
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#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
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#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
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#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
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#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
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#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
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#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
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#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
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#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
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#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */
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#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
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#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */
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#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */
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#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
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#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
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#define FEC0RX_DMA_PRI 5
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#define FEC1RX_DMA_PRI 4
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#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
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#define FEC0TX_DMA_PRI 2
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#define FEC1TX_DMA_PRI 1
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#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
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#if defined(MACHINE_FIREBEE)
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/* Firebee FPGA interrupt controller */
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#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000)
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#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004)
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#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008)
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#define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c)
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/* register bits for Firebee FPGA-based interrupt controller */
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#define FBEE_INTR_PIC (1 << 0) /* PIC interrupt enable/pending/clear bit */
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#define FBEE_INTR_ETHERNET (1 << 1) /* ethernet PHY interrupt enable/pending/clear bit */
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#define FBEE_INTR_DVI (1 << 2) /* TFP410 monitor sense interrupt enable/pending/clear bit */
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#define FBEE_INTR_PCI_INTA (1 << 3) /* /PCIINTA enable/pending clear bit */
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#define FBEE_INTR_PCI_INTB (1 << 4) /* /PCIINTB enable/pending clear bit */
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#define FBEE_INTR_PCI_INTC (1 << 5) /* /PCIINTC enable/pending clear bit */
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#define FBEE_INTR_PCI_INTD (1 << 6) /* /PCIINTD enable/pending clear bit */
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#define FBEE_INTR_DSP (1 << 7) /* DSP interrupt enable/pending/clear bit */
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#define FBEE_INTR_VSYNC (1 << 8) /* VSYNC interrupt enable/pending/clear bit */
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#define FBEE_INTR_HSYNC (1 << 9) /* HSYNC interrupt enable/pending/clear bit */
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#define FBEE_INTR_INT_HSYNC_IRQ2 (1 << 26) /* these bits are only meaningful for the FBEE_INTR_ENABLE register */
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#define FBEE_INTR_INT_CTR0_IRQ3 (1 << 27)
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#define FBEE_INTR_INT_VSYNC_IRQ4 (1 << 28)
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#define FBEE_INTR_INT_FPGA_IRQ5 (1 << 29)
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#define FBEE_INTR_INT_MFP_IRQ6 (1 << 30)
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#define FBEE_INTR_INT_IRQ7 (1 << 31)
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/*
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* Atari MFP interrupt registers.
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*/
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#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
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#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
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#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
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#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
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#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
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#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
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#endif /* MACHINE_FIREBEE */
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extern void isr_init(void);
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extern bool isr_set_prio_and_level(int int_source, int priority, int level);
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extern bool isr_enable_int_source(int int_source);
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extern bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg);
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extern void isr_remove_handler(bool (*handler)(void *, void *));
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extern bool isr_execute_handler(int vector);
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extern bool pic_interrupt_handler(void *arg1, void *arg2);
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extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
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extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
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extern bool irq5_handler(void *arg1, void *arg2);
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#endif /* _INTERRUPTS_H_ */
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