544 lines
26 KiB
C
544 lines
26 KiB
C
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.81
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF5475_GPIO_H__
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#define __MCF5475_GPIO_H__
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/*********************************************************************
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*
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* General Purpose I/O (GPIO)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
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#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
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#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
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#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
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#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
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#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
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#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
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#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
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#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
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#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
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#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
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#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
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#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
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#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
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#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
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#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
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#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
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#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
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#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
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#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
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#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
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#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
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#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
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#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
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#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
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#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
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#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
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#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
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#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
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#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
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#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
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#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
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#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
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#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
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#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
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#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
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#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
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#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
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#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
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#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
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#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
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#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
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#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
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#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
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#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
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#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
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#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
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#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
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#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
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#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
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#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
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#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
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/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
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#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
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#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
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#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
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#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
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#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
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#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
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#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
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#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
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#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
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/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
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#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
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#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
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#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
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#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
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#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
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#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
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#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
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#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
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#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
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#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
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#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
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#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
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#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
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#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
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#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
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/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
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#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
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#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
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#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
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#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
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/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
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#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
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#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
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#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
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#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
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#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
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#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
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#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
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#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
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/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
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#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
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#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
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#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
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#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
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/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
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#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
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#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
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#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
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#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
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#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
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#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
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#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
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#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
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#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
|
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
|
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#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
|
|
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
|
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
|
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
|
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
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#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
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|
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
|
|
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
|
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
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#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
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/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
|
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
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#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
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|
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/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
|
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#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
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|
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
|
|
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
|
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#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
|
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#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
|
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#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
|
|
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
|
|
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
|
|
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
|
|
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
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|
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/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
|
|
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
|
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|
|
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
|
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
|
|
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
|
|
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
|
|
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
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|
|
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
|
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
|
|
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
|
|
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
|
|
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
|
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
|
|
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
|
|
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
|
|
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
|
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
|
|
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
|
|
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
|
|
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
|
|
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
|
|
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
|
|
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
|
|
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
|
|
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
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|
|
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
|
|
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
|
|
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
|
|
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
|
|
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
|
|
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
|
|
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
|
|
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
|
|
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
|
|
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
|
|
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
|
|
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
|
|
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
|
|
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
|
|
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
|
|
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
|
|
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
|
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#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
|
|
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
|
|
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
|
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#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
|
|
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
|
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#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
|
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#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
|
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#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
|
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#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
|
|
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
|
|
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
|
|
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
|
|
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
|
|
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
|
|
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
|
|
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
|
|
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
|
|
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
|
|
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
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|
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/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
|
|
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
|
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#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
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|
|
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
|
|
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
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|
|
|
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
|
|
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
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|
|
|
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
|
|
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
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|
|
|
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
|
|
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
|
|
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
|
|
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
|
|
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
|
|
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
|
|
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
|
|
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
|
|
|
|
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
|
|
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
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#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
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#endif /* __MCF5475_GPIO_H__ */
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