172 lines
7.0 KiB
Verilog
172 lines
7.0 KiB
Verilog
// megafunction wizard: %LPM_MUX%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_MUX
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// ============================================================
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// File Name: lpm_muxVDM.v
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// Megafunction Name(s):
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// LPM_MUX
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_muxVDM (
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data0x,
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data10x,
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data11x,
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data12x,
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data13x,
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data14x,
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data15x,
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data1x,
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data2x,
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data3x,
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data4x,
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data5x,
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data6x,
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data7x,
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data8x,
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data9x,
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sel,
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result);
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input [127:0] data0x;
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input [127:0] data10x;
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input [127:0] data11x;
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input [127:0] data12x;
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input [127:0] data13x;
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input [127:0] data14x;
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input [127:0] data15x;
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input [127:0] data1x;
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input [127:0] data2x;
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input [127:0] data3x;
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input [127:0] data4x;
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input [127:0] data5x;
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input [127:0] data6x;
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input [127:0] data7x;
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input [127:0] data8x;
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input [127:0] data9x;
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input [3:0] sel;
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output [127:0] result;
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wire [127:0] sub_wire0;
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wire [127:0] sub_wire17 = data15x[127:0];
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wire [127:0] sub_wire16 = data14x[127:0];
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wire [127:0] sub_wire15 = data13x[127:0];
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wire [127:0] sub_wire14 = data12x[127:0];
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wire [127:0] sub_wire13 = data11x[127:0];
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wire [127:0] sub_wire12 = data10x[127:0];
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wire [127:0] sub_wire11 = data9x[127:0];
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wire [127:0] sub_wire10 = data8x[127:0];
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wire [127:0] sub_wire9 = data7x[127:0];
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wire [127:0] sub_wire8 = data6x[127:0];
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wire [127:0] sub_wire7 = data5x[127:0];
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wire [127:0] sub_wire6 = data4x[127:0];
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wire [127:0] sub_wire5 = data3x[127:0];
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wire [127:0] sub_wire4 = data2x[127:0];
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wire [127:0] sub_wire3 = data1x[127:0];
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wire [127:0] result = sub_wire0[127:0];
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wire [127:0] sub_wire1 = data0x[127:0];
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wire [2047:0] sub_wire2 = {sub_wire17, sub_wire16, sub_wire15, sub_wire14, sub_wire13, sub_wire12, sub_wire11, sub_wire10, sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3, sub_wire1};
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lpm_mux LPM_MUX_component (
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.data (sub_wire2),
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.sel (sel),
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.result (sub_wire0)
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// synopsys translate_off
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,
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.aclr (),
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.clken (),
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.clock ()
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// synopsys translate_on
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);
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defparam
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LPM_MUX_component.lpm_size = 16,
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LPM_MUX_component.lpm_type = "LPM_MUX",
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LPM_MUX_component.lpm_width = 128,
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LPM_MUX_component.lpm_widths = 4;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
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// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
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// Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
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// Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL "data10x[127..0]"
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// Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL "data11x[127..0]"
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// Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL "data12x[127..0]"
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// Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL "data13x[127..0]"
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// Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL "data14x[127..0]"
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// Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL "data15x[127..0]"
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// Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
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// Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL "data2x[127..0]"
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// Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL "data3x[127..0]"
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// Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL "data4x[127..0]"
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// Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL "data5x[127..0]"
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// Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL "data6x[127..0]"
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// Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL "data7x[127..0]"
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// Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL "data8x[127..0]"
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// Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL "data9x[127..0]"
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// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
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// Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
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// Retrieval info: CONNECT: @data 0 0 128 0 data0x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1280 data10x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1408 data11x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1536 data12x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1664 data13x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1792 data14x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1920 data15x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 128 data1x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 256 data2x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 384 data3x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 512 data4x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 640 data5x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 768 data6x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 896 data7x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1024 data8x 0 0 128 0
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// Retrieval info: CONNECT: @data 0 0 128 1152 data9x 0 0 128 0
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// Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
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// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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