1466 lines
65 KiB
Verilog
1466 lines
65 KiB
Verilog
// megafunction wizard: %ALTPLL_RECONFIG%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altpll_reconfig
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// ============================================================
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// File Name: altpll_reconfig1.v
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// Megafunction Name(s):
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// altpll_reconfig
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//
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// Simulation Library Files(s):
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// altera_mf;cycloneiii;lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
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//VERSION_BEGIN 13.1 cbx_altpll_reconfig 2013:10:23:18:05:48:SJ cbx_altsyncram 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_counter 2013:10:23:18:05:48:SJ cbx_lpm_decode 2013:10:23:18:05:48:SJ cbx_lpm_mux 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_stratixiii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
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module altpll_reconfig1_pllrcfg_t4q
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(
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busy,
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clock,
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counter_param,
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counter_type,
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data_in,
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data_out,
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pll_areset,
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pll_areset_in,
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pll_configupdate,
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pll_scanclk,
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pll_scanclkena,
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pll_scandata,
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pll_scandataout,
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pll_scandone,
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read_param,
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reconfig,
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reset,
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write_param) /* synthesis synthesis_clearbox=2 */;
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output busy;
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input clock;
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input [2:0] counter_param;
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input [3:0] counter_type;
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input [8:0] data_in;
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output [8:0] data_out;
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output pll_areset;
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input pll_areset_in;
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output pll_configupdate;
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output pll_scanclk;
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output pll_scanclkena;
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output pll_scandata;
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input pll_scandataout;
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input pll_scandone;
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input read_param;
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input reconfig;
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input reset;
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input write_param;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [2:0] counter_param;
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tri0 [3:0] counter_type;
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tri0 [8:0] data_in;
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tri0 pll_areset_in;
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tri0 pll_scandataout;
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tri0 pll_scandone;
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tri0 read_param;
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tri0 reconfig;
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tri0 write_param;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [0:0] wire_altsyncram4_q_a;
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wire wire_le_comb10_combout;
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wire wire_le_comb8_combout;
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wire wire_le_comb9_combout;
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reg areset_init_state_1;
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reg areset_state;
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reg C0_data_state;
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reg C0_ena_state;
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reg C1_data_state;
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reg C1_ena_state;
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reg C2_data_state;
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reg C2_ena_state;
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reg C3_data_state;
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reg C3_ena_state;
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reg C4_data_state;
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reg C4_ena_state;
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reg configupdate2_state;
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reg configupdate3_state;
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reg configupdate_state;
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reg [2:0] counter_param_latch_reg;
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reg [3:0] counter_type_latch_reg;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg idle_state;
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reg [0:0] nominal_data0;
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reg [0:0] nominal_data1;
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reg [0:0] nominal_data2;
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reg [0:0] nominal_data3;
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reg [0:0] nominal_data4;
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reg [0:0] nominal_data5;
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reg [0:0] nominal_data6;
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reg [0:0] nominal_data7;
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reg [0:0] nominal_data8;
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reg [0:0] nominal_data9;
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reg [0:0] nominal_data10;
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reg [0:0] nominal_data11;
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reg [0:0] nominal_data12;
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reg [0:0] nominal_data13;
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reg [0:0] nominal_data14;
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reg [0:0] nominal_data15;
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reg [0:0] nominal_data16;
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reg [0:0] nominal_data17;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_data_nominal_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_data_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_first_nominal_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_first_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_init_nominal_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_init_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_last_nominal_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg read_last_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_counter_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_init_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_post_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_seq_data_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_seq_ena_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg reconfig_wait_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
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reg reset_state;
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reg [0:0] shift_reg0;
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reg [0:0] shift_reg1;
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reg [0:0] shift_reg2;
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reg [0:0] shift_reg3;
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reg [0:0] shift_reg4;
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reg [0:0] shift_reg5;
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reg [0:0] shift_reg6;
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reg [0:0] shift_reg7;
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reg [0:0] shift_reg8;
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reg [0:0] shift_reg9;
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reg [0:0] shift_reg10;
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reg [0:0] shift_reg11;
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reg [0:0] shift_reg12;
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reg [0:0] shift_reg13;
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reg [0:0] shift_reg14;
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reg [0:0] shift_reg15;
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reg [0:0] shift_reg16;
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reg [0:0] shift_reg17;
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wire [17:0] wire_shift_reg_ena;
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reg tmp_nominal_data_out_state;
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reg tmp_seq_ena_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg write_data_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg write_init_nominal_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg write_init_state;
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(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
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reg write_nominal_state;
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wire [8:0] wire_add_sub5_result;
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wire [7:0] wire_add_sub6_result;
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wire wire_cmpr7_aeb;
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wire [7:0] wire_cntr1_q;
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wire [7:0] wire_cntr12_q;
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wire [5:0] wire_cntr13_q;
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wire [4:0] wire_cntr14_q;
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wire [7:0] wire_cntr15_q;
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wire [7:0] wire_cntr2_q;
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wire [4:0] wire_cntr3_q;
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wire [4:0] wire_decode11_eq;
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wire addr_counter_enable;
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wire [7:0] addr_counter_out;
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wire addr_counter_sload;
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wire [7:0] addr_counter_sload_value;
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wire [7:0] addr_decoder_out;
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wire [7:0] c0_wire;
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wire [7:0] c1_wire;
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wire [7:0] c2_wire;
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wire [7:0] c3_wire;
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wire [7:0] c4_wire;
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wire [2:0] counter_param_latch;
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wire [3:0] counter_type_latch;
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wire [2:0] cuda_combout_wire;
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wire dummy_scandataout;
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wire [2:0] encode_out;
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wire input_latch_enable;
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wire power_up;
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wire read_addr_counter_enable;
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wire [7:0] read_addr_counter_out;
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wire read_addr_counter_sload;
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wire [7:0] read_addr_counter_sload_value;
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wire [7:0] read_addr_decoder_out;
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wire read_nominal_out;
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wire reconfig_addr_counter_enable;
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wire [7:0] reconfig_addr_counter_out;
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wire reconfig_addr_counter_sload;
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wire [7:0] reconfig_addr_counter_sload_value;
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wire reconfig_done;
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wire reconfig_post_done;
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wire reconfig_width_counter_done;
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wire reconfig_width_counter_enable;
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wire reconfig_width_counter_sload;
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wire [5:0] reconfig_width_counter_sload_value;
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wire rotate_addr_counter_enable;
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wire [7:0] rotate_addr_counter_out;
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wire rotate_addr_counter_sload;
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wire [7:0] rotate_addr_counter_sload_value;
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wire [4:0] rotate_decoder_wires;
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wire rotate_width_counter_done;
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wire rotate_width_counter_enable;
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wire rotate_width_counter_sload;
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wire [4:0] rotate_width_counter_sload_value;
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wire [7:0] scan_cache_address;
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wire scan_cache_in;
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wire scan_cache_out;
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wire scan_cache_write_enable;
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wire sel_param_bypass_LF_unused;
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wire sel_param_c;
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wire sel_param_high_i_postscale;
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wire sel_param_low_r;
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wire sel_param_nominal_count;
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wire sel_param_odd_CP_unused;
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wire sel_type_c0;
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wire sel_type_c1;
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wire sel_type_c2;
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wire sel_type_c3;
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wire sel_type_c4;
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wire sel_type_cplf;
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wire sel_type_m;
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wire sel_type_n;
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wire sel_type_vco;
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wire [7:0] seq_addr_wire;
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wire [5:0] seq_sload_value;
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wire shift_reg_clear;
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wire shift_reg_load_enable;
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wire shift_reg_load_nominal_enable;
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wire shift_reg_serial_in;
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wire shift_reg_serial_out;
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wire shift_reg_shift_enable;
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wire shift_reg_shift_nominal_enable;
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wire [7:0] shift_reg_width_select;
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wire w1565w;
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wire w1592w;
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wire w64w;
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wire width_counter_done;
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wire width_counter_enable;
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wire width_counter_sload;
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wire [4:0] width_counter_sload_value;
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wire [4:0] width_decoder_out;
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wire [7:0] width_decoder_select;
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wire write_from_rom;
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altsyncram altsyncram4
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(
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.address_a(scan_cache_address),
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.clock0(clock),
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.data_a({scan_cache_in}),
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.eccstatus(),
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.q_a(wire_altsyncram4_q_a),
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.q_b(),
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.wren_a(scan_cache_write_enable)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.aclr0(1'b0),
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.aclr1(1'b0),
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.address_b({1{1'b1}}),
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.addressstall_a(1'b0),
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.addressstall_b(1'b0),
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.byteena_a({1{1'b1}}),
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.byteena_b({1{1'b1}}),
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.clock1(1'b1),
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.clocken0(1'b1),
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.clocken1(1'b1),
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.clocken2(1'b1),
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.clocken3(1'b1),
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.data_b({1{1'b1}}),
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.rden_a(1'b1),
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.rden_b(1'b1),
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.wren_b(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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);
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defparam
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altsyncram4.numwords_a = 144,
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altsyncram4.operation_mode = "SINGLE_PORT",
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altsyncram4.width_a = 1,
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altsyncram4.width_byteena_a = 1,
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altsyncram4.widthad_a = 8,
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altsyncram4.intended_device_family = "Cyclone III",
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altsyncram4.lpm_type = "altsyncram";
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cycloneiii_lcell_comb le_comb10
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(
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.combout(wire_le_comb10_combout),
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.cout(),
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.dataa(encode_out[0]),
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.datab(encode_out[1]),
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.datac(encode_out[2]),
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.cin(1'b0),
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.datad(1'b0)
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);
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defparam
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le_comb10.dont_touch = "on",
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le_comb10.lut_mask = 16'hF0F0,
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le_comb10.sum_lutc_input = "datac",
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le_comb10.lpm_type = "cycloneiii_lcell_comb";
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cycloneiii_lcell_comb le_comb8
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(
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.combout(wire_le_comb8_combout),
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.cout(),
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.dataa(encode_out[0]),
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.datab(encode_out[1]),
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.datac(encode_out[2]),
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.cin(1'b0),
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.datad(1'b0)
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);
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defparam
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le_comb8.dont_touch = "on",
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le_comb8.lut_mask = 16'hAAAA,
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le_comb8.sum_lutc_input = "datac",
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le_comb8.lpm_type = "cycloneiii_lcell_comb";
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cycloneiii_lcell_comb le_comb9
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(
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.combout(wire_le_comb9_combout),
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.cout(),
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.dataa(encode_out[0]),
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.datab(encode_out[1]),
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.datac(encode_out[2]),
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.cin(1'b0),
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.datad(1'b0)
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);
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defparam
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le_comb9.dont_touch = "on",
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le_comb9.lut_mask = 16'hCCCC,
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le_comb9.sum_lutc_input = "datac",
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le_comb9.lpm_type = "cycloneiii_lcell_comb";
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// synopsys translate_off
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initial
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areset_init_state_1 = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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areset_init_state_1 <= pll_scandone;
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// synopsys translate_off
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initial
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areset_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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areset_state <= (areset_init_state_1 & (~ reset));
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// synopsys translate_off
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initial
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C0_data_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
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// synopsys translate_off
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initial
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C0_ena_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C0_ena_state <= (C1_data_state & rotate_width_counter_done);
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// synopsys translate_off
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initial
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C1_data_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
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// synopsys translate_off
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initial
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C1_ena_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C1_ena_state <= (C2_data_state & rotate_width_counter_done);
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// synopsys translate_off
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initial
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C2_data_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
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// synopsys translate_off
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initial
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C2_ena_state = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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C2_ena_state <= (C3_data_state & rotate_width_counter_done);
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// synopsys translate_off
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initial
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C3_data_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
C3_ena_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
C3_ena_state <= (C4_data_state & rotate_width_counter_done);
|
|
// synopsys translate_off
|
|
initial
|
|
C4_data_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
C4_ena_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
C4_ena_state <= reconfig_init_state;
|
|
// synopsys translate_off
|
|
initial
|
|
configupdate2_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
configupdate2_state <= configupdate_state;
|
|
// synopsys translate_off
|
|
initial
|
|
configupdate3_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( negedge clock)
|
|
configupdate3_state <= configupdate2_state;
|
|
// synopsys translate_off
|
|
initial
|
|
configupdate_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
configupdate_state <= reconfig_post_state;
|
|
// synopsys translate_off
|
|
initial
|
|
counter_param_latch_reg = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
|
|
else if (input_latch_enable == 1'b1) counter_param_latch_reg <= counter_param;
|
|
// synopsys translate_off
|
|
initial
|
|
counter_type_latch_reg = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
|
|
else if (input_latch_enable == 1'b1) counter_type_latch_reg <= counter_type;
|
|
// synopsys translate_off
|
|
initial
|
|
idle_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) idle_state <= 1'b0;
|
|
else idle_state <= ((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | reset_state);
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data0 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data0 <= 1'b0;
|
|
else nominal_data0 <= wire_add_sub6_result[0];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data1 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data1 <= 1'b0;
|
|
else nominal_data1 <= wire_add_sub6_result[1];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data2 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data2 <= 1'b0;
|
|
else nominal_data2 <= wire_add_sub6_result[2];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data3 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data3 <= 1'b0;
|
|
else nominal_data3 <= wire_add_sub6_result[3];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data4 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data4 <= 1'b0;
|
|
else nominal_data4 <= wire_add_sub6_result[4];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data5 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data5 <= 1'b0;
|
|
else nominal_data5 <= wire_add_sub6_result[5];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data6 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data6 <= 1'b0;
|
|
else nominal_data6 <= wire_add_sub6_result[6];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data7 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data7 <= 1'b0;
|
|
else nominal_data7 <= wire_add_sub6_result[7];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data8 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data8 <= 1'b0;
|
|
else nominal_data8 <= data_in[0];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data9 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data9 <= 1'b0;
|
|
else nominal_data9 <= data_in[1];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data10 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data10 <= 1'b0;
|
|
else nominal_data10 <= data_in[2];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data11 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data11 <= 1'b0;
|
|
else nominal_data11 <= data_in[3];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data12 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data12 <= 1'b0;
|
|
else nominal_data12 <= data_in[4];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data13 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data13 <= 1'b0;
|
|
else nominal_data13 <= data_in[5];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data14 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data14 <= 1'b0;
|
|
else nominal_data14 <= data_in[6];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data15 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data15 <= 1'b0;
|
|
else nominal_data15 <= data_in[7];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data16 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data16 <= 1'b0;
|
|
else nominal_data16 <= data_in[8];
|
|
// synopsys translate_off
|
|
initial
|
|
nominal_data17 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) nominal_data17 <= 1'b0;
|
|
else nominal_data17 <= wire_cmpr7_aeb;
|
|
// synopsys translate_off
|
|
initial
|
|
read_data_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_data_nominal_state <= 1'b0;
|
|
else read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
read_data_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_data_state <= 1'b0;
|
|
else read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
read_first_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_first_nominal_state <= 1'b0;
|
|
else read_first_nominal_state <= read_init_nominal_state;
|
|
// synopsys translate_off
|
|
initial
|
|
read_first_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_first_state <= 1'b0;
|
|
else read_first_state <= read_init_state;
|
|
// synopsys translate_off
|
|
initial
|
|
read_init_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_init_nominal_state <= 1'b0;
|
|
else read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
|
|
// synopsys translate_off
|
|
initial
|
|
read_init_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_init_state <= 1'b0;
|
|
else read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
|
|
// synopsys translate_off
|
|
initial
|
|
read_last_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_last_nominal_state <= 1'b0;
|
|
else read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
|
|
// synopsys translate_off
|
|
initial
|
|
read_last_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) read_last_state <= 1'b0;
|
|
else read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_counter_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_counter_state <= 1'b0;
|
|
else reconfig_counter_state <= ((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state);
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_init_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_init_state <= 1'b0;
|
|
else reconfig_init_state <= (idle_state & reconfig);
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_post_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_post_state <= 1'b0;
|
|
else reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_seq_data_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
|
|
else reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_seq_ena_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
|
|
else reconfig_seq_ena_state <= tmp_seq_ena_state;
|
|
// synopsys translate_off
|
|
initial
|
|
reconfig_wait_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reconfig_wait_state <= 1'b0;
|
|
else reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
reset_state = {1{1'b1}};
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) reset_state <= {1{1'b1}};
|
|
else reset_state <= power_up;
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg0 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg0 <= 1'b0;
|
|
else if (wire_shift_reg_ena[0:0] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
|
|
else shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg1 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg1 <= 1'b0;
|
|
else if (wire_shift_reg_ena[1:1] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
|
|
else shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg2 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg2 <= 1'b0;
|
|
else if (wire_shift_reg_ena[2:2] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
|
|
else shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg3 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg3 <= 1'b0;
|
|
else if (wire_shift_reg_ena[3:3] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
|
|
else shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg4 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg4 <= 1'b0;
|
|
else if (wire_shift_reg_ena[4:4] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
|
|
else shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg5 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg5 <= 1'b0;
|
|
else if (wire_shift_reg_ena[5:5] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
|
|
else shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg6 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg6 <= 1'b0;
|
|
else if (wire_shift_reg_ena[6:6] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
|
|
else shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg7 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg7 <= 1'b0;
|
|
else if (wire_shift_reg_ena[7:7] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
|
|
else shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg8 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg8 <= 1'b0;
|
|
else if (wire_shift_reg_ena[8:8] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
|
|
else shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg9 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg9 <= 1'b0;
|
|
else if (wire_shift_reg_ena[9:9] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
|
|
else shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg10 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg10 <= 1'b0;
|
|
else if (wire_shift_reg_ena[10:10] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
|
|
else shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg11 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg11 <= 1'b0;
|
|
else if (wire_shift_reg_ena[11:11] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
|
|
else shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg12 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg12 <= 1'b0;
|
|
else if (wire_shift_reg_ena[12:12] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
|
|
else shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg13 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg13 <= 1'b0;
|
|
else if (wire_shift_reg_ena[13:13] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
|
|
else shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg14 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg14 <= 1'b0;
|
|
else if (wire_shift_reg_ena[14:14] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
|
|
else shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg15 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg15 <= 1'b0;
|
|
else if (wire_shift_reg_ena[15:15] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
|
|
else shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg16 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg16 <= 1'b0;
|
|
else if (wire_shift_reg_ena[16:16] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
|
|
else shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
|
|
// synopsys translate_off
|
|
initial
|
|
shift_reg17 = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) shift_reg17 <= 1'b0;
|
|
else if (wire_shift_reg_ena[17:17] == 1'b1)
|
|
if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
|
|
else shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
|
|
assign
|
|
wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
|
|
// synopsys translate_off
|
|
initial
|
|
tmp_nominal_data_out_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
|
|
// synopsys translate_off
|
|
initial
|
|
tmp_seq_ena_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock)
|
|
tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
|
|
// synopsys translate_off
|
|
initial
|
|
write_data_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) write_data_state <= 1'b0;
|
|
else write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
|
|
// synopsys translate_off
|
|
initial
|
|
write_init_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) write_init_nominal_state <= 1'b0;
|
|
else write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
|
|
// synopsys translate_off
|
|
initial
|
|
write_init_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) write_init_state <= 1'b0;
|
|
else write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
|
|
// synopsys translate_off
|
|
initial
|
|
write_nominal_state = 0;
|
|
// synopsys translate_on
|
|
always @ ( posedge clock or posedge reset)
|
|
if (reset == 1'b1) write_nominal_state <= 1'b0;
|
|
else write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
|
|
lpm_add_sub add_sub5
|
|
(
|
|
.cin(1'b0),
|
|
.cout(),
|
|
.dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
|
|
.datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
|
|
.overflow(),
|
|
.result(wire_add_sub5_result)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.add_sub(1'b1),
|
|
.clken(1'b1),
|
|
.clock(1'b0)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
add_sub5.lpm_width = 9,
|
|
add_sub5.lpm_type = "lpm_add_sub";
|
|
lpm_add_sub add_sub6
|
|
(
|
|
.cin(data_in[0]),
|
|
.cout(),
|
|
.dataa({data_in[8:1]}),
|
|
.overflow(),
|
|
.result(wire_add_sub6_result)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.add_sub(1'b1),
|
|
.clken(1'b1),
|
|
.clock(1'b0),
|
|
.datab({8{1'b0}})
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
add_sub6.lpm_width = 8,
|
|
add_sub6.lpm_type = "lpm_add_sub";
|
|
lpm_compare cmpr7
|
|
(
|
|
.aeb(wire_cmpr7_aeb),
|
|
.agb(),
|
|
.ageb(),
|
|
.alb(),
|
|
.aleb(),
|
|
.aneb(),
|
|
.dataa({data_in[7:0]}),
|
|
.datab(8'b00000001)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.clken(1'b1),
|
|
.clock(1'b0)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cmpr7.lpm_width = 8,
|
|
cmpr7.lpm_type = "lpm_compare";
|
|
lpm_counter cntr1
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(addr_counter_enable),
|
|
.cout(),
|
|
.data(addr_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr1_q),
|
|
.sload(addr_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr1.lpm_direction = "DOWN",
|
|
cntr1.lpm_modulus = 144,
|
|
cntr1.lpm_port_updown = "PORT_UNUSED",
|
|
cntr1.lpm_width = 8,
|
|
cntr1.lpm_type = "lpm_counter";
|
|
lpm_counter cntr12
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(reconfig_addr_counter_enable),
|
|
.cout(),
|
|
.data(reconfig_addr_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr12_q),
|
|
.sload(reconfig_addr_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr12.lpm_direction = "DOWN",
|
|
cntr12.lpm_modulus = 144,
|
|
cntr12.lpm_port_updown = "PORT_UNUSED",
|
|
cntr12.lpm_width = 8,
|
|
cntr12.lpm_type = "lpm_counter";
|
|
lpm_counter cntr13
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(reconfig_width_counter_enable),
|
|
.cout(),
|
|
.data(reconfig_width_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr13_q),
|
|
.sload(reconfig_width_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr13.lpm_direction = "DOWN",
|
|
cntr13.lpm_port_updown = "PORT_UNUSED",
|
|
cntr13.lpm_width = 6,
|
|
cntr13.lpm_type = "lpm_counter";
|
|
lpm_counter cntr14
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(rotate_width_counter_enable),
|
|
.cout(),
|
|
.data(rotate_width_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr14_q),
|
|
.sload(rotate_width_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr14.lpm_direction = "DOWN",
|
|
cntr14.lpm_port_updown = "PORT_UNUSED",
|
|
cntr14.lpm_width = 5,
|
|
cntr14.lpm_type = "lpm_counter";
|
|
lpm_counter cntr15
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(rotate_addr_counter_enable),
|
|
.cout(),
|
|
.data(rotate_addr_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr15_q),
|
|
.sload(rotate_addr_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr15.lpm_direction = "DOWN",
|
|
cntr15.lpm_modulus = 144,
|
|
cntr15.lpm_port_updown = "PORT_UNUSED",
|
|
cntr15.lpm_width = 8,
|
|
cntr15.lpm_type = "lpm_counter";
|
|
lpm_counter cntr2
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(read_addr_counter_enable),
|
|
.cout(),
|
|
.data(read_addr_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr2_q),
|
|
.sload(read_addr_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr2.lpm_direction = "UP",
|
|
cntr2.lpm_port_updown = "PORT_UNUSED",
|
|
cntr2.lpm_width = 8,
|
|
cntr2.lpm_type = "lpm_counter";
|
|
lpm_counter cntr3
|
|
(
|
|
.clock(clock),
|
|
.cnt_en(width_counter_enable),
|
|
.cout(),
|
|
.data(width_counter_sload_value),
|
|
.eq(),
|
|
.q(wire_cntr3_q),
|
|
.sload(width_counter_sload)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.aload(1'b0),
|
|
.aset(1'b0),
|
|
.cin(1'b1),
|
|
.clk_en(1'b1),
|
|
.sclr(1'b0),
|
|
.sset(1'b0),
|
|
.updown(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
cntr3.lpm_direction = "DOWN",
|
|
cntr3.lpm_port_updown = "PORT_UNUSED",
|
|
cntr3.lpm_width = 5,
|
|
cntr3.lpm_type = "lpm_counter";
|
|
lpm_decode decode11
|
|
(
|
|
.data(cuda_combout_wire),
|
|
.eq(wire_decode11_eq)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_off
|
|
`endif
|
|
,
|
|
.aclr(1'b0),
|
|
.clken(1'b1),
|
|
.clock(1'b0),
|
|
.enable(1'b1)
|
|
`ifndef FORMAL_VERIFICATION
|
|
// synopsys translate_on
|
|
`endif
|
|
);
|
|
defparam
|
|
decode11.lpm_decodes = 5,
|
|
decode11.lpm_width = 3,
|
|
decode11.lpm_type = "lpm_decode";
|
|
assign
|
|
addr_counter_enable = (write_data_state | write_nominal_state),
|
|
addr_counter_out = wire_cntr1_q,
|
|
addr_counter_sload = (write_init_state | write_init_nominal_state),
|
|
addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
|
|
addr_decoder_out = ((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}, 1'b0, (sel_type_n & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), {3{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, {2{(sel_type_m & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}, 1'b0, (sel_type_m & sel_param_low_r), 1'b0, (sel_type_m & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}, 1'b0, (sel_type_m & sel_param_nominal_count), 1'b0, (sel_type_m & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
|
|
), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}),
|
|
busy = ((~ idle_state) | areset_state),
|
|
c0_wire = 8'b01000111,
|
|
c1_wire = 8'b01011001,
|
|
c2_wire = 8'b01101011,
|
|
c3_wire = 8'b01111101,
|
|
c4_wire = 8'b10001111,
|
|
counter_param_latch = counter_param_latch_reg,
|
|
counter_type_latch = counter_type_latch_reg,
|
|
cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
|
|
data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
|
|
dummy_scandataout = pll_scandataout,
|
|
encode_out = {C4_ena_state, (C2_ena_state | C3_ena_state), (C1_ena_state | C3_ena_state)},
|
|
input_latch_enable = (idle_state & (write_param | read_param)),
|
|
pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
|
|
pll_configupdate = (configupdate_state & (~ configupdate3_state)),
|
|
pll_scanclk = clock,
|
|
pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
|
|
pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
|
|
power_up = ((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)),
|
|
read_addr_counter_enable = (((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state),
|
|
read_addr_counter_out = wire_cntr2_q,
|
|
read_addr_counter_sload = (read_init_state | read_init_nominal_state),
|
|
read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
|
|
read_addr_decoder_out = ((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_n & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, (sel_type_m & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), 1'b0, {3{(sel_type_m & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
|
|
), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}),
|
|
read_nominal_out = tmp_nominal_data_out_state,
|
|
reconfig_addr_counter_enable = reconfig_seq_data_state,
|
|
reconfig_addr_counter_out = wire_cntr12_q,
|
|
reconfig_addr_counter_sload = reconfig_seq_ena_state,
|
|
reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
|
|
reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
|
|
reconfig_post_done = pll_scandone,
|
|
reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
|
|
reconfig_width_counter_enable = reconfig_seq_data_state,
|
|
reconfig_width_counter_sload = reconfig_seq_ena_state,
|
|
reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
|
|
rotate_addr_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
|
|
rotate_addr_counter_out = wire_cntr15_q,
|
|
rotate_addr_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
|
|
rotate_addr_counter_sload_value = (((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})),
|
|
rotate_decoder_wires = wire_decode11_eq,
|
|
rotate_width_counter_done = (((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])),
|
|
rotate_width_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
|
|
rotate_width_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
|
|
rotate_width_counter_sload_value = 5'b10010,
|
|
scan_cache_address = ((((addr_counter_out & {8{addr_counter_enable}}) | (read_addr_counter_out & {8{read_addr_counter_enable}})) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})),
|
|
scan_cache_in = shift_reg_serial_out,
|
|
scan_cache_out = wire_altsyncram4_q_a[0],
|
|
scan_cache_write_enable = (write_data_state | write_nominal_state),
|
|
sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
|
|
sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
|
|
sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
|
|
sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
|
|
sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
|
|
sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
|
|
sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
|
|
sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
|
|
sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
|
|
sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
|
|
sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
|
|
sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
|
|
sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
|
|
sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
|
|
sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
|
|
seq_addr_wire = 8'b00110101,
|
|
seq_sload_value = 6'b110110,
|
|
shift_reg_clear = (read_init_state | read_init_nominal_state),
|
|
shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
|
|
shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
|
|
shift_reg_serial_in = scan_cache_out,
|
|
shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
|
|
shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
|
|
shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
|
|
shift_reg_width_select = width_decoder_select,
|
|
w1565w = 1'b0,
|
|
w1592w = 1'b0,
|
|
w64w = 1'b0,
|
|
width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
|
|
width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
|
|
width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
|
|
width_counter_sload_value = width_decoder_out,
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|
width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
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width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) | (sel_type_n & sel_param_low_r)) | (sel_type_m & sel_param_high_i_postscale)) | (sel_type_m & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) | (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused))},
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write_from_rom = 1'b0;
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endmodule //altpll_reconfig1_pllrcfg_t4q
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module altpll_reconfig1 (
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clock,
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counter_param,
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counter_type,
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data_in,
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pll_areset_in,
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pll_scandataout,
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pll_scandone,
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read_param,
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reconfig,
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reset,
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write_param,
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busy,
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data_out,
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pll_areset,
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pll_configupdate,
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pll_scanclk,
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pll_scanclkena,
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pll_scandata)/* synthesis synthesis_clearbox = 2 */;
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input clock;
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input [2:0] counter_param;
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input [3:0] counter_type;
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input [8:0] data_in;
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input pll_areset_in;
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input pll_scandataout;
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input pll_scandone;
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input read_param;
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input reconfig;
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input reset;
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input write_param;
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output busy;
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output [8:0] data_out;
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output pll_areset;
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output pll_configupdate;
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output pll_scanclk;
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output pll_scanclkena;
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output pll_scandata;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 pll_areset_in;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire sub_wire0;
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wire [8:0] sub_wire1;
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wire sub_wire2;
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wire sub_wire3;
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wire sub_wire4;
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wire sub_wire5;
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wire sub_wire6;
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wire pll_configupdate = sub_wire0;
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wire [8:0] data_out = sub_wire1[8:0];
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wire pll_scanclk = sub_wire2;
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wire pll_scanclkena = sub_wire3;
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wire pll_scandata = sub_wire4;
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wire busy = sub_wire5;
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wire pll_areset = sub_wire6;
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altpll_reconfig1_pllrcfg_t4q altpll_reconfig1_pllrcfg_t4q_component (
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.counter_param (counter_param),
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.data_in (data_in),
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.counter_type (counter_type),
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.pll_areset_in (pll_areset_in),
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.reconfig (reconfig),
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.pll_scandataout (pll_scandataout),
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.pll_scandone (pll_scandone),
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.reset (reset),
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.write_param (write_param),
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.clock (clock),
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.read_param (read_param),
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.pll_configupdate (sub_wire0),
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.data_out (sub_wire1),
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.pll_scanclk (sub_wire2),
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.pll_scanclkena (sub_wire3),
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.pll_scandata (sub_wire4),
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.busy (sub_wire5),
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.pll_areset (sub_wire6))/* synthesis synthesis_clearbox=2
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clearbox_macroname = altpll_reconfig
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clearbox_defparam = "intended_device_family=Cyclone III;" */;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
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// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
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// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
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// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
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// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
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// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
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// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
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// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
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// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
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// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
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// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
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// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
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// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
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// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
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// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
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// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
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|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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|
// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
|
|
// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
|
|
// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
|
|
// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
|
|
// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
|
|
// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
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|
// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
|
|
// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
|
|
// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
|
|
// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
|
|
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
|
|
// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
|
|
// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
|
|
// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
|
|
// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
|
|
// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
|
|
// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.v TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.v FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_bb.v FALSE
|
|
// Retrieval info: LIB_FILE: altera_mf
|
|
// Retrieval info: LIB_FILE: cycloneiii
|
|
// Retrieval info: LIB_FILE: lpm
|