Files
FireBee_SVN/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.v
2014-03-07 21:03:00 +00:00

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481 B
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// Xilinx XPort Language Converter, Version 4.1 (110)
//
// AHDL Design Source: lpm_bustri_LONG.tdf
// Verilog Design Output: lpm_bustri_LONG.v
// Created 05-Mar-2014 12:37 AM
//
// Copyright (c) 2014, Xilinx, Inc. All Rights Reserved.
// Xilinx Inc makes no warranty, expressed or implied, with respect to
// the operation and/or functionality of the converted output files.
//
//
//
// *** this module FAILED during conversion
//Look at error messages.
//