113 lines
4.2 KiB
Verilog
113 lines
4.2 KiB
Verilog
// megafunction wizard: %LPM_SHIFTREG%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_SHIFTREG
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// ============================================================
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// File Name: lpm_shiftreg1.v
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// Megafunction Name(s):
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// LPM_SHIFTREG
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_shiftreg1 (
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clock,
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shiftin,
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q);
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input clock;
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input shiftin;
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output [1:0] q;
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wire [1:0] sub_wire0;
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wire [1:0] q = sub_wire0[1:0];
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lpm_shiftreg LPM_SHIFTREG_component (
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.clock (clock),
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.shiftin (shiftin),
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.q (sub_wire0)
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// synopsys translate_off
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,
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.aclr (),
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.aset (),
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.data (),
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.enable (),
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.load (),
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.sclr (),
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.shiftout (),
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.sset ()
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// synopsys translate_on
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);
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defparam
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LPM_SHIFTREG_component.lpm_direction = "LEFT",
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LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
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LPM_SHIFTREG_component.lpm_width = 2;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ACLR NUMERIC "0"
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// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
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// Retrieval info: PRIVATE: ASET NUMERIC "0"
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// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: LeftShift NUMERIC "1"
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// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
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// Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
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// Retrieval info: PRIVATE: SCLR NUMERIC "0"
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// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
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// Retrieval info: PRIVATE: SSET NUMERIC "0"
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// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
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// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
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// Retrieval info: PRIVATE: nBit NUMERIC "2"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
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// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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