109 lines
4.1 KiB
Verilog
109 lines
4.1 KiB
Verilog
// megafunction wizard: %LPM_COMPARE%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: LPM_COMPARE
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// ============================================================
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// File Name: lpm_compare1.v
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// Megafunction Name(s):
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// LPM_COMPARE
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_compare1 (
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dataa,
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datab,
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agb);
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input [10:0] dataa;
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input [10:0] datab;
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output agb;
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wire sub_wire0;
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wire agb = sub_wire0;
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lpm_compare LPM_COMPARE_component (
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.dataa (dataa),
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.datab (datab),
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.agb (sub_wire0),
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.aclr (1'b0),
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.aeb (),
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.ageb (),
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.alb (),
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.aleb (),
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.aneb (),
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.clken (1'b1),
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.clock (1'b0));
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defparam
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LPM_COMPARE_component.lpm_representation = "UNSIGNED",
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LPM_COMPARE_component.lpm_type = "LPM_COMPARE",
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LPM_COMPARE_component.lpm_width = 11;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AeqB NUMERIC "0"
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// Retrieval info: PRIVATE: AgeB NUMERIC "0"
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// Retrieval info: PRIVATE: AgtB NUMERIC "1"
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// Retrieval info: PRIVATE: AleB NUMERIC "0"
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// Retrieval info: PRIVATE: AltB NUMERIC "0"
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// Retrieval info: PRIVATE: AneB NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
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// Retrieval info: PRIVATE: Latency NUMERIC "0"
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// Retrieval info: PRIVATE: PortBValue NUMERIC "0"
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// Retrieval info: PRIVATE: Radix NUMERIC "10"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
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// Retrieval info: PRIVATE: aclr NUMERIC "0"
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// Retrieval info: PRIVATE: clken NUMERIC "0"
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// Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
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// Retrieval info: PRIVATE: nBit NUMERIC "11"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
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// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
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// Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL "dataa[10..0]"
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// Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL "datab[10..0]"
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// Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
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// Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
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// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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