178 lines
7.2 KiB
Verilog
178 lines
7.2 KiB
Verilog
// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: dcfifo_mixed_widths
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// ============================================================
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// File Name: dcfifo1.v
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// Megafunction Name(s):
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// dcfifo_mixed_widths
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module dcfifo1 (
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aclr,
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data,
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rdclk,
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rdreq,
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wrclk,
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wrreq,
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q,
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rdusedw);
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input aclr;
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input [31:0] data;
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input rdclk;
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input rdreq;
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input wrclk;
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input wrreq;
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output [7:0] q;
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output [9:0] rdusedw;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 aclr;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [9:0] sub_wire0;
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wire [7:0] sub_wire1;
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wire [9:0] rdusedw = sub_wire0[9:0];
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wire [7:0] q = sub_wire1[7:0];
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dcfifo_mixed_widths dcfifo_mixed_widths_component (
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.aclr (aclr),
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.data (data),
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.rdclk (rdclk),
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.rdreq (rdreq),
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.wrclk (wrclk),
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.wrreq (wrreq),
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.rdusedw (sub_wire0),
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.q (sub_wire1),
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.rdempty (),
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.rdfull (),
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.wrempty (),
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.wrfull (),
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.wrusedw ());
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defparam
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dcfifo_mixed_widths_component.intended_device_family = "Cyclone III",
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dcfifo_mixed_widths_component.lpm_numwords = 256,
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dcfifo_mixed_widths_component.lpm_showahead = "OFF",
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dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
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dcfifo_mixed_widths_component.lpm_width = 32,
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dcfifo_mixed_widths_component.lpm_widthu = 8,
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dcfifo_mixed_widths_component.lpm_widthu_r = 10,
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dcfifo_mixed_widths_component.lpm_width_r = 8,
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dcfifo_mixed_widths_component.overflow_checking = "ON",
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dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
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dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
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dcfifo_mixed_widths_component.underflow_checking = "ON",
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dcfifo_mixed_widths_component.use_eab = "ON",
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dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
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dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "4"
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// Retrieval info: PRIVATE: Depth NUMERIC "256"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "2"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
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// Retrieval info: PRIVATE: Width NUMERIC "32"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "8"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "0"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
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// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
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// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
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// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
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// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
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// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
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// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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