554 lines
22 KiB
VHDL
554 lines
22 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part OF the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides the video toplevel OF the 'Firebee'----
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---- computer. It is optimized FOR the OF an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion OF the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is IN compa- ----
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---- rision TO the first edition completely written IN VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms OF the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 OF the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed IN the hope that it will be ----
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---- ful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty OF MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License FOR more ----
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---- details. ----
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---- ----
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---- You should have received a copy OF the GNU General Public ----
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---- License along with this program; IF not, write TO the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release OF the second edition.
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-- ST colours enhanced TO 4 bit colour mode (STE compatibility).
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LIBRARY work;
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USE work.firebee_pkg.ALL;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY video_system IS
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PORT (
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clk_main : IN std_logic;
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clk_33m : IN std_logic;
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clk_25m : IN std_logic;
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clk_video : IN std_logic;
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clk_ddr3 : IN std_logic;
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clk_ddr2 : IN std_logic;
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clk_ddr0 : IN std_logic;
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clk_pixel : OUT std_logic;
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vr_d : IN std_logic_vector(8 DOWNTO 0);
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vr_busy : IN std_logic;
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fb_adr : IN std_logic_vector(31 DOWNTO 0);
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fb_ad_in : IN std_logic_vector(31 DOWNTO 0);
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fb_ad_out : OUT std_logic_vector(31 DOWNTO 0);
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fb_ad_en_31_16 : OUT std_logic; -- Hi word.
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fb_ad_en_15_0 : OUT std_logic; -- Low word.
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fb_ale : IN std_logic;
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fb_cs_n : IN std_logic_vector(3 DOWNTO 1);
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fb_oe_n : IN std_logic;
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fb_wr_n : IN std_logic;
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fb_size1 : IN std_logic;
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fb_size0 : IN std_logic;
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vdp_in : IN std_logic_vector(63 DOWNTO 0);
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vr_rd : OUT std_logic;
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vr_wr : OUT std_logic;
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video_reconfig : OUT std_logic;
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red : OUT std_logic_vector(7 DOWNTO 0);
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green : OUT std_logic_vector(7 DOWNTO 0);
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blue : OUT std_logic_vector(7 DOWNTO 0);
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vsync : OUT std_logic;
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hsync : OUT std_logic;
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sync_n : OUT std_logic;
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blank_n : OUT std_logic;
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pd_vga_n : OUT std_logic;
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video_mod_ta : OUT std_logic;
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vd_vz : OUT std_logic_vector(127 DOWNTO 0);
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sr_fifo_wre : IN std_logic;
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sr_vdmp : IN std_logic_vector(7 DOWNTO 0);
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fifo_mw : OUT unsigned (8 DOWNTO 0);
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vdm_sel : IN std_logic_vector(3 DOWNTO 0);
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video_ram_ctr : OUT std_logic_vector(15 DOWNTO 0);
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fifo_clr : OUT std_logic;
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vdm : OUT std_logic_vector(3 DOWNTO 0);
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blitter_run : IN std_logic;
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blitter_on : OUT std_logic
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);
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END ENTITY video_system;
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ARCHITECTURE BEHAVIOUR OF video_system is
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COMPONENT lpm_fifo_dc0
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PORT(
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aclr : IN std_logic := '0';
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data : IN std_logic_vector (127 DOWNTO 0);
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rdclk : IN std_logic ;
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rdreq : IN std_logic ;
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wrclk : IN std_logic ;
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wrreq : IN std_logic ;
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q : OUT std_logic_vector (127 DOWNTO 0);
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rdempty : OUT std_logic ;
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wrusedw : OUT std_logic_vector (8 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT lpm_fifoDZ is
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PORT(
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aclr : IN std_logic ;
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clock : IN std_logic ;
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data : IN std_logic_vector (127 DOWNTO 0);
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rdreq : IN std_logic ;
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wrreq : IN std_logic ;
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q : OUT std_logic_vector (127 DOWNTO 0)
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);
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END COMPONENT;
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TYPE clut_shiftreg_t IS ARRAY(0 TO 7) OF std_logic_vector(15 DOWNTO 0);
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TYPE clut_st_t IS ARRAY(0 TO 15) OF std_logic_vector(11 DOWNTO 0);
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TYPE clut_fa_t IS ARRAY(0 TO 255) OF std_logic_vector(17 DOWNTO 0);
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TYPE clut_fbee_t IS ARRAY(0 TO 255) OF std_logic_vector(23 DOWNTO 0);
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SIGNAL clut_fa : clut_fa_t;
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SIGNAL clut_fi : clut_fbee_t;
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SIGNAL clut_st : clut_st_t;
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SIGNAL clut_fa_r : std_logic_vector(5 DOWNTO 0);
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SIGNAL clut_fa_g : std_logic_vector(5 DOWNTO 0);
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SIGNAL clut_fa_b : std_logic_vector(5 DOWNTO 0);
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SIGNAL clut_fbee_r : std_logic_vector(7 DOWNTO 0);
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SIGNAL clut_fbee_g : std_logic_vector(7 DOWNTO 0);
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SIGNAL clut_fbee_b : std_logic_vector(7 DOWNTO 0);
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SIGNAL clut_st_r : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_st_g : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_st_b : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_fa_out : std_logic_vector(17 DOWNTO 0);
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SIGNAL clut_fbee_out : std_logic_vector(23 DOWNTO 0);
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SIGNAL clut_st_out : std_logic_vector(11 DOWNTO 0);
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SIGNAL clut_adr : std_logic_vector(7 DOWNTO 0);
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SIGNAL clut_adr_a : std_logic_vector(7 DOWNTO 0);
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SIGNAL clut_adr_mux : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_shift_in : std_logic_vector(5 DOWNTO 0);
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SIGNAL clut_shift_load : std_logic;
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SIGNAL clut_off : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_fbee_rd : std_logic;
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SIGNAL clut_fbee_wr : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_fa_rdh : std_logic;
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SIGNAL clut_fa_rdl : std_logic;
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SIGNAL clut_fa_wr : std_logic_vector(3 DOWNTO 0);
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SIGNAL clut_st_rd : std_logic;
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SIGNAL clut_st_wr : std_logic_vector(1 DOWNTO 0);
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SIGNAL data_out_video_ctrl : std_logic_vector(31 DOWNTO 0);
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SIGNAL data_en_h_video_ctrl : std_logic;
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SIGNAL data_en_l_video_ctrl : std_logic;
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SIGNAL COLOR1 : std_logic;
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SIGNAL color2 : std_logic;
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SIGNAL color4 : std_logic;
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SIGNAL color8 : std_logic;
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SIGNAL ccr : std_logic_vector(23 DOWNTO 0);
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SIGNAL CC_SEL : std_logic_vector(2 DOWNTO 0);
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SIGNAL fifo_clr_i : std_logic;
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SIGNAL dop_fifo_clr : std_logic;
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SIGNAL fifo_wre : std_logic;
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SIGNAL fifo_rd_req_128 : std_logic;
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SIGNAL fifo_rd_req_512 : std_logic;
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SIGNAL fifo_rde : std_logic;
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SIGNAL inter_zei : std_logic;
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SIGNAL fifo_d_out_128 : std_logic_vector(127 DOWNTO 0);
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SIGNAL fifo_d_out_512 : std_logic_vector(127 DOWNTO 0);
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SIGNAL FIFO_D_IN_512 : std_logic_vector(127 DOWNTO 0);
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SIGNAL fifo_d : std_logic_vector(127 DOWNTO 0);
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SIGNAL vd_vz_i : std_logic_vector(127 DOWNTO 0);
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SIGNAL vdm_a : std_logic_vector(127 DOWNTO 0);
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SIGNAL vdm_b : std_logic_vector(127 DOWNTO 0);
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SIGNAL vdm_c : std_logic_vector(127 DOWNTO 0);
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SIGNAL V_DMA_SEL : std_logic_vector(3 DOWNTO 0);
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SIGNAL vdmp : std_logic_vector(7 DOWNTO 0);
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SIGNAL vdmp_i : std_logic_vector(7 DOWNTO 0);
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SIGNAL cc_24 : std_logic_vector(31 DOWNTO 0);
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SIGNAL cc_16 : std_logic_vector(23 DOWNTO 0);
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SIGNAL clk_pixel_i : std_logic;
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SIGNAL VD_OUT_I : std_logic_vector(31 DOWNTO 0);
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SIGNAL zr_c8 : std_logic_vector(7 DOWNTO 0);
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BEGIN
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clk_pixel <= clk_pixel_i;
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fifo_clr <= fifo_clr_i;
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p_clut_st_mc : PROCESS
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-- This is the dual ported ram FOR the ST colour lookup tables
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VARIABLE clut_fa_index : INTEGER;
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VARIABLE clut_st_index : INTEGER;
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VARIABLE clut_fi_index : INTEGER;
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BEGIN
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clut_st_index := TO_INTEGER(unsigned(fb_adr(4 DOWNTO 1)));
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clut_fa_index := TO_INTEGER(unsigned(fb_adr(9 DOWNTO 2)));
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clut_fi_index := TO_INTEGER(unsigned(fb_adr(9 DOWNTO 2)));
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WAIT UNTIL rising_edge(clk_main);
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IF clut_st_wr(0) = '1' THEN
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clut_st(clut_st_index)(11 DOWNTO 8) <= fb_ad_in(27 DOWNTO 24);
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END IF;
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IF clut_st_wr(1) = '1' THEN
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clut_st(clut_st_index)(7 DOWNTO 0) <= fb_ad_in(23 DOWNTO 16);
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END IF;
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IF clut_fa_wr(0) = '1' THEN
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clut_fa(clut_fa_index)(17 DOWNTO 12) <= fb_ad_in(31 DOWNTO 26);
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END IF;
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IF clut_fa_wr(1) = '1' THEN
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clut_fa(clut_fa_index)(11 DOWNTO 6) <= fb_ad_in(23 DOWNTO 18);
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END IF;
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IF clut_fa_wr(3) = '1' THEN
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clut_fa(clut_fa_index)(5 DOWNTO 0) <= fb_ad_in(23 DOWNTO 18);
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END IF;
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IF clut_fbee_wr(1) = '1' THEN
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clut_fi(clut_fi_index)(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16);
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END IF;
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IF clut_fbee_wr(2) = '1' THEN
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clut_fi(clut_fi_index)(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8);
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END IF;
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IF clut_fbee_wr(3) = '1' THEN
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clut_fi(clut_fi_index)(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0);
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END IF;
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--
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clut_st_out <= clut_st(clut_st_index);
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clut_fa_out <= clut_fa(clut_fa_index);
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clut_fbee_out <= clut_fi(clut_fi_index);
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END PROCESS p_clut_st_mc;
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p_clut_st_px : PROCESS
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VARIABLE clut_fa_index : INTEGER;
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VARIABLE clut_st_index : INTEGER;
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VARIABLE clut_fi_index : INTEGER;
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-- This is the dual ported ram FOR the ST colour lookup tables.
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BEGIN
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clut_st_index := TO_INTEGER(unsigned(clut_adr(3 DOWNTO 0)));
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clut_fa_index := TO_INTEGER(unsigned(clut_adr));
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clut_fi_index := TO_INTEGER(unsigned(zr_c8));
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WAIT UNTIL clk_pixel_i = '1' and clk_pixel_i' event;
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clut_st_r <= clut_st(clut_st_index)(8) & clut_st(clut_st_index)(11 DOWNTO 9);
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clut_st_g <= clut_st(clut_st_index)(4) & clut_st(clut_st_index)(7 DOWNTO 5);
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clut_st_b <= clut_st(clut_st_index)(0) & clut_st(clut_st_index)(3 DOWNTO 1);
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clut_fa_r <= clut_fa(clut_fa_index)(17 DOWNTO 12);
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clut_fa_g <= clut_fa(clut_fa_index)(11 DOWNTO 6);
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clut_fa_b <= clut_fa(clut_fa_index)(5 DOWNTO 0);
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clut_fbee_r <= clut_fi(clut_fi_index)(23 DOWNTO 16);
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clut_fbee_g <= clut_fi(clut_fi_index)(15 DOWNTO 8);
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clut_fbee_b <= clut_fi(clut_fi_index)(7 DOWNTO 0);
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END PROCESS p_clut_st_px;
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p_video_out : PROCESS
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VARIABLE video_out : std_logic_vector(23 DOWNTO 0);
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BEGIN
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WAIT UNTIL rising_edge(clk_pixel_i);
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CASE CC_SEL is
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WHEN "111" => video_out := ccr; -- Register TYPE video.
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WHEN "110" => video_out := cc_24(23 DOWNTO 0); -- 3 byte FIFO TYPE video.
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WHEN "101" => video_out := cc_16; -- 2 byte FIFO TYPE video.
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WHEN "100" => video_out := clut_fbee_r & clut_fbee_g & clut_fbee_b; -- Firebee TYPE video.
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WHEN "001" => video_out := clut_fa_r & "00" & clut_fa_g & "00" & clut_fa_b & "00"; -- Falcon TYPE video.
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WHEN "000" => video_out := clut_st_r & x"0" & clut_st_g & x"0" & clut_st_b & x"0"; -- ST TYPE video.
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WHEN OTHERS => video_out := (OTHERS => '0');
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END CASE;
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red <= video_out(23 DOWNTO 16);
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green <= video_out(15 DOWNTO 8);
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blue <= video_out(7 DOWNTO 0);
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END PROCESS p_video_out;
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P_CC: PROCESS
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VARIABLE cc24_i : std_logic_vector(31 DOWNTO 0);
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VARIABLE cc_i : std_logic_vector(15 DOWNTO 0);
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VARIABLE zr_c8_i : std_logic_vector(7 DOWNTO 0);
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BEGIN
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WAIT UNTIL clk_pixel_i = '1' and clk_pixel_i' event;
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CASE clut_adr_mux(1 DOWNTO 0) is
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WHEN "11" => cc24_i := fifo_d(31 DOWNTO 0);
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WHEN "10" => cc24_i := fifo_d(63 DOWNTO 32);
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WHEN "01" => cc24_i := fifo_d(95 DOWNTO 64);
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WHEN "00" => cc24_i := fifo_d(127 DOWNTO 96);
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WHEN OTHERS => cc24_i := (OTHERS => 'Z');
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END CASE;
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--
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cc_24 <= cc24_i;
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--
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CASE clut_adr_mux(2 DOWNTO 0) is
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WHEN "111" => cc_i := fifo_d(15 DOWNTO 0);
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WHEN "110" => cc_i := fifo_d(31 DOWNTO 16);
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WHEN "101" => cc_i := fifo_d(47 DOWNTO 32);
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WHEN "100" => cc_i := fifo_d(63 DOWNTO 48);
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WHEN "011" => cc_i := fifo_d(79 DOWNTO 64);
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WHEN "010" => cc_i := fifo_d(95 DOWNTO 80);
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WHEN "001" => cc_i := fifo_d(111 DOWNTO 96);
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WHEN "000" => cc_i := fifo_d(127 DOWNTO 112);
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WHEN OTHERS => cc_i := (OTHERS => 'X');
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END CASE;
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--
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cc_16 <= cc_i(15 DOWNTO 11) & "000" & cc_i(10 DOWNTO 5) & "00" & cc_i(4 DOWNTO 0) & "000";
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--
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CASE clut_adr_mux(3 DOWNTO 0) is
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WHEN x"F" => zr_c8_i := fifo_d(7 DOWNTO 0);
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WHEN x"E" => zr_c8_i := fifo_d(15 DOWNTO 8);
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WHEN x"D" => zr_c8_i := fifo_d(23 DOWNTO 16);
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WHEN x"C" => zr_c8_i := fifo_d(31 DOWNTO 24);
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WHEN x"B" => zr_c8_i := fifo_d(39 DOWNTO 32);
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WHEN x"A" => zr_c8_i := fifo_d(47 DOWNTO 40);
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WHEN x"9" => zr_c8_i := fifo_d(55 DOWNTO 48);
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WHEN x"8" => zr_c8_i := fifo_d(63 DOWNTO 56);
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WHEN x"7" => zr_c8_i := fifo_d(71 DOWNTO 64);
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WHEN x"6" => zr_c8_i := fifo_d(79 DOWNTO 72);
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WHEN x"5" => zr_c8_i := fifo_d(87 DOWNTO 80);
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WHEN x"4" => zr_c8_i := fifo_d(95 DOWNTO 88);
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WHEN x"3" => zr_c8_i := fifo_d(103 DOWNTO 96);
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WHEN x"2" => zr_c8_i := fifo_d(111 DOWNTO 104);
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WHEN x"1" => zr_c8_i := fifo_d(119 DOWNTO 112);
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WHEN x"0" => zr_c8_i := fifo_d(127 DOWNTO 120);
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WHEN OTHERS => zr_c8_i := (OTHERS => 'X');
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END CASE;
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--
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CASE COLOR1 is
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WHEN '1' => zr_c8 <= zr_c8_i;
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WHEN OTHERS => zr_c8 <= "0000000" & zr_c8_i(0);
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END CASE;
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END PROCESS P_CC;
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clut_shift_in <= clut_adr_a(6 DOWNTO 1) WHEN color4 = '0' and color2 = '0' ELSE
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clut_adr_a(7 DOWNTO 2) WHEN color4 = '0' and color2 = '1' ELSE
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"00" & clut_adr_a(7 DOWNTO 4) WHEN color4 = '1' and color2 = '0' ELSE "000000";
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fifo_rd_req_128 <= '1' WHEN fifo_rde = '1' and inter_zei = '1' ELSE '0';
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fifo_rd_req_512 <= '1' WHEN fifo_rde = '1' and inter_zei = '0' ELSE '0';
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FIFO_DMUX: PROCESS
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BEGIN
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WAIT UNTIL rising_edge(clk_pixel_i);
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IF fifo_rde = '1' and inter_zei = '1' THEN
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fifo_d <= fifo_d_out_128;
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ELSIF fifo_rde = '1' THEN
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fifo_d <= fifo_d_out_512;
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END IF;
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END PROCESS FIFO_DMUX;
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CLUT_SHIFTREGS: PROCESS
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VARIABLE clut_shiftreg : clut_shiftreg_t;
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BEGIN
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WAIT UNTIL rising_edge(clk_pixel_i);
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clut_shift_load <= fifo_rde;
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IF clut_shift_load = '1' THEN
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FOR i IN 0 TO 7 LOOP
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clut_shiftreg(7 - i) := fifo_d((i + 1) * 16 - 1 DOWNTO i * 16);
|
|
END LOOP;
|
|
ELSE
|
|
clut_shiftreg(7) := clut_shiftreg(7)(14 DOWNTO 0) & clut_adr_a(0);
|
|
clut_shiftreg(6) := clut_shiftreg(6)(14 DOWNTO 0) & clut_adr_a(7);
|
|
clut_shiftreg(5) := clut_shiftreg(5)(14 DOWNTO 0) & clut_shift_in(5);
|
|
clut_shiftreg(4) := clut_shiftreg(4)(14 DOWNTO 0) & clut_shift_in(4);
|
|
clut_shiftreg(3) := clut_shiftreg(3)(14 DOWNTO 0) & clut_shift_in(3);
|
|
clut_shiftreg(2) := clut_shiftreg(2)(14 DOWNTO 0) & clut_shift_in(2);
|
|
clut_shiftreg(1) := clut_shiftreg(1)(14 DOWNTO 0) & clut_shift_in(1);
|
|
clut_shiftreg(0) := clut_shiftreg(0)(14 DOWNTO 0) & clut_shift_in(0);
|
|
END IF;
|
|
--
|
|
FOR i IN 0 TO 7 LOOP
|
|
clut_adr_a(i) <= clut_shiftreg(i)(15);
|
|
END LOOP;
|
|
END PROCESS CLUT_SHIFTREGS;
|
|
|
|
clut_adr(7) <= clut_off(3) or (clut_adr_a(7) and color8);
|
|
clut_adr(6) <= clut_off(2) or (clut_adr_a(6) and color8);
|
|
clut_adr(5) <= clut_off(1) or (clut_adr_a(5) and color8);
|
|
clut_adr(4) <= clut_off(0) or (clut_adr_a(4) and color8);
|
|
clut_adr(3) <= clut_adr_a(3) and (color8 or color4);
|
|
clut_adr(2) <= clut_adr_a(2) and (color8 or color4);
|
|
clut_adr(1) <= clut_adr_a(1) and (color8 or color4 or color2);
|
|
clut_adr(0) <= clut_adr_a(0);
|
|
|
|
fb_ad_out <= x"0" & clut_st_out & x"0000" WHEN clut_st_rd = '1' ELSE
|
|
clut_fa_out(17 DOWNTO 12) & "00" & clut_fa_out(11 DOWNTO 6) & "00" & x"0000" WHEN clut_fa_rdh = '1' ELSE
|
|
x"00" & clut_fa_out(5 DOWNTO 0) & "00" & x"0000" WHEN clut_fa_rdl = '1' ELSE
|
|
x"00" & clut_fbee_out WHEN clut_fbee_rd = '1' ELSE
|
|
data_out_video_ctrl WHEN data_en_h_video_ctrl = '1' ELSE -- Use upper word.
|
|
data_out_video_ctrl WHEN data_en_l_video_ctrl = '1' ELSE (OTHERS => '0'); -- Use lower word.
|
|
|
|
fb_ad_en_31_16 <= '1' WHEN clut_fbee_rd = '1' ELSE
|
|
'1' WHEN clut_fa_rdh = '1' ELSE
|
|
'1' WHEN data_en_h_video_ctrl = '1' ELSE '0';
|
|
|
|
fb_ad_en_15_0 <= '1' WHEN clut_fbee_rd = '1' ELSE
|
|
'1' WHEN clut_fa_rdl = '1' ELSE
|
|
'1' WHEN data_en_l_video_ctrl = '1' ELSE '0';
|
|
|
|
vd_vz <= vd_vz_i;
|
|
|
|
DFF_CLK0: PROCESS
|
|
BEGIN
|
|
WAIT UNTIL rising_edge(clk_ddr0);
|
|
vd_vz_i <= vd_vz_i(63 DOWNTO 0) & vdp_in(63 DOWNTO 0);
|
|
|
|
IF fifo_wre = '1' THEN
|
|
vdm_a <= vd_vz_i;
|
|
vdm_b <= vdm_a;
|
|
END IF;
|
|
END PROCESS DFF_CLK0;
|
|
|
|
DFF_CLK2: PROCESS
|
|
BEGIN
|
|
WAIT UNTIL rising_edge(clk_ddr2);
|
|
vdmp <= sr_vdmp;
|
|
END PROCESS DFF_CLK2;
|
|
|
|
DFF_CLK3: PROCESS
|
|
BEGIN
|
|
WAIT UNTIL rising_edge(clk_ddr3);
|
|
vdmp_i <= vdmp;
|
|
END PROCESS DFF_CLK3;
|
|
|
|
vdm <= vdmp_i(7 DOWNTO 4) WHEN clk_ddr3 = '1' ELSE vdmp_i(3 DOWNTO 0);
|
|
|
|
SHIFT_CLK0: PROCESS
|
|
VARIABLE tmp : std_logic_vector(4 DOWNTO 0);
|
|
BEGIN
|
|
WAIT UNTIL rising_edge(clk_ddr0);
|
|
tmp := sr_fifo_wre & tmp(4 DOWNTO 1);
|
|
fifo_wre <= tmp(0);
|
|
END PROCESS SHIFT_CLK0;
|
|
|
|
with vdm_sel select
|
|
vdm_c <= vdm_b WHEN x"0",
|
|
vdm_b(119 DOWNTO 0) & vdm_a(127 DOWNTO 120) WHEN x"1",
|
|
vdm_b(111 DOWNTO 0) & vdm_a(127 DOWNTO 112) WHEN x"2",
|
|
vdm_b(103 DOWNTO 0) & vdm_a(127 DOWNTO 104) WHEN x"3",
|
|
vdm_b(95 DOWNTO 0) & vdm_a(127 DOWNTO 96) WHEN x"4",
|
|
vdm_b(87 DOWNTO 0) & vdm_a(127 DOWNTO 88) WHEN x"5",
|
|
vdm_b(79 DOWNTO 0) & vdm_a(127 DOWNTO 80) WHEN x"6",
|
|
vdm_b(71 DOWNTO 0) & vdm_a(127 DOWNTO 72) WHEN x"7",
|
|
vdm_b(63 DOWNTO 0) & vdm_a(127 DOWNTO 64) WHEN x"8",
|
|
vdm_b(55 DOWNTO 0) & vdm_a(127 DOWNTO 56) WHEN x"9",
|
|
vdm_b(47 DOWNTO 0) & vdm_a(127 DOWNTO 48) WHEN x"A",
|
|
vdm_b(39 DOWNTO 0) & vdm_a(127 DOWNTO 40) WHEN x"B",
|
|
vdm_b(31 DOWNTO 0) & vdm_a(127 DOWNTO 32) WHEN x"C",
|
|
vdm_b(23 DOWNTO 0) & vdm_a(127 DOWNTO 24) WHEN x"D",
|
|
vdm_b(15 DOWNTO 0) & vdm_a(127 DOWNTO 16) WHEN x"E",
|
|
vdm_b(7 DOWNTO 0) & vdm_a(127 DOWNTO 8) WHEN x"F",
|
|
(OTHERS => 'X') WHEN OTHERS;
|
|
|
|
I_FIFO_DC0: lpm_fifo_dc0
|
|
PORT map(
|
|
aclr => fifo_clr_i,
|
|
data => vdm_c,
|
|
rdclk => clk_pixel_i,
|
|
rdreq => fifo_rd_req_512,
|
|
wrclk => clk_ddr0,
|
|
wrreq => fifo_wre,
|
|
q => fifo_d_out_512,
|
|
--rdempty =>, -- Not d.
|
|
unsigned(wrusedw) => fifo_mw
|
|
);
|
|
|
|
I_FIFO_DZ: lpm_fifoDZ
|
|
PORT map(
|
|
aclr => dop_fifo_clr,
|
|
clock => clk_pixel_i,
|
|
data => fifo_d_out_512,
|
|
rdreq => fifo_rd_req_128,
|
|
wrreq => fifo_rd_req_512,
|
|
q => fifo_d_out_128
|
|
);
|
|
|
|
I_VIDEO_CTRL: VIDEO_CTRL
|
|
PORT map(
|
|
clk_main => clk_main,
|
|
fb_cs_n(1) => fb_cs_n(1),
|
|
fb_cs_n(2) => fb_cs_n(2),
|
|
fb_wr_n => fb_wr_n,
|
|
fb_oe_n => fb_oe_n,
|
|
FB_SIZE(0) => fb_size0,
|
|
FB_SIZE(1) => fb_size1,
|
|
fb_adr => fb_adr,
|
|
CLK33M => clk_33m,
|
|
CLK25M => clk_25m,
|
|
blitter_run => blitter_run,
|
|
clk_video => clk_video,
|
|
vr_d => unsigned(vr_d),
|
|
vr_busy => vr_busy,
|
|
color8 => color8,
|
|
FBEE_CLUT_RD => clut_fbee_rd,
|
|
COLOR1 => COLOR1,
|
|
FALCON_CLUT_RDH => clut_fa_rdh,
|
|
FALCON_CLUT_RDL => clut_fa_rdl,
|
|
std_logic_vector(FALCON_CLUT_WR) => clut_fa_wr,
|
|
clut_st_rd => clut_st_rd,
|
|
std_logic_vector(clut_st_wr) => clut_st_wr,
|
|
std_logic_vector(CLUT_MUX_ADR) => clut_adr_mux,
|
|
hsync => hsync,
|
|
vsync => vsync,
|
|
blank_n => blank_n,
|
|
sync_n => sync_n,
|
|
pd_vga_n => pd_vga_n,
|
|
fifo_rde => fifo_rde,
|
|
color2 => color2,
|
|
color4 => color4,
|
|
clk_pixel => clk_pixel_i,
|
|
std_logic_vector(clut_off) => clut_off,
|
|
blitter_on => blitter_on,
|
|
std_logic_vector(video_ram_ctr) => video_ram_ctr,
|
|
video_mod_ta => video_mod_ta,
|
|
std_logic_vector(ccr) => ccr,
|
|
std_logic_vector(CCSEL) => CC_SEL,
|
|
std_logic_vector(FBEE_CLUT_WR) => clut_fbee_wr,
|
|
inter_zei => inter_zei,
|
|
dop_fifo_clr => dop_fifo_clr,
|
|
video_reconfig => video_reconfig,
|
|
vr_wr => vr_wr,
|
|
vr_rd => vr_rd,
|
|
fifo_clr => fifo_clr_i,
|
|
DATA_IN => unsigned(fb_ad_in),
|
|
std_logic_vector(DATA_OUT) => data_out_video_ctrl,
|
|
DATA_EN_H => data_en_h_video_ctrl,
|
|
DATA_EN_L => data_en_l_video_ctrl
|
|
);
|
|
END ARCHITECTURE;
|