586 lines
22 KiB
VHDL
586 lines
22 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part of the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides the package of the 'Firebee' ----
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---- computer. It is optimized for the use of an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion of the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is IN compa- ----
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---- rision to the first edition completely written IN VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 of the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed IN the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU General Public ----
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---- License along with this program; if not, write to the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release of the second edition.
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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PACKAGE firebee_pkg IS
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COMPONENT VIDEO_SYSTEM
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PORT(
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clk_main : IN STD_LOGIC;
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CLK_33M : IN STD_LOGIC;
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CLK_25M : IN STD_LOGIC;
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clk_video : IN STD_LOGIC;
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CLK_DDR3 : IN STD_LOGIC;
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CLK_DDR2 : IN STD_LOGIC;
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CLK_DDR0 : IN STD_LOGIC;
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CLK_PIXEL : OUT STD_LOGIC;
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vr_d : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
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vr_busy : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_EN_31_16 : OUT STD_LOGIC; -- Hi word.
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FB_AD_EN_15_0 : OUT STD_LOGIC; -- Low word.
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FB_ALE : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1);
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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fb_size1 : IN STD_LOGIC;
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fb_size0 : IN STD_LOGIC;
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vdp_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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VR_RD : OUT STD_LOGIC;
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VR_WR : OUT STD_LOGIC;
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video_reconfig : OUT STD_LOGIC;
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red : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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green : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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blue : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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vsync : OUT STD_LOGIC;
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hsync : OUT STD_LOGIC;
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sync_n : OUT STD_LOGIC;
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blank_n : OUT STD_LOGIC;
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pd_vga_n : OUT STD_LOGIC;
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video_mod_ta : OUT STD_LOGIC;
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vd_vz : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
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sr_fifo_wre : IN STD_LOGIC;
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sr_vdmp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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fifo_mw : OUT UNSIGNED (8 DOWNTO 0);
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vdm_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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video_ram_ctr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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fifo_clr : OUT STD_LOGIC;
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vdm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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blitter_run : IN STD_LOGIC;
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blitter_on : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT VIDEO_CTRL
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PORT(
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clk_main : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR (2 DOWNTO 1);
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fb_wr_n : IN STD_LOGIC;
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fb_oe_n : IN STD_LOGIC;
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fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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clk33m : IN STD_LOGIC;
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clk25m : IN STD_LOGIC;
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blitter_run : IN STD_LOGIC;
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clk_video : IN STD_LOGIC;
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vr_d : IN UNSIGNED (8 DOWNTO 0);
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vr_busy : IN STD_LOGIC;
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color8 : OUT STD_LOGIC;
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fbee_clut_rd : OUT STD_LOGIC;
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color1 : OUT STD_LOGIC;
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falcon_clut_rdh : OUT STD_LOGIC;
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falcon_clut_rdl : OUT STD_LOGIC;
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falcon_clut_wr : OUT UNSIGNED(3 DOWNTO 0);
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clut_st_rd : OUT STD_LOGIC;
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clut_st_wr : OUT UNSIGNED (1 DOWNTO 0);
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clut_mux_adr : OUT UNSIGNED (3 DOWNTO 0);
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hsync : OUT STD_LOGIC;
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vsync : OUT STD_LOGIC;
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blank_n : OUT STD_LOGIC;
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sync_n : OUT STD_LOGIC;
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pd_vga_n : OUT STD_LOGIC;
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FIFO_RDE : OUT STD_LOGIC;
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COLOR2 : OUT STD_LOGIC;
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COLOR4 : OUT STD_LOGIC;
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CLK_PIXEL : OUT STD_LOGIC;
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CLUT_OFF : OUT UNSIGNED (3 DOWNTO 0);
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blitter_on : OUT STD_LOGIC;
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video_ram_ctr : OUT UNSIGNED (15 DOWNTO 0);
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video_mod_ta : OUT STD_LOGIC;
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CCR : OUT UNSIGNED (23 DOWNTO 0);
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CCSEL : OUT UNSIGNED (2 DOWNTO 0);
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FBEE_CLUT_WR : OUT UNSIGNED (3 DOWNTO 0);
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INTER_ZEI : OUT STD_LOGIC;
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DOP_FIFO_CLR : OUT STD_LOGIC;
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video_reconfig : OUT STD_LOGIC;
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VR_WR : OUT STD_LOGIC;
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VR_RD : OUT STD_LOGIC;
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fifo_clr : OUT STD_LOGIC;
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DATA_IN : IN UNSIGNED (31 DOWNTO 0);
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DATA_OUT : OUT UNSIGNED (31 DOWNTO 0);
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DATA_EN_H : OUT STD_LOGIC;
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DATA_EN_L : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT DDR_CTRL is
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PORT(
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clk_main : IN STD_LOGIC;
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ddr_sync_66m : IN STD_LOGIC;
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fb_adr : IN UNSIGNED (31 DOWNTO 0);
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fb_cs1_n : IN STD_LOGIC;
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fb_oe_n : IN STD_LOGIC;
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fb_size0 : IN STD_LOGIC;
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fb_size1 : IN STD_LOGIC;
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fb_ale : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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fifo_clr : IN STD_LOGIC;
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vram_control : IN UNSIGNED (15 DOWNTO 0);
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blitter_adr : IN UNSIGNED (31 DOWNTO 0);
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blitter_sig : IN STD_LOGIC;
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blitter_wr : IN STD_LOGIC;
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ddrclk0 : IN STD_LOGIC;
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clk_33m : IN STD_LOGIC;
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fifo_mw : IN UNSIGNED (8 DOWNTO 0);
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va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips
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vwe_n : OUT STD_LOGIC; -- video memory write enable
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vras_n : OUT STD_LOGIC; -- video memory RAS
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vcs_n : OUT STD_LOGIC; -- video memory chip SELECT
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vcke : OUT STD_LOGIC; -- video memory clock enable
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vcas_n : OUT STD_LOGIC; -- video memory CAS
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fb_le : OUT UNSIGNED (3 DOWNTO 0);
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fb_vdoe : OUT UNSIGNED (3 DOWNTO 0);
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sr_fifo_wre : OUT STD_LOGIC;
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sr_ddr_fb : OUT STD_LOGIC;
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sr_ddr_wr : OUT STD_LOGIC;
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sr_ddrwr_d_sel : OUT STD_LOGIC;
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sr_vdmp : OUT UNSIGNED (7 DOWNTO 0);
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video_ddr_ta : OUT STD_LOGIC;
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sr_blitter_dack : OUT STD_LOGIC;
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ba : OUT UNSIGNED (1 DOWNTO 0);
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ddrwr_d_sel1 : OUT STD_LOGIC;
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vdm_sel : OUT UNSIGNED (3 DOWNTO 0);
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data_in : IN UNSIGNED (31 DOWNTO 0);
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data_out : OUT UNSIGNED (31 DOWNTO 16);
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data_en_h : OUT STD_LOGIC;
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data_en_l : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT INTHANDLER
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PORT(
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clk_main : IN STD_LOGIC;
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reset_n : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1);
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fb_size0 : IN STD_LOGIC;
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fb_size1 : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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fb_oe_n : IN STD_LOGIC;
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FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_EN_31_24 : OUT STD_LOGIC;
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FB_AD_EN_23_16 : OUT STD_LOGIC;
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FB_AD_EN_15_8 : OUT STD_LOGIC;
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FB_AD_EN_7_0 : OUT STD_LOGIC;
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PIC_INT : IN STD_LOGIC;
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E0_INT : IN STD_LOGIC;
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DVI_INT : IN STD_LOGIC;
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pci_inta_n : IN STD_LOGIC;
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pci_intb_n : IN STD_LOGIC;
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pci_intc_n : IN STD_LOGIC;
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pci_intd_n : IN STD_LOGIC;
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mfp_int_n : IN STD_LOGIC;
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DSP_INT : IN STD_LOGIC;
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vsync : IN STD_LOGIC;
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hsync : IN STD_LOGIC;
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DRQ_DMA : IN STD_LOGIC;
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irq_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 2);
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INT_HANDLER_TA : OUT STD_LOGIC;
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FBEE_CONF : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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TIN0 : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT FBEE_DMA is
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PORT(
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RESET : IN STD_LOGIC;
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clk_main : IN STD_LOGIC;
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CLK_FDC : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
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FB_ALE : IN STD_LOGIC;
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fb_size : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1);
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_EN_31_24 : OUT STD_LOGIC;
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FB_AD_EN_23_16 : OUT STD_LOGIC;
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FB_AD_EN_15_8 : OUT STD_LOGIC;
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FB_AD_EN_7_0 : OUT STD_LOGIC;
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ACSI_DIR : OUT STD_LOGIC;
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ACSI_D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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ACSI_D_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ACSI_D_EN : OUT STD_LOGIC;
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ACSI_CSn : OUT STD_LOGIC;
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ACSI_A1 : OUT STD_LOGIC;
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ACSI_RESETn : OUT STD_LOGIC;
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ACSI_DRQn : IN STD_LOGIC;
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ACSI_ACKn : OUT STD_LOGIC;
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DATA_IN_FDC : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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DATA_IN_SCSI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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DATA_OUT_FDC_SCSI : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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DMA_DRQ_IN : IN STD_LOGIC; -- From 1772.
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DMA_DRQ_OUT : OUT STD_LOGIC; -- To Interrupt handler.
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DMA_DRQ11 : OUT STD_LOGIC;
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SCSI_DRQ : IN STD_LOGIC;
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SCSI_DACKn : OUT STD_LOGIC;
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SCSI_INT : IN STD_LOGIC;
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SCSI_CSn : OUT STD_LOGIC;
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SCSI_CS : OUT STD_LOGIC;
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CA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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FLOPPY_HD_DD : IN STD_LOGIC;
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WDC_BSL0 : OUT STD_LOGIC;
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FDC_CSn : OUT STD_LOGIC;
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FDC_WRn : OUT STD_LOGIC;
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FD_INT : IN STD_LOGIC;
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IDE_INT : IN STD_LOGIC;
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DMA_CS : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT IDE_CF_SD_ROM is
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PORT(
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RESET : IN STD_LOGIC;
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clk_main : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(19 DOWNTO 5);
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FB_CS1n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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FB_B0 : IN STD_LOGIC;
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FB_B1 : IN STD_LOGIC;
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FBEE_CONF : IN STD_LOGIC_VECTOR(31 DOWNTO 30);
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RP_UDSn : OUT STD_LOGIC;
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RP_LDSn : OUT STD_LOGIC;
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SD_CLK : OUT STD_LOGIC;
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SD_D0 : IN STD_LOGIC;
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SD_D1 : IN STD_LOGIC;
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SD_D2 : IN STD_LOGIC;
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SD_CD_D3_IN : IN STD_LOGIC;
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SD_CD_D3_OUT : OUT STD_LOGIC;
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SD_CD_D3_EN : OUT STD_LOGIC;
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SD_CMD_D1_IN : IN STD_LOGIC;
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SD_CMD_D1_OUT : OUT STD_LOGIC;
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SD_CMD_D1_EN : OUT STD_LOGIC;
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SD_CARD_DETECT : IN STD_LOGIC;
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SD_WP : IN STD_LOGIC;
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IDE_RDY : IN STD_LOGIC;
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IDE_WRn : buffer STD_LOGIC;
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IDE_RDn : OUT STD_LOGIC;
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IDE_CSn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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IDE_DRQn : OUT STD_LOGIC;
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IDE_CF_TA : OUT STD_LOGIC;
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ROM4n : OUT STD_LOGIC;
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ROM3n : OUT STD_LOGIC;
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CF_WP : IN STD_LOGIC;
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CF_CSn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT FBEE_BLITTER is
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PORT(
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reset_n : IN STD_LOGIC;
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clk_main : IN STD_LOGIC;
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CLK_DDR0 : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_ALE : IN STD_LOGIC;
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fb_size1 : IN STD_LOGIC;
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fb_size0 : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1);
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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DATA_EN : OUT STD_LOGIC;
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blitter_on : IN STD_LOGIC;
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BLITTER_DIN : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
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BLITTER_DACK_SR : IN STD_LOGIC;
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blitter_run : OUT STD_LOGIC;
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BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
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BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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BLITTER_SIG : OUT STD_LOGIC;
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BLITTER_WR : OUT STD_LOGIC;
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BLITTER_TA : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT DSP is
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PORT(
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CLK_33M : IN STD_LOGIC;
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clk_main : IN STD_LOGIC;
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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FB_CS1n : IN STD_LOGIC;
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FB_CS2n : IN STD_LOGIC;
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fb_size0 : IN STD_LOGIC;
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fb_size1 : IN STD_LOGIC;
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FB_BURSTn : IN STD_LOGIC;
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fb_adr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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RESETn : IN STD_LOGIC;
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FB_CS3n : IN STD_LOGIC;
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SRCSn : OUT STD_LOGIC;
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SRBLEn : OUT STD_LOGIC;
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SRBHEn : OUT STD_LOGIC;
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SRWEn : OUT STD_LOGIC;
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SROEn : OUT STD_LOGIC;
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DSP_INT : OUT STD_LOGIC;
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DSP_TA : OUT STD_LOGIC;
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FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FB_AD_EN : OUT STD_LOGIC;
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IO_IN : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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IO_OUT : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
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IO_EN : OUT STD_LOGIC;
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SRD_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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SRD_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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SRD_EN : OUT STD_LOGIC
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);
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END COMPONENT DSP;
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COMPONENT WF2149IP_TOP_SOC
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PORT(
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SYS_CLK : IN STD_LOGIC;
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RESETn : IN STD_LOGIC;
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WAV_CLK : IN STD_LOGIC;
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SELn : IN STD_LOGIC;
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BDIR : IN STD_LOGIC;
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BC2, BC1 : IN STD_LOGIC;
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A9n, A8 : IN STD_LOGIC;
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DA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DA_EN : OUT STD_LOGIC;
|
|
|
|
IO_A_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
IO_A_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
IO_A_EN : OUT STD_LOGIC;
|
|
IO_B_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
IO_B_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
IO_B_EN : OUT STD_LOGIC;
|
|
|
|
OUT_A : OUT STD_LOGIC;
|
|
OUT_B : OUT STD_LOGIC;
|
|
OUT_C : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT WF2149IP_TOP_SOC;
|
|
|
|
COMPONENT WF68901IP_TOP_SOC
|
|
PORT (
|
|
CLK : IN STD_LOGIC;
|
|
RESETn : IN STD_LOGIC;
|
|
DSn : IN STD_LOGIC;
|
|
CSn : IN STD_LOGIC;
|
|
RWn : IN STD_LOGIC;
|
|
DTACKn : OUT STD_LOGIC;
|
|
RS : IN STD_LOGIC_VECTOR(5 DOWNTO 1);
|
|
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_EN : OUT STD_LOGIC;
|
|
GPIP_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
GPIP_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
GPIP_EN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
IACKn : IN STD_LOGIC;
|
|
IEIn : IN STD_LOGIC;
|
|
IEOn : OUT STD_LOGIC;
|
|
irq_n : OUT STD_LOGIC;
|
|
XTAL1 : IN STD_LOGIC;
|
|
TAI : IN STD_LOGIC;
|
|
TBI : IN STD_LOGIC;
|
|
TAO : OUT STD_LOGIC;
|
|
TBO : OUT STD_LOGIC;
|
|
TCO : OUT STD_LOGIC;
|
|
TDO : OUT STD_LOGIC;
|
|
RC : IN STD_LOGIC;
|
|
TC : IN STD_LOGIC;
|
|
SI : IN STD_LOGIC;
|
|
SO : OUT STD_LOGIC;
|
|
SO_EN : OUT STD_LOGIC;
|
|
RRn : OUT STD_LOGIC;
|
|
TRn : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT WF68901IP_TOP_SOC;
|
|
|
|
COMPONENT WF6850IP_TOP_SOC
|
|
PORT (
|
|
CLK : IN STD_LOGIC;
|
|
RESETn : IN STD_LOGIC;
|
|
|
|
CS2n, CS1, CS0 : IN STD_LOGIC;
|
|
E : IN STD_LOGIC;
|
|
RWn : IN STD_LOGIC;
|
|
RS : IN STD_LOGIC;
|
|
|
|
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_EN : OUT STD_LOGIC;
|
|
|
|
TXCLK : IN STD_LOGIC;
|
|
RXCLK : IN STD_LOGIC;
|
|
RXDATA : IN STD_LOGIC;
|
|
CTSn : IN STD_LOGIC;
|
|
DCDn : IN STD_LOGIC;
|
|
|
|
irq_n : OUT STD_LOGIC;
|
|
TXDATA : OUT STD_LOGIC;
|
|
RTSn : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT WF6850IP_TOP_SOC;
|
|
|
|
COMPONENT WF5380_TOP_SOC
|
|
PORT (
|
|
CLK : IN STD_LOGIC;
|
|
RESETn : IN STD_LOGIC;
|
|
ADR : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
|
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_EN : OUT STD_LOGIC;
|
|
CSn : IN STD_LOGIC;
|
|
RDn : IN STD_LOGIC;
|
|
WRn : IN STD_LOGIC;
|
|
EOPn : IN STD_LOGIC;
|
|
DACKn : IN STD_LOGIC;
|
|
DRQ : OUT STD_LOGIC;
|
|
INT : OUT STD_LOGIC;
|
|
READY : OUT STD_LOGIC;
|
|
DB_INn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DB_OUTn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DB_EN : OUT STD_LOGIC;
|
|
DBP_INn : IN STD_LOGIC;
|
|
DBP_OUTn : OUT STD_LOGIC;
|
|
DBP_EN : OUT STD_LOGIC;
|
|
RST_INn : IN STD_LOGIC;
|
|
RST_OUTn : OUT STD_LOGIC;
|
|
RST_EN : OUT STD_LOGIC;
|
|
BSY_INn : IN STD_LOGIC;
|
|
BSY_OUTn : OUT STD_LOGIC;
|
|
BSY_EN : OUT STD_LOGIC;
|
|
SEL_INn : IN STD_LOGIC;
|
|
SEL_OUTn : OUT STD_LOGIC;
|
|
SEL_EN : OUT STD_LOGIC;
|
|
ACK_INn : IN STD_LOGIC;
|
|
ACK_OUTn : OUT STD_LOGIC;
|
|
ACK_EN : OUT STD_LOGIC;
|
|
ATN_INn : IN STD_LOGIC;
|
|
ATN_OUTn : OUT STD_LOGIC;
|
|
ATN_EN : OUT STD_LOGIC;
|
|
REQ_INn : IN STD_LOGIC;
|
|
REQ_OUTn : OUT STD_LOGIC;
|
|
REQ_EN : OUT STD_LOGIC;
|
|
IOn_IN : IN STD_LOGIC;
|
|
IOn_OUT : OUT STD_LOGIC;
|
|
IO_EN : OUT STD_LOGIC;
|
|
CDn_IN : IN STD_LOGIC;
|
|
CDn_OUT : OUT STD_LOGIC;
|
|
CD_EN : OUT STD_LOGIC;
|
|
MSG_INn : IN STD_LOGIC;
|
|
MSG_OUTn : OUT STD_LOGIC;
|
|
MSG_EN : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT WF5380_TOP_SOC;
|
|
|
|
COMPONENT WF1772IP_TOP_SOC
|
|
PORT (
|
|
CLK : IN STD_LOGIC;
|
|
RESETn : IN STD_LOGIC;
|
|
CSn : IN STD_LOGIC;
|
|
RWn : IN STD_LOGIC;
|
|
A1, A0 : IN STD_LOGIC;
|
|
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
DATA_EN : OUT STD_LOGIC;
|
|
RDn : IN STD_LOGIC;
|
|
TR00n : IN STD_LOGIC;
|
|
IPn : IN STD_LOGIC;
|
|
WPRTn : IN STD_LOGIC;
|
|
DDEn : IN STD_LOGIC;
|
|
HDTYPE : IN STD_LOGIC;
|
|
MO : OUT STD_LOGIC;
|
|
WG : OUT STD_LOGIC;
|
|
WD : OUT STD_LOGIC;
|
|
STEP : OUT STD_LOGIC;
|
|
DIRC : OUT STD_LOGIC;
|
|
DRQ : OUT STD_LOGIC;
|
|
INTRQ : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT WF1772IP_TOP_SOC;
|
|
|
|
COMPONENT RTC is
|
|
PORT(
|
|
clk_main : IN STD_LOGIC;
|
|
fb_adr : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
|
|
FB_CS1n : IN STD_LOGIC;
|
|
fb_size0 : IN STD_LOGIC;
|
|
fb_size1 : IN STD_LOGIC;
|
|
fb_wr_n : IN STD_LOGIC;
|
|
fb_oe_n : IN STD_LOGIC;
|
|
FB_AD_IN : IN STD_LOGIC_VECTOR(23 DOWNTO 16);
|
|
FB_AD_OUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 16);
|
|
FB_AD_EN_23_16 : OUT STD_LOGIC;
|
|
PIC_INT : IN STD_LOGIC
|
|
);
|
|
END COMPONENT RTC;
|
|
END firebee_pkg;
|