48 lines
1.1 KiB
VHDL
48 lines
1.1 KiB
VHDL
library work;
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use work.firebee_pkg.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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-- DDR ram simulation for Firebee video RAM
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entity ddr_ram_model is
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port (
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signal CK : in std_logic;
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signal CKE : in std_logic;
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signal CSn : in std_logic;
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signal RASn : in std_logic;
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signal CASn : in std_logic;
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signal WEn : in std_logic;
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signal LDM : in std_logic;
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signal UDM : in std_logic;
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signal BA : in std_logic_vector(1 downto 0);
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signal A : in std_logic_vector(12 downto 0);
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signal DQ : inout std_logic_vector(7 downto 0);
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signal LDQS : inout std_logic;
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signal UDQS : inout std_logic
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);
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end entity ddr_ram_model;
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architecture behav of ddr_ram_model is
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signal opcode : std_logic_vector(14 downto 0);
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signal command : std_logic_vector(5 downto 0);
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signal OLD_CKE : std_logic := 'X';
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begin
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opcode <= BA & A(10) & A(12 downto 11) & A(9 downto 0);
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command <= OLD_CKE & CKE & CSn & RASn & CASn & WEn;
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clock_hi : process
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begin
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wait until rising_edge(CK) and CK = '1';
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end process;
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clock_lo : process
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begin
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wait until falling_edge(CK) and CK = '0';
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end process;
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end behav;
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