186 lines
7.4 KiB
Plaintext
186 lines
7.4 KiB
Plaintext
Done:
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02.01.09
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- Started work on pipeline (FE, FE2, DC, AG, EX)
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- Program counter counts linearly
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- Initial program memory holds program data
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- Started work on instruction decoder
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03.01.09
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- Jump instructions work (with flushing of the pipeline)
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- First version of AGU implemented
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- Detection of double word instructions
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- Initial version of global register file
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04.01.09
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- Included hardware stack
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- Finished support for JSR and JSCC instructions
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- RTI/RTS work
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- ANDI/ORI work
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- Initial work on REP instruction
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10.01.09
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- Initial suppurt for X memory accesses. One stall cycle is introduced when
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accessing the X memory.
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- Finished implementation of REP instruction. Reading number of loops from
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registers is still missing.
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- Initial support for DO loops.
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- Preventing to write the R registers when stalling occurs or a jump is
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performed
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11.01.09
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- Finished implementation of DO loops (stop looping at the end)
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- Nested loops work
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- Single instruction loops work
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- ENDDO instruction implemented (very much the same as usual end of the loop)
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12.01.09
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- Included Y memory and its addressing modes for REP and DO instruction.
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- Setup of a sheet showing which types of which instructions have been
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implemented and how many clock cycles are needed.
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16.01.09
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- Integration of LUA instruction.
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24.01.09
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- Integrated different addressing schemes (immediate short, immediate long,
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absolute address)
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- Integration and test of MOVE(C) instruction. Some modes missing (writing to
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memory)
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- Testing of Y memory read accesses.
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26.01.09
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- Continued testing of different addressing modes.
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- Decoding for first parallel move operations.
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01.02.09
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- Moved memory components to an extra entity (memory_management)
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- Writing to internal X and Y memory supported. Problems are possible for
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reading the same address one instruction after writing at the same address!
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- Included ALU registers (x,y,a,b) into register file
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- Integration of x/y/l bus started
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03.02.09
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- Continued testing of parallel moves (there are quite a few cases!)
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07.02.09
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- Fixed REP instruction for instructions that are causing a stall due to
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a memory read
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- Fixed fetching from program data when stalling.
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- Fixed detection of double word instruction, when previous instruction
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used the AGU as well (forgot instruction word in sensitivity list).
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- Continued testing of parallel moves.
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- First synthesis run: Changed RAM description to map to BRAMs, removed
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latches, and many things are still missing, post-synthesis results:
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- Xilinx Spartan3A, Speed-Grade -4
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- 1488 FFs
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- 4657 4-Input LUTs
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- 3 BRAMs
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- 71.08 MHz
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08.02.09
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- Implemented second address generation unit in order to access X and Y
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memory at the same time
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- Implemented reverse carry addressing modes for FFT addressing
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- Started implementation of modulo addressing.
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- Set M0-M7 to -1 in reset.
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- Downloaded the assembler for DSP56300. I hope to use it in order to
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generate the content of the program memory automatically, which will
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boost the testing speed...
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- Encoding each instruction to test by hand just sucks. I think I will
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integrate some bootloader in order to use the LOD files from the
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assembler to initiate the RAMs.
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- Implementation of data shifter and limiter (when accessing a or b and
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giving the result to XDB or YDB). Needs testing.
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- Integration for L: addressing modes. Needs nesting.
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10.02.09
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- Fixed decoding of X: and Y: adressing mode (collided with L: adressing)
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- L: adressing modes are working
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14.02.09
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- Implemented BCHG,BCLR,BSET,BTST,JCLR,JSCLR,JSET,JSSET. A lot of testing
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is still needed. Peripheral register accesses are still missing.
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- Second synthesis run: Removed new latches again.
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, many things are still missing, post-synthesis results:
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- Xilinx Spartan3A, Speed-Grade -4
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- 1519 FFs
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- 6210 4-Input LUTs
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- 3 BRAMs
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- 51.68 MHz
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* Critical path for JSCLR/JSSET=> read limited a/b, go through bit modify
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unit, test whether condition met, push data to stack. Reading of
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limited A/B is probably a bug (DSP56001 UM says CCR is not changed,
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in DSP56300 simulator the flag is set when reading a/b!!).
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15.02.09
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- Started implementing the ALU.
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- ABS works.
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- MPY(R), MAC(R) implemented, rounding is missing.
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- Clock frequency dropped to 41 MHz, but the critical path is not caused by
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the MAC in the ALU! The multiplier is composed of four 18x18 multipliers
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and still seems to be very fast!
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16.02.09
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- Implemented decoding and controlling of ALU for
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ADC, ADD, ADDL, ADDR, AND, ASL, ASR, CLR, CMP, CMPM, EOR, NEG, NOT, OR
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Still missing ALU instructions:
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DIV, NORM, RND, ROL, ROR, SBC, SUB, SUBL, SUBR, Tcc, TFR, TST
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Except for DIV and NORM this will be straight forward.
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- Other things that need to be done :
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* Adress Generation Unit does not support modulo addressing.
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* MOVEP/MOVEM/STOP/WAIT/ILLEGAL/RESET/SWI
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* Interrupts
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* External memory accesses
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* Peripheral devices (SCI, SSI, Host port)
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17.02.09
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- Implemented decoding and controlling of ALU instructions for
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RND, ROL, ROR, SBC, SUB, SUBL, SUBR, TFR, TST
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Still missing ALU instructions:
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DIV, NORM, Tcc
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08.03.09
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- Forgot integration of LSR and LSL instructions. TBD.
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- Started integration of Condition flag generation in ALU.
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- New synthesis run with ALU, register balancing:
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- Xilinx Spartan3A, Speed-Grade -4
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- 3115 FFs
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- 7417 4-Input LUTs
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- 3 BRAMs
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- 39.47 MHz
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13.03.09
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- Integrated decoding of LSL/LSR instructions.
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- Integrated rotating function into ALU.
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- Included convergent rounding functionality into ALU.
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- Implemented Tcc instruction.
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- Implemented DIV instruction.
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15.03.09
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- Tested ABS,ADC,ADD,ADDL,ADDR,AND,ASL,ASR,CLR,CMP,CMPM,DIV,EOR,
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LSL,LSR,MPY,MPYR,MAC,MACR,NEG,NOT,OR
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- Bugs fixed:
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- Detection of overflow corrected when negating most negative
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value $80 000000 000000.
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- Decoding of ADC and TFR clarified.
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- Overflow flag generation when left shifting of 56 bit values.
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- For logical operations the flag generation relied on the adder
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output which was wrong. Now relies on the Logical unit output.
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- Decoding of CMPM clarified in order not to conflict with NOT.
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- Shifter was used for CMP(M) instructions, which is wrong.
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- Hopefully calculation of carry and overflow flag work correctly now...
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- MPY/MAC write result back.
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- Limit Flag is not cleared by the ALU anymore (has to be reset by the
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user!).
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16.03.09
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- Tested RND
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- Bugs fixed:
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- Simulator seems to misunderstand the X"1000000" where the first digit
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represents a single bit. Comparing against this value fixed! RND works.
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17.03.09
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- Tested ROR,ROL,SBC,SUB,SUBL,SUBR,TCC,TFR,TST,NORM
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- Integrated logic for NORM instruction support.
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- ALU is complete now!
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- Bugs fixed:
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- Fixed setting of CCR for ROL/ROR
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- TCC didn't read register through ALU
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- Known bugs:
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- Carry calculation for SBC is still buggy
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- New synthesis run with ALU, register balancing:
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- Xilinx Spartan3A, Speed-Grade -4
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- 1801 FFs
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- 7407 4-Input LUTs
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- 3 BRAMs
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- 30.84 MHz
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Critical path is in the ALU (multiplication, adding, rounding, zero-flag
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calculation). I wonder why the values changed like that since the
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last synthesis run.
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26.03.09
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- Included support for modulo addressing in AGUs. This allows for the
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integration of ring buffers. Now 7900 LUTs.
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18.05.10
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- Commenting of code.
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- Added second memory port for p-mem (needed for movem-instruction)
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