228 lines
8.0 KiB
ArmAsm
228 lines
8.0 KiB
ArmAsm
/*
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* INIT ACR and MMU
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*/
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#include "startcf.h"
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#ifdef MACHINE_FIREBEE
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#include "firebee.h"
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#endif /* MACHINE_FIREBEE */
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#ifdef MACHINE_M5484LITE
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#include "m5484l.h"
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#endif /* MACHINE_M5484LITE */
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.extern _rt_vbr
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.extern _rt_cacr
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.extern _rt_asid
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.extern _rt_acr0
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.extern _rt_acr1
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.extern _rt_acr2
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.extern _rt_acr3
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.extern _rt_mmubar
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.extern ___MMUBAR
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.extern cpusha
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.extern _video_tlb
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.extern _video_sbt
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.extern __TOS
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/* Register read/write macros */
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#define MCF_MMU_MMUCR __MMUBAR
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#define MCF_MMU_MMUOR __MMUBAR+0x04
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#define MCF_MMU_MMUSR __MMUBAR+0x08
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#define MCF_MMU_MMUAR __MMUBAR+0x10
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#define MCF_MMU_MMUTR __MMUBAR+0x14
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#define MCF_MMU_MMUDR __MMUBAR+0x18
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/* Bit definitions and macros for MCF_MMU_MMUCR */
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#define MCF_MMU_MMUCR_EN (0x1)
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#define MCF_MMU_MMUCR_ASM (0x2)
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/* Bit definitions and macros for MCF_MMU_MMUOR */
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#define MCF_MMU_MMUOR_UAA (0x1)
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#define MCF_MMU_MMUOR_ACC (0x2)
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#define MCF_MMU_MMUOR_RW (0x4)
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#define MCF_MMU_MMUOR_ADR (0x8)
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#define MCF_MMU_MMUOR_ITLB (0x10)
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#define MCF_MMU_MMUOR_CAS (0x20)
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#define MCF_MMU_MMUOR_CNL (0x40)
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#define MCF_MMU_MMUOR_CA (0x80)
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#define MCF_MMU_MMUOR_STLB (0x100)
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#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
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/* Bit definitions and macros for MCF_MMU_MMUSR */
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#define MCF_MMU_MMUSR_HIT (0x2)
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#define MCF_MMU_MMUSR_WF (0x8)
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#define MCF_MMU_MMUSR_RF (0x10)
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#define MCF_MMU_MMUSR_SPF (0x20)
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/* Bit definitions and macros for MCF_MMU_MMUAR */
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#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_MMU_MMUTR */
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#define MCF_MMU_MMUTR_V (0x1)
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#define MCF_MMU_MMUTR_SG (0x2)
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#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
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#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
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/* Bit definitions and macros for MCF_MMU_MMUDR */
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#define MCF_MMU_MMUDR_LK (0x2)
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#define MCF_MMU_MMUDR_X (0x4)
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#define MCF_MMU_MMUDR_W (0x8)
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#define MCF_MMU_MMUDR_R (0x10)
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#define MCF_MMU_MMUDR_SP (0x20)
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#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
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#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
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#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
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#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V)
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#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
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#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
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#define writethrough_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
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#define copyback_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
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#define nocache_precise_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
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.global _mmu_init
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.global _mmutr_miss
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//
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// to avoid chicken and egg situations, we need to make sure that MMU TLB miss exceptions do not end up in a memory
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// area that in turn cause a TLB miss exception themself after the MMU is enabled. At least the exception handler must live
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// in an area that's either covered by one of the ACR's or a locked MMU TLB entry. This is especially important when we link
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// BaS for RAM.
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//
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.text
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_mmu_init:
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move.l d3,-(sp) // Backup registers
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move.l d2,-(sp)
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clr.l d0
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movec d0,ASID // ASID always 0
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move.l d0,_rt_asid // save shadow register
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move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff
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movec d0,ACR0
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move.l d0,_rt_acr0 // save shadow register
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move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff
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movec d0,ACR1
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move.l d0,_rt_acr1 // save shadow register
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move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff
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movec d0,ACR2
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move.l d0,_rt_acr2 // save shadow register
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clr.l d0 // acr3 off
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movec d0,ACR3
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move.l d0,_rt_acr3 // save shadow register
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move.l #__MMUBAR+1,d0
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movec d0,MMUBAR // set MMUBAR
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move.l d0,_rt_mmubar // save shadow register
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nop
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move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries,
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move.l d0,MCF_MMU_MMUOR
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nop
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// 0000'0000 - 000F'FFFF (first megabyte of physical memory) locked virtual = physical
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moveq.l #0x00000000|std_mmutr,d0
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moveq.l #0x00000000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
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moveq.l #mmuord_d,d2 // MMU update data
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moveq.l #mmuord_i,d3 // MMU update instruction
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // MMU update data
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move.l d3,MCF_MMU_MMUOR // MMU update instruction
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// 00D0'0000 - 0x00DF'FFFF (last megabyte of ST RAM = Falcon video memory) locked ID=6
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// mapped to physical address 60D0'0000 (FPGA video memory)
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// video ram: read write execute normal write true
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#ifdef MACHINE_FIREBEE
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move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0
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move.l #0x60d00000|writethrough_mmudr|MCF_MMU_MMUDR_LK,d1
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // MMU update data
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move.l #0x00d00000|std_mmutr,d0
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move.l d3,MCF_MMU_MMUOR // MMU update instruction
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move.l #0x2000,d0
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move.l d0,_video_tlb // set page as video page
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clr.l _video_sbt // clear time
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#endif /* MACHINE_FIREBEE */
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// Make the TOS (in SDRAM) read-only
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// this maps virtual 0x00E0'0000-0x00EF'FFFF to the same physical address
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move.l #__TOS+std_mmutr,d0
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move.l #__TOS+copyback_mmudr+MCF_MMU_MMUDR_LK,d1
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht
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move.l d3,MCF_MMU_MMUOR // setzen
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// 00f0'0000 locked
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// this maps virtual 0x00F0'0000 - 0x00FF'FFFF to physical 0xFFF0'0000 - 0xFFFF'FFFF effectively making I/O area
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// accesses ST-compatible (just the same what Atari made for TT and Falcon). This does not get mapped for the
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// m5484LITE boards which enables us to later act on I/O access attempts during a page miss exception
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#ifdef MACHINE_FIREBEE
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move.l #0x00f00000|std_mmutr,d0
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move.l #0xfff00000|nocache_precise_mmudr|MCF_MMU_MMUDR_LK,d1
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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#endif /* MACHINE_FIREBEE */
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// 1ff0'0000 locked
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// maps virtual 0x1FF0'0000 - 0x1FFF'FFFF to the same physical address
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0 // last MB of physical RAM reserved for BaS
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// move.l #0x1FF00000|std_mmutr,d0 // last megabyte of physical RAM. Reserved for BaS
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | copyback_mmudr | MCF_MMU_MMUDR_LK,d1
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// move.l #0x1FF00000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // setzen data
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move.l d3,MCF_MMU_MMUOR // setzen instr
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move.l (sp)+,d2 // Restore registers
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move.l (sp)+,d3
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rts
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/*
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* Everything else gets 1:1 mapped on miss
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*/
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_mmutr_miss:
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lea -4 * 4(sp),sp
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movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers
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move.l d0,-(sp)
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pea MISS_text
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jsr _xprintf
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addq.l #8,sp
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movem.l (sp),d0-d1/a0-a1 // restore registers
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lea 4 * 4(sp),sp
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bsr cpusha // clear caches
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and.l #0xFFF00000,d0 // d0 is the address not found (MMUAR at the time of the exception)
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or.l #std_mmutr,d0 // mark shared and valid
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move.l d0,MCF_MMU_MMUTR // add to TLB
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and.l #0xFFF00000,d0 // mask out page
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or.l #copyback_mmudr,d0 // 1MB page size, cachable copyback, read, write, execute
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move.l d0,MCF_MMU_MMUDR // add physical address to TLB
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moveq.l #mmuord_d,d0 // MMU update data
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move.l d0,MCF_MMU_MMUOR // set
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moveq.l #mmuord_i,d0 // MMU update instruction
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move.l d0,MCF_MMU_MMUOR // set
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move.l (sp)+,d0 // restore register saved in acess
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rte
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.data
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MISS_text:
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.ascii "MMU TLB MISS at %p"
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.byte 13, 10, 0
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