127 lines
4.1 KiB
VHDL
127 lines
4.1 KiB
VHDL
-- megafunction wizard: %LPM_SHIFTREG%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: LPM_SHIFTREG
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-- ============================================================
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-- File Name: lpm_shiftreg6.vhd
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-- Megafunction Name(s):
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-- LPM_SHIFTREG
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--
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-- Simulation Library Files(s):
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-- lpm
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY lpm;
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USE lpm.all;
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ENTITY lpm_shiftreg6 IS
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PORT
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(
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clock : IN STD_LOGIC ;
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shiftin : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
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);
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END lpm_shiftreg6;
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ARCHITECTURE SYN OF lpm_shiftreg6 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
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COMPONENT lpm_shiftreg
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GENERIC (
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lpm_direction : STRING;
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lpm_type : STRING;
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lpm_width : NATURAL
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);
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PORT (
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clock : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
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shiftin : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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q <= sub_wire0(4 DOWNTO 0);
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LPM_SHIFTREG_component : LPM_SHIFTREG
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GENERIC MAP (
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lpm_direction => "RIGHT",
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lpm_type => "LPM_SHIFTREG",
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lpm_width => 5
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)
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PORT MAP (
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clock => clock,
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shiftin => shiftin,
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q => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
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-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
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-- Retrieval info: PRIVATE: ASET NUMERIC "0"
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-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
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-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
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-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
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-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
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-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
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-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
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-- Retrieval info: PRIVATE: SSET NUMERIC "0"
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-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
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-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
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-- Retrieval info: PRIVATE: nBit NUMERIC "5"
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-- Retrieval info: PRIVATE: new_diagram STRING "1"
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-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
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-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
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-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: lpm
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