137 lines
5.3 KiB
VHDL
137 lines
5.3 KiB
VHDL
-- megafunction wizard: %ALTDDIO_BIDIR%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: ALTDDIO_BIDIR
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-- ============================================================
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-- File Name: altddio_bidir0.vhd
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-- Megafunction Name(s):
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-- ALTDDIO_BIDIR
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY altddio_bidir0 IS
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PORT
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(
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datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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inclock : IN STD_LOGIC ;
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oe : IN STD_LOGIC ;
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outclock : IN STD_LOGIC ;
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combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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);
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END altddio_bidir0;
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ARCHITECTURE SYN OF altddio_bidir0 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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BEGIN
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combout <= sub_wire0(31 DOWNTO 0);
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dataout_h <= sub_wire1(31 DOWNTO 0);
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dataout_l <= sub_wire2(31 DOWNTO 0);
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ALTDDIO_BIDIR_component : ALTDDIO_BIDIR
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GENERIC MAP (
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extend_oe_disable => "OFF",
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implement_input_in_lcell => "ON",
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intended_device_family => "Cyclone III",
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invert_output => "OFF",
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lpm_hint => "UNUSED",
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lpm_type => "altddio_bidir",
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oe_reg => "UNREGISTERED",
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power_up_high => "OFF",
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width => 32
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)
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PORT MAP (
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datain_h => datain_h,
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datain_l => datain_l,
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oe => oe,
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outclock => outclock,
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inclock => inclock,
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combout => sub_wire0,
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dataout_h => sub_wire1,
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dataout_l => sub_wire2,
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padio => padio
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
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-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
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-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
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-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
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-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]"
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-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
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-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]"
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-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
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-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]"
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-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
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-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]"
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-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
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-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]"
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-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
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-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
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-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
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-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
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-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
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-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
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-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
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-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]"
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-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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