146 lines
2.0 KiB
Verilog
146 lines
2.0 KiB
Verilog
module lpm_ff0(
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clock,
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data,
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enable,
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q
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);
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input clock;
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input [31:0] data;
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input enable;
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output [31:0] q;
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reg [31:0] r_q = 32'd0;
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assign q = r_q;
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always @(posedge clock) begin
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if (enable) begin
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r_q <= data;
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end
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff1(
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clock,
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data,
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q
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);
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input clock;
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input [31:0] data;
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output [31:0] q;
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reg [31:0] r_q = 32'd0;
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assign q = r_q;
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always @(posedge clock) begin
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r_q <= data;
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff2(
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clock,
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data,
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q
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);
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input clock;
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input [127:0] data;
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output [127:0] q;
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reg [127:0] r_q = 128'd0;
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assign q = r_q;
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always @(posedge clock) begin
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r_q <= data;
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff3(
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clock,
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data,
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q
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);
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input clock;
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input [23:0] data;
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output [23:0] q;
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reg [23:0] r_q = 24'd0;
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assign q = r_q;
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always @(posedge clock) begin
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r_q <= data;
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff4(
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clock,
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data,
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q
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);
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input clock;
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input [15:0] data;
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output [15:0] q;
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reg [15:0] r_q = 16'd0;
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assign q = r_q;
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always @(posedge clock) begin
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r_q <= data;
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff5(
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clock,
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data,
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q
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);
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input clock;
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input [7:0] data;
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output [7:0] q;
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reg [7:0] r_q = 8'd0;
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assign q = r_q;
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always @(posedge clock) begin
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r_q <= data;
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////
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module lpm_ff6(
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clock,
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data,
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enable,
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q
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);
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input clock;
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input [127:0] data;
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input enable;
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output [127:0] q;
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reg [127:0] r_q = 128'd0;
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assign q = r_q;
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always @(posedge clock) begin
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if (enable) begin
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r_q <= data;
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end
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end
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endmodule
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